CN115207129B - Double-groove silicon carbide MOSFET with side wall gate resisting negative pressure and preparation method thereof - Google Patents
Double-groove silicon carbide MOSFET with side wall gate resisting negative pressure and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 102
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 101
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000009987 spinning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention provides a double-groove silicon carbide MOSFET with a side wall gate resisting negative pressure and a preparation method thereof, wherein the preparation method comprises the following steps: the silicon carbide N epitaxial layer comprises a first P + area and a second P + area which are positioned above the silicon carbide N epitaxial layer, the width of the first P + area is larger than that of the second P + area, the depth of the first P + area is larger than that of the second P + area, and symmetrical silicon oxide is wrapped in the first P + area. According to the invention, the silicon carbide groove is prepared firstly, the silicon carbide is etched, the mask is opened again, the wide groove is widened, the narrow groove is opened, the narrow groove is etched, the concave structure is formed in the wide groove, the side wall MOSFET is formed between two anodes which are staggered in depth, the shallow groove is sandwiched between the deep grooves, the two deep grooves are mutually exhausted, the deep groove is further exhausted, the bottom potential at the deep groove is lower than that of the shallow groove, so that the electric field at the N region of the side wall is low, in the process of closing the grid, the low potential is kept, the voltage difference between two ends of the grid oxygen is small, and the further negative voltage adding of the grid is favorably reduced.
Description
Technical Field
The invention relates to the technical field of silicon carbide trench MOSFET preparation, in particular to a double-trench silicon carbide MOSFET with a side wall gate resisting negative pressure and a preparation method thereof.
Background
The silicon carbide power semiconductor device has the characteristics of high voltage resistance, good thermal stability, low switching loss, high power density and the like, and is widely applied to the field of new energy sources such as electric automobiles, wind power generation, photovoltaic power generation and the like. The silicon carbide power semiconductor devices commonly used at present mainly include: silicon carbide SBD (Schottky Barrier diode) and a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), wherein the silicon carbide MOSFET belongs to a single-stage device, the turn-on and turn-off speed is high, and higher requirements are provided for the reliability of a grid electrode.
Silicon carbide (SiC) materials have been paid attention to and studied by people due to their excellent physical properties, and thus silicon carbide MOSFETs are derived, which are important components of modern power electronic devices, and due to their characteristics of high frequency and high power density, the power supply volume can be greatly reduced, and the conversion efficiency is improved.
Therefore, it is necessary to develop new fabrication schemes to improve the negative voltage resistance of the gate electrode, so as to improve the performance of the trench silicon carbide MOSFET.
Disclosure of Invention
In view of this, the invention provides a method for preparing a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage, which solves the technical problem that the gate of the trench silicon carbide MOSFET in the prior art has defects in the negative voltage resistance.
In order to achieve the above object, the present invention provides a double trench silicon carbide MOSFET with a sidewall gate resistant to a negative voltage, comprising: the transistor comprises a drain electrode, a silicon carbide substrate positioned above the drain electrode, a silicon carbide N epitaxy positioned above the silicon carbide substrate, a first P + region and a second P + region positioned above the silicon carbide N epitaxy, a gate oxide region, a gate electrode and an N channel which are symmetrically arranged above the first P + region, a Pwell region and an N + region positioned on the side surfaces of the gate oxide region, the gate electrode and the N channel, and a source electrode positioned above the Pwell region and the N + region;
the width of the first P + region is larger than that of the second P + region, the depth of the first P + region is larger than that of the second P + region, and symmetrical silicon oxide is coated in the first P + region.
Furthermore, a Pwell area and an N + area are symmetrically arranged above the second P + area.
Further, the N + region is located above the Pwell region.
In order to achieve the above object, the present invention further provides a method for manufacturing the double trench silicon carbide MOSFET with the sidewall gate resistant to negative voltage, comprising the following steps:
manufacturing a Pwell area in an injection or epitaxial mode, depositing a silicon carbide groove, etching to obtain a mixed mask layer, coating a photoresist in a spinning mode, photoetching, etching the mixed mask layer, and removing the photoresist;
under the action of the mixed mask layer, silicon carbide is etched to form a silicon carbide wide groove with the width of 4-9 mu m and the depth of the groove is 0.2-0.5 mu m;
widening the silicon carbide wide grooves to 5-10 mu m through photoetching blocking, and preparing 2-3 mu m silicon carbide narrow grooves between any two silicon carbide wide grooves;
etching the silicon carbide narrow groove to 1 mu m under the action of the mixed mask layer, forming a concave groove in the silicon carbide wide groove at the moment, and removing the photoresist;
depositing a side wall protective layer, etching by a dry method until the silicon carbide is completely exposed, selecting photoresist as a mask again, and removing the side wall mask in the silicon carbide narrow groove;
removing the photoresist, and performing high-temperature aluminum ion implantation under the action of the mixed mask layer and the side wall protection layer to form a first P + region and a second P + region with high concentration; removing the side wall mask, the photoresist and the mixed mask layer, spin-coating the photoresist, adjusting the exposure intensity, exposing the surface silicon carbide layer, retaining the photoresist in the hole, performing nitrogen ion implantation under the mask of the photoresist to form an N + region, and removing the photoresist;
depositing a carbon film, activating injected ions at high temperature, then preparing gate oxide, depositing polycrystalline silicon with the thickness of 1-2 mu m, etching the polycrystalline silicon without a mask until the gate oxide at the bottom and the top is exposed, depositing an isolation dielectric layer, filling a silicon carbide wide groove, etching the isolation dielectric layer and a gate oxide region through a photoresist mask to form an electrical isolation layer of the polycrystalline silicon, and depositing metal to define a grid electrode, a source electrode and a drain electrode.
The beneficial effects of adopting the above embodiment are:
the invention firstly prepares a 4-9 μm wide silicon carbide groove, etches silicon carbide 0.2-0.5 μm, opens the mask again, widens the wide groove to 5-10 μm, opens a narrow groove 2-3 μm, etches the narrow groove to 1 μm, forms a concave structure in the wide groove, forms a sidewall MOSFET between two anodes with staggered depth, the shallow grooves are sandwiched between the deep grooves, the two deep grooves are mutually exhausted, the potential at the bottom of the deep groove is lower than that of the shallow groove, thus leading the electric field at the N region of the sidewall to be low, in the closing process of the grid, the potential point at the N region does not have larger change due to the existence of the deep grooves, keeps low potential, the voltage difference at two ends of the grid oxide is not large, and is beneficial to further reducing the voltage applied by the grid, namely Vgs voltage.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage after step S1 is performed in the method for manufacturing a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage according to the present invention;
fig. 2 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a negative-voltage-resistant sidewall gate after step S2 of the method for manufacturing a double-trench silicon carbide MOSFET with a negative-voltage-resistant sidewall gate according to the present invention is performed;
fig. 3 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage after step S3 is performed in the method for manufacturing a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage according to the present invention;
fig. 4 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage after step S4 is performed in the method for manufacturing a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage according to the present invention;
fig. 5 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage after step S5 is performed in the method for manufacturing a double-trench silicon carbide MOSFET with a side-wall gate resistant to negative voltage according to the present invention;
fig. 6 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a negative-voltage-resistant sidewall gate after step S6 in the method for manufacturing a double-trench silicon carbide MOSFET with a negative-voltage-resistant sidewall gate according to the invention;
fig. 7 is a schematic structural change diagram of an embodiment of a double-trench silicon carbide MOSFET with a sidewall gate resistant to negative voltage after step S7 is performed in the method for manufacturing a double-trench silicon carbide MOSFET with a sidewall gate resistant to negative voltage according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To solve the technical problem in the prior art, the present invention provides a sidewall-gate anti-negative-voltage dual-trench silicon carbide MOSFET, please refer to fig. 7, where fig. 7 is a drawing of an embodiment of a sidewall-gate anti-negative-voltage dual-trench silicon carbide MOSFET provided in the present invention.
Specifically, the double-groove silicon carbide MOSFET with the side wall gate resisting negative pressure comprises: a drain 112, a silicon carbide substrate 101 located above the drain 112, a silicon carbide N-epi 102 located above the silicon carbide substrate 101, a first P + region 117 and a second P + region 127 located above the silicon carbide N-epi 102, a gate oxide region, a gate electrode 110 and an N-channel symmetrically located above the first P + region 117, pwell regions 103 and N + regions 106 located on the side surfaces of the gate oxide region, the gate electrode 110 and the N-channel, and a source 109 located above the Pwell regions 103 and the N + regions 106;
the width of the first P + region 117 is greater than the width of the second P + region 127, and the depth of the first P + region 117 is greater than the depth of the second P + region 127, wherein the first P + region 117 is covered by a symmetrical silicon oxide 108.
Furthermore, a Pwell region 103 and an N + region 106 are symmetrically disposed above the second P + region 127.
Further, the N + region 106 is located above the Pwell region 103.
Specifically, in this embodiment, a concave structure is formed in the prepared wide trench, a sidewall MOSFET with a staggered depth is formed between two anodes, a shallow trench is sandwiched between the deep trenches, the two deep trenches are mutually depleted, the deep trench is further depleted, and the bottom potential at the deep trench is lower than the shallow trench, which results in a low electric field at the N region of the sidewall, during the closing process of the gate 110, the potential point at the N region does not change greatly due to the existence of the deep trench, so that a low potential is maintained, the voltage difference between two ends of the gate oxide is not large, and it is beneficial to further applying a negative voltage, i.e., vgs voltage, to the gate 110 to further reduce.
In order to fabricate the double-trench silicon carbide MOSFET with the sidewall gate resistant to negative voltage, in an embodiment of the present invention, referring to fig. 1 to 7, the present invention further provides a method for fabricating a double-trench silicon carbide MOSFET with a sidewall gate resistant to negative voltage, including the following steps:
s1, a Pwell area 103 is manufactured in an injection or epitaxial mode, a silicon carbide groove is deposited and etched to obtain a mixed mask layer 104, photoresist is coated in a spinning mode and is etched, then the mixed mask layer 104 is etched, and the photoresist is removed, wherein the mixed mask layer 104 comprises a mixed layer of silicide and Ni according to an etching selection ratio and a later injection condition, the mixed layer Ni is arranged at the top, the silicide is arranged at the bottom, the Ni layer can be selected to be about 0.5 micrometer, the silicide is selected to be about 2 micrometers thick, the silicide is preferably silicon dioxide, specifically, the mixed mask layer 104 serves as an etching mask layer and an injection barrier layer, and specifically, referring to figure 1, the mixed mask layer 104 is partially etched;
s2, etching the silicon carbide under the action of the mixed mask layer 104 to form a silicon carbide wide groove with the width of 4-9 microns and the depth of 0.2-0.5 microns, and referring to a graph 2 to obtain a silicon carbide wide groove structure;
s3, widening the silicon carbide wide grooves to 5-10 microns through photoetching blocking, preparing 2-3 microns silicon carbide narrow grooves between any two silicon carbide wide grooves, referring to the graph 3, and obtaining the silicon carbide wide grooves and the silicon carbide narrow grooves, wherein the depths of the grooves are different;
s4, etching the silicon carbide narrow groove to 1 mu m under the action of the mixed mask layer 104, forming a concave groove in the silicon carbide wide groove at the moment, removing photoresist, and referring to the graph of FIG. 4, wherein the depth of the silicon carbide narrow groove sequentially penetrates through the mixed mask layer 104, the Pwell area 103 and part of the silicon carbide N epitaxy 102;
s5, depositing a side wall protection layer 105, performing dry etching until the silicon carbide is completely exposed, selecting the photoresist as a mask again, and removing the side wall mask in the silicon carbide narrow groove, referring to the graph of FIG. 5, wherein the side wall protection layer 105 at the silicon carbide narrow groove is already removed, and the side wall protection layer 105 at the silicon carbide wide groove is still remained;
s6, removing the photoresist, and performing high-temperature aluminum ion implantation under the action of the mixed mask layer 104 and the side wall protection layer 105 to form a first P + region 117 and a second P + region 127 with high concentration; removing the side wall mask, the photoresist and the mixed mask layer 104, spin-coating the photoresist, adjusting the exposure intensity, exposing the surface silicon carbide layer, retaining the photoresist in the hole, performing nitrogen ion implantation under the mask of the photoresist to form an N + region 106, removing the photoresist, referring to fig. 6, wherein the width of the first P + region 117 is greater than the width of the second P + region 127, the depth of the first P + region 117 is greater than the depth of the second P + region 127, and the first P + region 117 is internally coated with symmetrical silicon oxide 108;
s7, depositing a carbon film, activating injected ions at high temperature, then preparing gate oxide, depositing polycrystalline silicon with the thickness of 1-2 mu m, etching the polycrystalline silicon without a mask until the gate oxide at the bottom and the top is exposed, depositing an isolation dielectric layer 111, filling a silicon carbide wide groove, etching the isolation dielectric layer 111 and a gate oxide area through a photoresist mask to form an electrical isolation layer of the polycrystalline silicon, and depositing metal to define a grid electrode 110, a source electrode 109 and a drain electrode 112.
In summary, the invention prepares a 4-9 μm wide silicon carbide trench, etches silicon carbide 0.2-0.5 μm, opens the mask again, widens the wide trench to 5-10 μm, opens the narrow trench 2-3 μm, etches the narrow trench to 1 μm, forms a concave structure in the wide trench, forms a sidewall MOSFET with two staggered anodes, and traps a shallow trench between the deep trenches, the two deep trenches are mutually exhausted, the deep trench is further exhausted, the bottom potential at the deep trench is lower than the shallow trench, resulting in a low electric field at the N region of the sidewall, during the closing process of the gate, the potential point at the N region does not change greatly due to the existence of the deep trench, vgs is kept at a low potential, the voltage difference between two ends of the gate oxide is not large, and is beneficial for further reducing the voltage when a negative voltage is applied to the gate.
The method for preparing the double-groove silicon carbide MOSFET with the side-wall gate for resisting negative pressure provided by the invention is described in detail, a specific example is applied in the method for explaining the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (2)
1. A double trench silicon carbide MOSFET with a sidewall gate resistant to negative voltage, comprising: the silicon carbide substrate is positioned above the drain electrode, the silicon carbide N epitaxy is positioned above the silicon carbide substrate, the first P + region and the second P + region are positioned above the silicon carbide N epitaxy, the gate oxide region, the gate electrode and the N channel are symmetrically arranged above the first P + region, the Pwell region and the N + region are positioned on the side surfaces of the gate oxide region, the gate electrode and the N channel, and the source electrode is positioned above the Pwell region and the N + region;
the width of the first P + region is greater than that of the second P + region, the depth of the first P + region is greater than that of the second P + region, and symmetrical silicon oxide is coated in the first P + region;
a Pwell region and an N + region are symmetrically arranged above the second P + region, the N + region is positioned above the Pwell region, and the source electrode extends into the first P + region; the silicon oxide is arranged on the side wall of the source electrode exceeding the grid oxide area, and the source electrode extends into the second P + area.
2. The method of fabricating a sidewall-gated negative-voltage tolerant double trench silicon carbide MOSFET of claim 1 comprising the steps of:
manufacturing a Pwell area in an injection or epitaxial mode, depositing a silicon carbide groove, etching to obtain a mixed mask layer, coating a photoresist in a spinning mode, photoetching, etching the mixed mask layer, and removing the photoresist;
under the action of the mixed mask layer, silicon carbide is etched to form a silicon carbide wide groove with the width of 4-9 mu m and the depth of the groove is 0.2-0.5 mu m;
widening the silicon carbide wide grooves to 5-10 mu m through photoetching blocking, and preparing 2-3 mu m silicon carbide narrow grooves between any two silicon carbide wide grooves;
etching the silicon carbide narrow groove to 1 mu m under the action of the mixed mask layer, forming a concave groove in the silicon carbide wide groove at the moment, and removing the photoresist;
depositing a side wall protective layer, etching by a dry method until the silicon carbide is completely exposed, selecting the photoresist as a mask again, and removing the side wall mask in the silicon carbide narrow groove;
removing the photoresist, and performing high-temperature aluminum ion implantation under the action of the mixed mask layer and the side wall protection layer to form a first P + region and a second P + region with high concentration; removing the side wall mask, the photoresist and the mixed mask layer, spin-coating the photoresist, adjusting the exposure intensity, exposing the surface silicon carbide layer, retaining the photoresist in the hole, performing nitrogen ion implantation under the mask of the photoresist to form an N + region, and removing the photoresist;
depositing a carbon film, activating injected ions at high temperature, then preparing gate oxide, depositing polycrystalline silicon with the thickness of 1-2 mu m, etching the polycrystalline silicon without a mask until the gate oxide at the bottom and the top is exposed, depositing an isolation dielectric layer, filling a silicon carbide wide groove, etching the isolation dielectric layer and a gate oxide region through a photoresist mask to form an electrical isolation layer of the polycrystalline silicon, and depositing metal to define a grid electrode, a source electrode and a drain electrode.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937297A (en) * | 1998-06-01 | 1999-08-10 | Chartered Semiconductor Manufacturing, Ltd. | Method for making sub-quarter-micron MOSFET |
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