CN115132600A

CN115132600A - Method for manufacturing electronic device

Info

Publication number: CN115132600A
Application number: CN202110331205.8A
Authority: CN
Inventors: 林俊贤
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-09-30
Also published as: TW202303545A; US20220367529A1; TWI809765B

Abstract

The invention provides a manufacturing method of an electronic device, which comprises the following steps: a substrate is provided that includes a non-disposable portion and a disposable portion adjacent to the non-disposable portion. A first test lead is formed to extend through the non-discarded portion and the discarded portion. The substrate is cut on the target line, wherein the target line is aligned with a boundary between the non-discarded portion and the discarded portion. And carrying out a first conduction test on the first test lead. When the result of the first conduction test is a short circuit, the substrate is determined to be in a deviated cutting state from the target, or when the result of the first conduction test is an open circuit, the substrate is determined to be in a target cutting state.

Description

Method for manufacturing electronic device

Technical Field

The present disclosure relates to a method for manufacturing an electronic device, and more particularly, to a method for manufacturing an electronic device capable of detecting the cutting and grinding results during the manufacturing process.

Background

Electronic devices that are common today have tiled display panels (tiled display panels) to provide information to a user through the tiled display panels. The tiled display panel includes a plurality of individual display panels connected to each other and having a frameless (boarderless) design to reduce gaps between adjacent display panels. Therefore, in the manufacturing process of these individual display panels, the frame is removed by performing a cutting (SB) and grinding (grinding) step. In addition, after the display panel is cut and ground, whether the result meets the specification needs to be detected. In the conventional method, a person confirms whether the result meets the specification through an Optical Microscope (OM), so the detection is relatively time-consuming to perform, and the probability of human error is increased.

Disclosure of Invention

One embodiment of the present disclosure provides a method for manufacturing an electronic device, which includes the following steps. A substrate is provided, wherein the substrate includes a non-disposable portion and a disposable portion adjacent to the non-disposable portion. A first test conductor is formed to extend through the non-discard portion and the discard portion. The substrate is wire cut in alignment with a target line, wherein the target line is aligned with a boundary between the non-discarded portion and the discarded portion. And carrying out a first conduction test on the first test lead. When the result of the first conduction test is a short circuit, the substrate is determined to be in a deviated cutting state from the target, or when the result of the first conduction test is an open circuit, the substrate is determined to be in a target cutting state.

Drawings

Fig. 1 is a schematic top view of a substrate of an electronic device without cutting and polishing according to a first embodiment of the disclosure.

Fig. 2 is a schematic top view of a substrate of an electronic device cut according to a first embodiment of the disclosure.

Fig. 3 is a schematic top view of a substrate of a polished electronic device according to a first embodiment of the disclosure.

Fig. 4 is a flowchart illustrating a method for manufacturing an electronic device according to a first embodiment of the disclosure.

Fig. 5 is a schematic top view illustrating a substrate of an electronic device without cutting and polishing according to a second embodiment of the disclosure.

Fig. 6 is a schematic view of a substrate of a portion of an electronic device cut and polished according to a third embodiment of the present disclosure.

Fig. 7 is a schematic top view of a substrate of an electronic device without cutting and polishing according to a fourth embodiment of the disclosure.

Fig. 8 is a schematic diagram of a substrate of a portion of an electronic device cut and ground according to a fifth embodiment of the disclosure.

Fig. 9 is a schematic top view of a substrate of an electronic device without cutting and polishing according to a sixth embodiment of the disclosure.

Fig. 10 is a schematic top view of a substrate of an electronic device cut and polished according to a sixth embodiment of the disclosure.

Description of reference numerals: 10, an electronic device; 100 to a substrate; 1001-1004, 1011, 1013, 1221-1224 edges; 100F, 100R-surface; 100S1-100S 3-side; 1021-; 1061-; 1081. 1083, 1085, 1087, 1141, 1143, 1145, 1147 — test wires; 1101, 1161, 1163, 1261, 1263, 1301, 1303-wires; 1121 1122, 1181 1182, 1281 1282, 1321 1322 to the test pad; 1201-1204, 1241-1242, 1361-1363 segments; AA-display area; BD-boundary; DP-discard part; NDP-non-discard portion; OLB — outer pin joint part; PA-peripheral area; S100-S116; x, Y, Z-direction.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and simplicity of illustration, various figures in the present disclosure depict only a portion of an electronic device and are not necessarily drawn to scale. In addition, the number and size of the components in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following description and claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to …".

It will be understood that when an element or layer is referred to as being "on" or "disposed" or "connected" to another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present (indirectly). In contrast, when an element is referred to as being "directly on," "directly disposed on" or "directly connected to" another element or layer, there are no intervening elements or layers present. In addition, the arrangement relationship between different elements can be explained according to the content of the drawings.

The electrical connection may be a direct connection or an indirect connection. The two elements may be in direct contact to transmit electrical signals without other elements in between. The two component electrical connections may be bridged by a component intermediate the two to transmit electrical signals. An electrical connection may also be referred to as a coupling.

Although the terms first, second, and third … may be used to describe various components, the components are not limited by this term. This term is used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but are substituted with the first, second and third … in the order in which the elements of the claims are recited. Therefore, in the following description, a first constituent element may be a second constituent element in the claims.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

The electronic device of the present disclosure may include a display device, an antenna device, a touch display device (touch display), a curved display device (curved display), or a non-rectangular display device (free shape display), but is not limited thereto. The electronic device can be a bendable or flexible electronic device. The electronic device may include, for example, but is not limited to, a light emitting diode, a liquid crystal (liquid crystal), a fluorescent (fluorescent), a phosphorescent (phosphorescent), other suitable display medium, or a combination of the foregoing. The light emitting diode may include, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a sub-millimeter light-emitting diode (mini LED), a micro-light-emitting diode (micro-LED), a Quantum Dot (QDs) light-emitting diode (such as a QLED or a QDLED), other suitable materials, or any combination thereof, but not limited thereto. The display device may, for example, include a tiled display device, but is not so limited. The concepts or principles of the present disclosure may also be applied to non-self-emissive Liquid Crystal Displays (LCDs), but are not limited thereto.

The antenna device may be, for example, a liquid crystal antenna or other types of antennas, but is not limited thereto. The antenna device may, for example, include a tiled antenna device, but is not so limited. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. In addition, the exterior of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronics may have peripheral systems such as drive systems, control systems, light source systems, shelving systems … to support the display device, antenna devices, or tile devices. The present disclosure will be described below with reference to a display device as an electronic apparatus, but the present disclosure is not limited thereto.

In the following figures a direction X, a direction Y and a direction Z are indicated. The direction Z may be perpendicular to the surface 100F of the substrate 100, and the directions X and Y may be parallel to the surface 100F of the substrate 100. The direction Z may be perpendicular to the direction X and the direction Y, and the direction X may be perpendicular to the direction Y. The following figures may describe the spatial relationship of structures in terms of direction X, direction Y, and direction Z.

Referring to fig. 1, a schematic top view of a substrate of an electronic device without cutting and polishing according to a first embodiment of the disclosure is shown. The electronic device 10 of the present embodiment is exemplified by a display device, but not limited thereto. In general, a display device may include two opposing substrates and a display medium layer disposed between the two substrates. In order to highlight the technical features of the present disclosure and make the drawings more comprehensible, only one of the substrates is shown in the drawings, and the display medium layer and the other substrate are omitted. In other possible embodiments, the display device may include a substrate and a display medium layer disposed on the substrate.

Please refer to fig. 1 and fig. 4 simultaneously, wherein fig. 4 is a flowchart illustrating a method for manufacturing an electronic device according to a first embodiment of the present disclosure. Referring to fig. 4, step S100 is performed to provide a substrate, wherein the substrate includes a non-discarding portion and a discarding portion adjacent to the non-discarding portion. As shown in fig. 1, the substrate 100 may be, for example, an array substrate (array substrate) of a display device, and the substrate 100 may include a plurality of thin film transistors for controlling a display medium layer, and signal lines and control circuits for controlling the thin film transistors, but not limited thereto. The display medium layer may include the light emitting devices described in the above paragraphs, the display medium layer of the present embodiment may include micro light emitting diodes, and the light emitting diodes may be disposed on the substrate 100, but not limited thereto. However, in order to simplify the drawings, the light emitting diode, the thin film transistor, the signal line and the control circuit are not shown in the drawings.

In some embodiments, the substrate 100 may also be, for example, a color filter substrate (color filter substrate) of a display device, but not limited thereto. In addition, the material of the base layer of the substrate 100 may include glass, quartz, sapphire, polymer (such as Polyimide (PI), polyethylene terephthalate (PET)), and/or other suitable materials, which can be used as a flexible substrate or a rigid substrate, but is not limited thereto.

The substrate 100 may include an edge 1001, an edge 1002, an edge 1003, and an edge 1004, and these edges may be connected to each other to form a rectangle. In the method of the present disclosure, a target line 1021, a target line 1022, a target line 1023, and a target line 1024 may be pre-defined on a surface 100F of the substrate 100, which may be used as target lines for a dicing (SB) process, and the target lines may be connected to each other to form a rectangle. In addition, a target line 1041, a target line 1042, a target line 1043 and a target line 1044, which are used as target lines for a grinding process, may be previously set on the surface 100F of the substrate 100, and the target lines may be connected to each other to form a rectangle.

The substrate 100 may have a display area AA and a peripheral area PA surrounding the display area AA. In order to realize the borderless design, the rectangular areas formed by the

target lines

1041, 1042, 1043 and 1044 of the polishing process may correspond to or substantially correspond to the display area AA of the display device. The

target lines

1021, 1022, 1023, 1024 of the dicing process may be located in the peripheral area PA of the display device, but not limited thereto.

As with FIG. 1, target line 1021 may be located between margin 1001 and target line 1041, target line 1022 may be located between margin 1002 and target line 1042, target line 1023 may be located between margin 1003 and target line 1043, and target line 1024 may be located between margin 1004 and target line 1044. The edge 1001, the edge 1003, the target line 1021, the target line 1023, the target line 1041, and/or the target line 1043 may be parallel or substantially parallel to the direction Y. Additionally, edge 1002, edge 1004, target line 1022, target line 1024, target line 1042, and/or target line 1044 can be parallel or substantially parallel to direction X.

To effectively control the results of the cutting and polishing processes, a gauge line 1061 and a gauge line 1062 may be defined based on the target line 1021, and a gauge line 1063 may be defined based on the target line 1041. The gauge line 1061 may be a Lower Specification Limit (LSL) of the cutting process, the gauge line 1062 may be an Upper Specification Limit (USL) of the cutting process, and the target line 1021 is between the gauge line 1061 and the gauge line 1062. In addition, gauge line 1063 may be the upper gauge limit of the polishing process, and target line 1041 is located between gauge line 1062 and gauge line 1063.

Similarly, target line 1023 is located between a gauge line 1064 and a gauge line 1065, and target line 1043 is located between gauge line 1065 and a gauge line 1066. Gauge line 1064 may be a lower gauge limit of a cutting process, gauge line 1065 may be an upper gauge limit of a cutting process, and gauge line 1066 may be an upper gauge limit of a polishing process.

In the direction X, the area of the substrate with the target line 1021 and the right or left of the target line 1023 or the area of the substrate between the target line 1021 and the target line 1023 can be defined as a non-discarded portion NDP, as shown in fig. 1. In addition, in the direction X, the area of the substrate between the target line 1021 and the left or right target line 1023, or the area of the substrate between the target line 1021 and the edge 1001, or the area of the substrate between the target line 1023 and the edge 1003 may be defined as a discarded portion DP. In other words, the target line 1021 or the target line 1023 may be defined as a boundary BD between the non-discarded portion NDP and the discarded portion DP. In addition, the discard portion DP may be removed after the dicing and polishing process, and at least a portion of the non-discard portion NDP may be retained after the dicing and polishing process.

Referring to FIG. 4, step S102 is performed to form a first test lead extending through the non-discarded portion and the discarded portion. As shown in fig. 1, test wires 1081 and/or test wires 1083 (both may also be referred to as first test wires) may be formed on the non-discarding part NDP and the discarding part DP, and the test wires 1081 and the test wires 1083 may have the same or similar structures. In the embodiment, the test wires 1081 may be disposed corresponding to the edge 1001 (e.g., short edge), and the test wires 1083 may be disposed corresponding to the edge 1003 (e.g., short edge), but not limited thereto.

The test wire 1081 or the test wire 1083 may include, but is not limited to, a wire 1101 (which may be referred to as a first wire), a wire 1102 (which may be referred to as a second wire), a wire 1103 (which may be referred to as a second wire), a test pad 1121 (which may be referred to as a first test pad), and a test pad 1122 (which may be referred to as a first test pad).

The conductive line 1101 may be disposed on the discarded portion DP or in the peripheral region PA, and may extend along a boundary BD (i.e., the target line 1021 or the target line 1023) between the non-discarded portion NDP and the discarded portion DP. The extending direction of the conductive line 1101 may be parallel to the direction Y, but is not limited thereto. The conductive line 1102 and the conductive line 1103 may extend through the non-discarding part NDP and the discarding part DP, and the extending direction of the conductive line 1102 and the conductive line 1103 may be parallel to the direction X, but not limited thereto. Thus, the direction of extension of at least a portion of conductive line 1102 and at least a portion of conductive line 1103 is different from the direction of extension of conductive line 1101. Further, one end of the wire 1101 may be connected to one end of the wire 1102, and the other end of the wire 1101 may be connected to one end of the wire 1103.

The test pad 1121 and the test pad 1122 may be disposed on the non-disposal portion NDP or within the display area AA, the test pad 1121 may be connected to the other end of the wire 1102, and the test pad 1122 may be connected to the other end of the wire 1103. Thus, the test pad 1121 may be electrically connected to the wire 1101 through the wire 1102, and the test pad 1122 may be electrically connected to the wire 1101 through the wire 1103. Therefore, the method of the present disclosure can measure the conductivity of the test wire 1081 or the test wire 1083 through the

test pads

1121 and 1122.

The

wires

1101, 1102, 1103, 1121, and 1122 may be formed on the surface 100F of the substrate 100, but not limited thereto. The

wires

1101, 1102, 1103, 1121, and 1122 may comprise metal, transparent conductive material, and other suitable conductive materials, wherein the

wires

1101, 1102, and 1103 of the present embodiment may comprise transparent conductive material (such as Indium Tin Oxide (ITO)), but not limited thereto. In addition, the structure of the test wire 1081 and/or the structure of the test wire 1083 are not limited to the embodiment, and other variations may be adopted.

Referring to fig. 4, step S104 is performed to align a target wire cut substrate, wherein the target wire is aligned with a boundary between the non-discarded portion and the discarded portion. In the dicing process, the target line may be used as a default scribe line and the scribe line is aligned to cut the substrate, but due to the alignment accuracy of the tool, the scribe line on the substrate may not be completely coincident with the target line. Thus, the target line may be a cut line ideally. Further, the word "aligned" may represent that the target line and the boundary coincide with each other.

As shown in fig. 1, a cutting process may be performed and the substrate 100 may be cut in alignment with the target line 1021 and/or the target line 1023. In the cutting process, the substrate 100 may be cut by using a suitable cutting tool such as a cutter wheel, a laser, etc. Since there may be deviations in the position or direction of the cut during the cutting process, an upper specification limit (e.g., the specification line 1062 or 1065) and a lower specification limit (e.g., the specification line 1061 or 1064) are usually set to provide a range that is acceptable in the process.

Referring to fig. 1 and fig. 2, fig. 2 is a schematic top view illustrating a substrate of an electronic device cut according to a first embodiment of the disclosure. As shown in fig. 2, after the substrate 100 is cut along the direction Y by the cutting process corresponding to the target line 1021 and the target line 1023 of fig. 1, a portion of the substrate 100 on the left of the target line 1021 in fig. 1 can be removed, a portion of the substrate 100 on the right of the target line 1023 in fig. 1 can be removed, and the wires 1101 in the

test wires

1081 and 1083 can be removed to expose an edge 1011 and an edge 1013 of the substrate 100. Alternatively, taking the test wire 1081 of fig. 1 as an example, after the dicing process cuts the substrate 100 along the direction Y at a position between the wire 1101 and the gauge line 1062 (the upper limit of the gauge of the dicing process), the wire 1101 and a portion of the substrate 100 may be removed.

According to the above situation, as shown in fig. 2, the conductive path between the test pad 1121 and the test pad 1122 in the test wire 1081 is cut off after the dicing process, so that the test pad 1121 and the test pad 1122 are electrically isolated. In addition, the above description can also be applied to the test wires 1083, and is not repeated.

Referring to fig. 4, step S106 is performed to perform a first conduction test on the first test wire. As shown in fig. 2, the test wire 1081 or the test wire 1083 may be subjected to a first conduction test through the

test pads

1121 and 1122. Next, step S108 in fig. 4 is performed to determine that the substrate is in a off-target cutting state when the result of the first conduction test is short-circuited, or determine that the substrate is in a target cutting state when the result of the first conduction test is open-circuited.

As shown in fig. 1 and 2, when the result of the first conduction test is a short circuit, the conduction path between the test pad 1121 and the test pad 1122 is not cut off, which indicates that the cutting position of the cutting process may fall within the range between the specification line 1061 (the lower specification limit of the cutting process) and the edge 1001 of the substrate 100, or the cutting process is not cutting along the direction Y. Therefore, it can be determined that the substrate 100 is in the off-target dicing state, and it can be determined that this substrate is a master. If the substrate is determined as the control, it means that the substrate needs to be polished for a longer time in the subsequent polishing process, and the first conduction test is repeated after the polishing process.

As shown in fig. 2, when the result of the first conduction test is an open circuit, the conductive path between the test pad 1121 and the test pad 1122 is cut, i.e., the cutting position representing the cutting process falls within the range between the conductive line 1101 and the specification line 1062 (the upper specification limit of the cutting process), or the cutting process may cut the substrate 100 corresponding to the target line 1021. Therefore, the substrate 100 can be determined to be in the target dicing state, and the substrate can be determined to be a non-defective product.

Referring to fig. 4, step S110 is performed to form a second test lead on the non-discarded portion. As in fig. 1 or fig. 2, the test leads 1141 and/or 1143 (both may also be referred to as second test leads) may be formed on the non-discarded portion NDP, and the test leads 1141 and 1143 may have the same or similar structure. In the present embodiment, the test lead 1141 may be disposed corresponding to the edge 1001 (e.g., short edge), and the test lead 1143 may be disposed corresponding to the edge 1003 (e.g., short edge), but not limited thereto.

The

test wires

1141 or 1143 may include a wire 1161 (which may be referred to as a third wire), a wire 1162 (which may be referred to as a fourth wire), a wire 1163 (which may be referred to as a fourth wire), a test pad 1181 (which may be referred to as a second test pad), and a test pad 1182 (which may be referred to as a second test pad), but not limited thereto.

The conductive line 1161 may be disposed on the non-discarded portion NDP or within the display area AA, and may extend along a boundary BD (i.e., the target line 1021 or the target line 1023) between the non-discarded portion NDP and the discarded portion DP. The extending direction of the conductive line 1161 may be parallel to the direction Y, but is not limited thereto. The

wires

1162 and 1163 may be disposed on the non-discarded portion NDP or within the display area AA, and the

wires

1162 and 1163 may each include a segment 1201 and a segment 1202, but are not limited thereto. The extending direction of the segment 1201 may be parallel to the direction X, the extending direction of the segment 1202 may be parallel to the direction Y, and one end of the segment 1201 may be connected to one end of the segment 1202, but not limited thereto. Therefore, the extending direction of at least a part of the wires 1162 and at least a part of the wires 1163 is different from the extending direction of the wires 1161.

In addition, one end of the wire 1161 may be connected to one end of the wire 1162, and the other end of the wire 1161 may be connected to one end of the wire 1163. As shown in fig. 1, one end of a wire 1161 may be connected to one end of segment 1201 of wire 1162, and the other end of wire 1161 may be connected to one end of segment 1201 of wire 1163.

Test pad 1181 and test pad 1182 may be disposed on the non-discarded portion NDP or within display area AA, test pad 1181 may be connected to the other end of lead 1162, and test pad 1182 may be connected to the other end of lead 1163. As with fig. 1 or 2, test pad 1181 may be connected to one end of segment 1202 of lead 1162, and test pad 1182 may be connected to one end of segment 1202 of lead 1163. Thus, test pad 1181 may be electrically connected to lead 1161 through lead 1162, and test pad 1182 may be electrically connected to lead 1161 through lead 1163. Therefore, the method of the present disclosure can measure the conductivity of the test wire 1141 or the test wire 1143 through the

test pads

1181 and 1182.

Wire 1161, wire 1162, wire 1163, test pad 1181 and test pad 1182 may be formed on the same surface of non-discarded portion NDP of substrate 100 (i.e., surface 100F), but are not limited thereto.

Wires

1161, 1162, 1163, test pad 1181 and test pad 1182 may comprise metal, transparent conductive material, and other suitable conductive materials, wherein

wires

1161, 1162 and 1163 of the present embodiment may comprise transparent conductive material (such as Indium Tin Oxide (ITO)), but not limited thereto. In addition, the structure of the test lead 1141 and/or the structure of the test lead 1143 are not limited to this embodiment, and may have other variation structures.

Referring to fig. 4, step S112 is performed to polish an exposed edge of the substrate after the substrate is cut. As shown in fig. 2, the edge 1011 and/or the edge 1013 exposed after the dicing process may be polished. For example, the substrate 100 may be polished with any suitable polishing tool. In consideration of the error in the polishing process, an upper specification limit (e.g., the specification line 1063 or the specification line 1066) may be set to provide a range that is acceptable in the process.

Referring to fig. 2 and 3, fig. 3 is a schematic top view of a substrate of an electronic device polished according to a first embodiment of the disclosure. Referring to fig. 3, after the edge 1011 and/or the edge 1013 of the substrate 100 in fig. 2 are polished to the target line 1041 and/or the target line 1043 by the polishing process, a portion of the substrate 100 to the left of the target line 1041 in fig. 2 may be removed, a portion of the substrate 100 to the right of the target line 1043 in fig. 2 may be removed, and a portion of the conductive line 1102 and a portion of the conductive line 1103 may be removed, exposing an edge 1221 and an edge 1223 of the substrate 100. After the cutting and polishing processes, the non-discarded portion NDP of the remaining substrate 100 may be retained, and the edge 1221 and the edge 1223 may substantially correspond to the edge of the display area AA, so as to achieve a borderless design.

In some embodiments, edge 1011 and/or edge 1013 of substrate 100 of fig. 2 may be polished to gauge line 1063 and/or gauge line 1066. At this time, the edge 1221 of the substrate 100 in fig. 3 may be substantially aligned with the outer edge of the lead 1161 of the test lead 1141, or the edge 1223 of the substrate 100 in fig. 3 may be substantially aligned with the outer edge of the lead 1161 of the test lead 1143.

Referring to fig. 4, step S114 is performed to perform a second conduction test on the second test wire. As in fig. 3, a second conduction test may be performed on test lead 1141 or test lead 1143 through test pad 1181 and test pad 1182. Next, step S116 in fig. 4 is performed to determine that the substrate is in an off-target polishing state when the result of the second conductivity test is open, or determine that the substrate is in a target polishing state when the result of the second conductivity test is short.

As shown in fig. 3, when the result of the second conduction test is an open circuit, the conductive path between the test pad 1181 and the test pad 1182 is cut. This result indicates that the polishing process may have polished the edge of the substrate 100 beyond the gauge line 1063 or the gauge line 1066, such that the conductive line 1161 may have been removed. Therefore, it can be determined that the substrate 100 is in the off-target polishing state, and that the substrate is defective.

As shown in fig. 3, when the result of the second conductivity test is a short circuit, the conductive path between the test pad 1181 and the test pad 1182 is not cut off, which means that the polishing process does not polish the edge of the substrate 100 beyond the gauge line 1063 or the gauge line 1066, or that the polishing process may polish the edge of the substrate 100 to the target line 1041 or the target line 1043. Therefore, the substrate 100 can be determined to be in the target polishing state, and the substrate can be determined to be a non-defective product.

It should be noted that if the substrate 100 is short-circuited as a result of the first conductivity test, the first conductivity test is required to be repeated in addition to the second conductivity test after the polishing process. When the first conduction test result is a short circuit and the second conduction test result is a short circuit, the substrate 100 still needs to be determined as a defective product. Since this means that the discarded portion of the substrate 100 is not removed after the cutting process and the polishing process, the borderless design cannot be realized when the substrate 100 is subsequently used for the splicing process.

Therefore, the method for manufacturing the electronic device of the embodiment can confirm whether the frame or the cutting and grinding result meets the specification through an Optical Microscope (OM) without waiting for the display module to be manufactured. In the manufacturing method of the electronic device of the embodiment, whether the cutting or grinding result meets the specification can be judged through a simple conduction test in the manufacturing process, the detection time can be greatly shortened, and the probability of personnel error can be reduced.

In addition, in the conventional display apparatus, the test pads are usually disposed in the peripheral region PA, and various detections may need to be performed after the display module is manufactured, so that the frame width cannot be effectively reduced. However, in the method for manufacturing the electronic device of the present embodiment, the test pads may be disposed in the display area AA (e.g., the rectangular areas corresponding to the

target lines

1041, 1042, 1043, and 1044), so that the frame can be effectively reduced to the edge of the display area AA, thereby implementing a frameless design.

In the present embodiment (as shown in fig. 1), the

test wires

1081, 1083, 1141 and 1143 may be formed on the substrate 100 before the dicing process is performed, but not limited thereto. In some embodiments, the

test wires

1081 and 1083 may be formed on the substrate 100 before the dicing process is performed, and the

test wires

1141 and 1143 may be formed on the substrate 100 after the dicing process and before the polishing process is performed, but not limited thereto.

The steps shown in the method of manufacturing the electronic device in fig. 4 may not be exhaustive and other steps may be performed before, after or between any of the steps shown. Further, some steps may be performed in a different order. The method for manufacturing an electronic device of the present embodiment may include steps S100 to S116. In some embodiments, the method for manufacturing an electronic device may include steps S100 to S108. In addition, the first conduction test and the second conduction test of the present embodiment can also be applied to other embodiments.

The method for manufacturing the electronic device of the present disclosure is not limited to the above embodiments. Other embodiments of the present disclosure will be further disclosed, however, in order to simplify the description and to make the difference between the embodiments more prominent, the same elements are labeled with the same reference numerals and repeated descriptions are omitted.

Referring to fig. 5, a schematic top view of a substrate of an electronic device without cutting and polishing according to a second embodiment of the disclosure is shown. The present embodiment is different from the first embodiment (as shown in fig. 1) in that the

test pads

1121 and 1122 of the

test wires

1081 or 1083 of the present embodiment can be disposed on an outer lead bonding portion OLB and a non-discarded portion NDP in the peripheral region PA of the substrate 100. The outer lead bonding portions OLB may be disposed on at least one side of the display area AA, as shown in fig. 5, and the outer lead bonding portions OLB may be disposed on two sides of the display area AA in the direction Y, but not limited thereto. It should be understood that the outer lead bonding portion OLB may be removed after the subsequent cutting and grinding of the edge 1002 and/or the edge 1004 (e.g., the long side), but not limited thereto.

Lead 1102 and lead 1103 may each include, but are not limited to, a segment 1241 and a segment 1242. The extending direction of the line segment 1241 may be parallel to the direction X, the extending direction of the line segment 1242 may be parallel to the direction Y, and one end of the line segment 1241 may be connected to one end of the line segment 1242, but not limited thereto. Thus, the direction of extension of at least a portion of conductive line 1102 and at least a portion of conductive line 1103 is different from the direction of extension of conductive line 1101. Further, one end of the wire 1101 may be connected with one end of the segment 1241 of the wire 1102, and the other end of the wire 1101 may be connected with one end of the segment 1241 of the wire 1103.

The test pad 1121 may be connected to one end of a segment 1242 of the wire 1102, and the test pad 1122 may be connected to one end of the segment 1242 of the wire 1103. Thus, the test pad 1121 may be electrically connected to the wire 1101 through the wire 1102, and the test pad 1122 may be electrically connected to the wire 1101 through the wire 1103. The other features of the present embodiment can be the same as those of the first embodiment, and the same effects as those of the first embodiment can be achieved, and are not described again.

Referring to fig. 6, a substrate of a portion of an electronic device cut and polished according to a third embodiment of the disclosure is shown. In order to highlight the technical features of the present embodiment and make the drawings more clearly understood, fig. 6 illustrates the substrate 100 corresponding to a portion of the test wire 1141, omitting the test wire 1143, and omitting the cut and ground test wire 1081 or the remaining portion of the test wire 1083. As shown in fig. 6, the substrate 100 (or the non-discarded portion NDP of the substrate 100) may include a surface 100F (or may be referred to as a first surface) and a surface 100R (or may be referred to as a second surface), and the surface 100F and the surface 100R may be two surfaces of the substrate 100 opposite to each other in the direction Z. The present embodiment is different from the first embodiment (as shown in fig. 1) in that the conductive wires 1161 of the present embodiment can be formed on the surface 100F and the

test pads

1181 and 1182 can be formed on the surface 100R.

The segment 1202 of the wire 1162 may extend along the direction Y to one edge of the surface 100F of the substrate 100, and the segment 1202 of the wire 1163 may extend along the direction Y to the other edge of the surface 100F of the substrate 100, but not limited thereto. In the present embodiment, the

wires

1162 and 1163 may each include a segment 1203 and a segment 1204, but not limited thereto. The segment 1203 of the conductive trace 1162 may be formed on a side 100S1 of the substrate 100 (or the non-discarded portion NDP of the substrate 100), the segment 1203 of the conductive trace 1163 may be formed on a side 100S2 of the substrate 100 (or the non-discarded portion NDP of the substrate 100), and the segment 1203 may extend along the direction Z, but not limited thereto. The side 100S1 and the side 100S2 may be two sides of the substrate 100 opposite to each other in the direction Y, and the side 100S1 and the side 100S2 may be connected to the surface 100F and the surface 100R.

A segment 1204 of the

wires

1162 and 1163 may be formed on the surface 100R, and the segment 1204 may extend along the direction Y, but is not limited thereto. One end of line segment 1203 may be connected to one end of line segment 1202 on surface 100F, the other end of line segment 1203 may be connected to one end of line segment 1204 on surface 100R, and the other end of line segment 1204 may be connected to test pad 1181 or test pad 1182.

Segment 1203, segment 1204, test pad 1181 and test pad 1182 may be formed after the cutting and polishing process is completed, wherein segment 1203 may be formed on sides 100S1 and 100S2 by a side printing process, but not limited thereto. Thus, test pad 1181 and test pad 1182 may be electrically connected to lead 1161 on surface 100F through a side printing process. In addition, the conductive line 1161, the line segment 1201 and the line segment 1202 may be formed before the polishing process, but not limited thereto. The other features of the present embodiment can be the same as the above embodiment, and can achieve the same effects as the above embodiment, and are not repeated.

Referring to fig. 7, a top view of a substrate of an electronic device without cutting and polishing according to a fourth embodiment of the disclosure is shown. This embodiment is different from the first embodiment (fig. 1) in that the edge 1002 and/or the edge 1004 (e.g., long edge) can be cut and ground in this embodiment. In the present embodiment, a specification line 1341 and a specification line 1342 are defined based on the target line 1022 (the target line of the cutting process), and a specification line 1343 is defined based on the target line 1042 (the target line of the polishing process). Gauge line 1341 may be the lower gauge limit of the cutting process, gauge line 1342 may be the upper gauge limit of the cutting process, and target line 1022 is located between gauge line 1341 and gauge line 1342. In addition, the gauge line 1343 may be the upper gauge limit of the polishing process, and the target line 1042 is located between the gauge line 1342 and the gauge line 1343.

Similarly, target line 1024 (the target line for the cutting process) is located between a gauge line 1344 and a gauge line 1345, and target line 1044 (the target line for the grinding process) is located between gauge line 1345 and a gauge line 1346. Gauge line 1344 may be the lower gauge limit of the cutting process, gauge line 1345 may be the upper gauge limit of the cutting process, and gauge line 1346 may be the upper gauge limit of the grinding process.

As shown in fig. 7, in the direction Y, a region of the substrate below the target line 1022 or above the target line 1024 or a region of the substrate between the target line 1022 and the target line 1024 may be defined as the non-discarded portion NDP. Further, in the direction Y, a region of the substrate above the target line 1022 or below the target line 1024, or a region of the substrate between the target line 1022 and the edge 1002, or a region of the substrate between the target line 1024 and the edge 1004 may be defined as the discarded portion DP. In other words, target line 1022 or target line 1024 may be defined as boundary BD between non-discarded portion NDP and discarded portion DP.

In addition, the first test wires of the present embodiment may include at least one test wire 1085 and/or at least one test wire 1087, and the second test wires may include at least one test wire 1145 and/or at least one test wire 1147. Referring to fig. 7, two test wires 1085 and two test wires 1145 may be disposed corresponding to the edge 1002 (e.g., long edge), and two test wires 1087 and two test wires 1147 may be disposed corresponding to the edge 1004 (e.g., long edge), wherein the number of the test wires is not limited to that shown in fig. 7.

The

test wires

1085 or 1087 may include, but are not limited to, a wire 1261 (which may be referred to as a first wire), a wire 1262 (which may be referred to as a second wire), a wire 1263 (which may be referred to as a second wire), a test pad 1281 (which may be referred to as a first test pad), and a test pad 1282 (which may be referred to as a first test pad).

Lead 1261 may be disposed on discarded portion DP or within peripheral region PA and may extend along boundary BD (i.e., target line 1022 or target line 1024). The extending direction of the wires 1261 may be parallel to the direction X, but is not limited thereto.

Wires

1262 and 1263 may extend through non-discard portion NDP and discard portion DP, and the direction of extension of

wires

1262 and 1263 may be parallel to direction Y, but is not so limited. Further, one end of a wire 1261 may be connected to one end of wire 1262, and the other end of wire 1261 may be connected to one end of wire 1263.

Test pad 1281 and test pad 1282 may be disposed on the non-discarded portion NDP or within display area AA, test pad 1281 may be connected to the other end of wire 1262, and test pad 1282 may be connected to the other end of wire 1263. Thus, test pad 1281 may be electrically connected to wire 1261 by wire 1262, and test pad 1282 may be electrically connected to wire 1261 by wire 1263.

Taking test wire 1085 as an example, when the result of the first conductive test is a short circuit, the conductive path between test pad 1281 and test pad 1282 is not cut, which means that the cutting position of the cutting process may fall within the range between the specification line 1341 (the lower specification limit of the cutting process) and the edge 1002 of the substrate 100, or the cutting process is not performed along the direction X. Therefore, it can be determined that the substrate 100 is in the off-target cutting state, and that the substrate is a defective product.

When the result of the first conductive test is open, the conductive path between the test pad 1281 and the test pad 1282 is cut, i.e., the cutting position representing the cutting process falls within a range between the conductive line 1261 and the gauge line 1342 (the upper limit of the gauge of the cutting process), or the cutting process may be cutting the substrate 100 corresponding to the target line 1022. Therefore, the substrate 100 can be determined to be in the target cutting state, and the substrate can be determined to be a non-defective product.

In the present embodiment, the wires 1261, the wires 1262, the wires 1263, the test pads 1281 and the test pads 1282 may be formed on the surface 100F of the substrate 100, but not limited thereto.

Wires

1261, 1262, 1263, 1281 and 1282 may comprise metal, transparent conductive material, and other suitable conductive materials, wherein

wires

1261, 1262 and 1263 of the present embodiment may comprise transparent conductive material (such as indium tin oxide), but not limited thereto. In addition, the structure of the test wire 1085 and/or the structure of the test wire 1087 are not limited to the embodiment, and other variations may be adopted.

The

test wires

1145 or 1147 may include a wire 1301 (which may be referred to as a third wire), a wire 1302 (which may be referred to as a fourth wire), a wire 1303 (which may be referred to as a fourth wire), a test pad 1321 (which may be referred to as a second test pad), and a test pad 1322 (which may be referred to as a second test pad), but not limited thereto.

The conductive line 1301 may be disposed on the non-discarded portion NDP or within the display area AA, and may extend along the boundary BD (i.e., the target line 1022 or the target line 1024). The extending direction of the conductive line 1301 may be parallel to the direction X, but is not limited thereto. The conductive lines 1302 and the conductive lines 1303 may be disposed on the non-discarded portion NDP or in the display area AA, and the extending directions of the conductive lines 1302 and the conductive lines 1303 may be parallel to the direction Y, but not limited thereto. Therefore, the extending direction of at least a part of the conductive lines 1302 and at least a part of the conductive lines 1303 is different from the extending direction of the conductive lines 1301. Further, one end of the wire 1301 may be connected to one end of the wire 1302, and the other end of the wire 1301 may be connected to one end of the wire 1303.

Test pad 1321 and test pad 1322 may be disposed on the non-discarded portion NDP or within display area AA, test pad 1321 may be connected to the other end of wire 1302, and test pad 1322 may be connected to the other end of wire 1303. Thus, test pad 1321 may be electrically connected to lead 1301 by lead 1302, and test pad 1622 may be electrically connected to lead 1301 by lead 1303.

When the result of the second conduction test is an open circuit, the conductive path between test pad 1321 and test pad 1322 is severed. This result indicates that the polishing process may have polished the edge of the substrate 100 beyond the gauge line 1343 or gauge line 1346 such that the lead 1301 may have been removed. Therefore, it can be determined that the substrate 100 is in the off-target polishing state, and that the substrate is defective.

When the result of the second conductive test is a short, the conductive path between the test pad 1321 and the test pad 1322 is not cut off, which means that the polishing process does not polish the edge of the substrate 100 beyond the specification line 1343 or the specification line 1346, or that the polishing process may polish the edge of the substrate 100 to the target line 1042 or the target line 1044. Therefore, the substrate 100 can be determined to be in the target polishing state, and the substrate can be determined to be a non-defective product.

In the present embodiment, the conductive lines 1301, the conductive lines 1302, the conductive lines 1303, the test pads 1321 and the test pads 1322 may be formed on the same surface (i.e., the surface 100F) of the non-discarded portion NDP of the substrate 100, but not limited thereto. The

conductive lines

1301, 1302, 1303, 1321 and 1322 may include metal, transparent conductive material and other suitable conductive materials, wherein the

conductive lines

1301, 1302 and 1303 of the present embodiment may include transparent conductive material (such as ito), but not limited thereto. In addition, the structure of the test lead 1145 and/or the structure of the test lead 1147 are not limited to this embodiment, and may have other variation structures. The steps and other features of the manufacturing method of this embodiment may be the same as those of the first embodiment, and the same effects as those of the first embodiment may be achieved, and are not described again.

In the present embodiment, a plurality of signal lines may be disposed in the peripheral area PA on both sides of the display area AA in the direction Y, so that the size (e.g., area) of the

test wires

1085 or 1087 may be smaller than the size of the

test wires

1081 or 1083 in the first embodiment, or the size of the

test wires

1145 or 1147 may be smaller than the size of the

test wires

1141 or 1143 in the first embodiment. For example, the length of wire 1261 of test wire 1085 or test wire 1087 may be less than the length of wire 1101 of test wire 1081 or test wire 1083, or the length of wire 1301 of test wire 1145 or test wire 1147 may be less than the length of wire 1161 of test wire 1141 or test wire 1143, but not limited thereto.

Therefore, the test lead can be prevented from occupying too much arrangement space of the signal line in the peripheral area PA, and the electrical interference of the test lead to the signal line can be reduced. On the other hand, the number of the

test wires

1085 or 1087 may be greater than the number of the

test wires

1081 or 1083, or the number of the

test wires

1145 or 1147 may be greater than the number of the

test wires

1141 or 1143, so as to improve the accuracy of the detection result of the substrate 100 after the cutting and polishing processes.

Referring to fig. 8, a substrate of a portion of an electronic device cut and polished according to a fifth embodiment of the disclosure is shown. In order to highlight the technical features of the present embodiment and make the drawings more clearly understood, fig. 8 illustrates the substrate 100 corresponding to a portion of the test wire 1145, omitting the test wire 1147, and omitting the cut and ground test wire 1085 or the remaining portion of the test wire 1087. The present embodiment is different from the fourth embodiment (as shown in fig. 7) in that the conductive lines 1301 of the present embodiment can be formed on the surface 100F and the

test pads

1321 and 1322 can be formed on the surface 100R.

The

conductive lines

1302 and 1303 of the present embodiment may each include a line segment 1361, a line segment 1362, and a line segment 1363. The line segment 1361 of the conductive line 1302 and the conductive line 1303 may extend along the direction Y to an edge of the surface 100F of the substrate 100, one end of the conductive line 1301 may be connected to one end of the line segment 1361 of the conductive line 1302, and the other end of the conductive line 1301 may be connected to one end of the line segment 1361 of the conductive line 1303.

In the

conductive lines

1302 and 1303, a line segment 1362 may be formed on a side surface 100S3 of the substrate 100 (or the non-discarded portion NDP of the substrate 100), and the line segment 1362 may extend along the direction Z. Taking fig. 8 as an example, the side surface 100S3 may be a side surface formed by the substrate 100 polished to the target line 1042 of the polishing process, but not limited thereto.

In the

wires

1302 and 1303, a line segment 1363 may be formed on the surface 100R, and the line segment 1363 may extend along the direction Y, but not limited thereto. One end of line 1362 may be connected to one end of line 1361 on surface 100F, the other end of line 1362 may be connected to one end of line 1363 on surface 100R, and the other end of line 1363 may be connected to test pad 1321 or test pad 1322.

Line 1362, line 1363, test pad 1321 and test pad 1322 may be formed after the cutting and grinding process is completed, wherein line 1362 may be formed on side 100S3 by the side printing process, but not limited thereto. In addition, the conductive line 1301 and the line segment 1361 can be formed before the polishing process, but not limited thereto. The remaining features of this embodiment can be the same as those of the fourth embodiment (see fig. 7), and the same effects as those of the first embodiment can be achieved, and further description is omitted.

Referring to fig. 9 and 10, fig. 9 is a schematic top view illustrating a substrate of an electronic device without being cut and polished according to a sixth embodiment of the present disclosure, and fig. 10 is a schematic top view illustrating a substrate of an electronic device with being cut and polished according to a sixth embodiment of the present disclosure. As shown in fig. 9, the present embodiment may be a combination of the first embodiment (fig. 1) and the fourth embodiment (fig. 7). The first test wires of the present embodiment may include the

test wires

1081 and 1083 of the first embodiment and the

test wires

1085 and 1087 of the fourth embodiment, and the second test wires of the present embodiment may include the

test wires

1141 and 1143 of the first embodiment and the

test wires

1145 and 1147 of the fourth embodiment.

The

test wires

1081 and 1141 may be disposed corresponding to the edge 1001 (e.g., short edge), the

test wires

1083 and 1143 may be disposed corresponding to the edge 1003 (e.g., short edge), the two

test wires

1085 and 1145 may be disposed corresponding to the edge 1002 (e.g., long edge), and the two

test wires

1087 and 1147 may be disposed corresponding to the edge 1004 (e.g., long edge), but not limited thereto.

Therefore, for the cutting and polishing process, the cutting and polishing states of the four edges of the substrate 100 can be detected by performing the first conduction test and the second conduction test on the first test wire and the second test wire by the method described in the first embodiment. As shown in fig. 10, an edge 1221, an edge 1222, an edge 1223, and an edge 1224 of the substrate 100 may be aligned with or substantially aligned with the edge of the display area AA of the display device, so as to achieve a frameless design. The other features of the present embodiment may be the same as those of the first embodiment and the fourth embodiment, and the same effects as those of the first embodiment can be achieved, and further description is omitted.

In summary, in the method for manufacturing an electronic device of the present disclosure, the first test wires and the second test wires are disposed on the substrate, and the first conduction test and the second conduction test are performed through the test pads of the first test wires and the second test wires. Compared with the existing detection method, the method disclosed by the invention can judge whether the cutting or grinding result meets the specification or not through a simple conduction test in the manufacturing process, the detection time can be greatly shortened, and the probability of personnel error can be reduced. In addition, the test pad can be arranged in the display area, so that the frame can be effectively reduced to the edge of the display area, and the design without the frame is realized.

The above description is only an example of the present disclosure, and is not intended to limit the present disclosure, and it is apparent to those skilled in the art that various modifications and variations can be made in the present disclosure. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method of making an electronic device, comprising:

providing a substrate, wherein the substrate comprises a non-discard portion and a discard portion adjacent to the non-discard portion;

forming a first test lead extending through the non-disposable portion and the disposable portion;

cutting the substrate in alignment with a target line, wherein the target line is aligned with a boundary between the non-discarded portion and the discarded portion;

carrying out a first conduction test on the first test lead; and

when the result of the first conduction test is short-circuit, the substrate is judged to be in a target cutting state, or when the result of the first conduction test is open-circuit, the substrate is judged to be in a target cutting state.

2. The method of manufacturing an electronic device according to claim 1, wherein the first test lead includes a first lead disposed on the discarding portion and extending along the boundary and a first test pad disposed on the non-discarding portion and electrically connected to the first lead.

3. The method of claim 2, wherein the first test trace further includes a second trace extending through the non-disposable portion and the disposable portion, the first test pad is electrically connected to the first trace through the second trace, and at least a portion of the second trace extends in a direction different from a direction of the first trace.

4. The method of manufacturing an electronic device according to claim 1, wherein the substrate includes a display area and an outer lead bonding portion disposed on at least one side of the display area, the first test wire includes a first wire and a first test pad, the first wire is disposed on the discarding portion and extends along the boundary, the first test pad is disposed on the outer lead bonding portion and the non-discarding portion, and the first test pad is electrically connected to the first wire.

5. The method of manufacturing an electronic device according to claim 1, further comprising:

forming a second test lead on the non-disposable portion;

grinding one exposed edge of the substrate after the cutting;

performing a second conduction test on the second test lead; and

determining that the substrate is in an off-target polishing state when the result of the second conductivity test is an open circuit, or determining that the substrate is in a target polishing state when the result of the second conductivity test is a short circuit.

6. The method of manufacturing an electronic device according to claim 5, wherein the second test lead includes a third lead and a second test pad, the third lead and the second test pad being disposed on the non-discarded portion, the third lead extending along the boundary, and the second test pad being electrically connected to the third lead.

7. The method according to claim 6, wherein the second testing conductive line further includes a fourth conductive line, the second testing pad is electrically connected to the third conductive line through the fourth conductive line, and at least a portion of the fourth conductive line extends in a direction different from a direction in which the third conductive line extends.

8. The method of fabricating an electronic device according to claim 6, wherein the third conductive line and the second test pad are formed on a same surface of the non-discarded portion.

9. The method of manufacturing an electronic device according to claim 6, wherein the non-discarded portion includes a first surface and a second surface opposite to the first surface, the third conductive line is formed on the first surface and the second test pad is formed on the second surface.

10. The method of claim 6, wherein the second test pad is electrically connected to the third conductive line by a side printing process.