CN115132579A - Method for controlling uniformity of polycrystalline silicon layer in furnace - Google Patents
Method for controlling uniformity of polycrystalline silicon layer in furnace Download PDFInfo
- Publication number
- CN115132579A CN115132579A CN202210748350.0A CN202210748350A CN115132579A CN 115132579 A CN115132579 A CN 115132579A CN 202210748350 A CN202210748350 A CN 202210748350A CN 115132579 A CN115132579 A CN 115132579A
- Authority
- CN
- China
- Prior art keywords
- furnace
- polycrystalline silicon
- layer
- polysilicon
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 516
- 238000000034 method Methods 0.000 title claims abstract description 94
- 229920005591 polysilicon Polymers 0.000 claims abstract description 346
- 230000008021 deposition Effects 0.000 claims abstract description 106
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000006243 chemical reaction Methods 0.000 claims abstract description 32
- 239000012686 silicon precursor Substances 0.000 claims abstract description 19
- 230000009467 reduction Effects 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 112
- 239000002243 precursor Substances 0.000 claims description 58
- 238000002955 isolation Methods 0.000 claims description 41
- 230000001965 increasing effect Effects 0.000 claims description 13
- 239000006185 dispersion Substances 0.000 claims description 9
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 6
- 238000010926 purge Methods 0.000 claims description 5
- 206010037544 Purging Diseases 0.000 claims description 4
- 238000005234 chemical deposition Methods 0.000 claims description 4
- 230000001276 controlling effect Effects 0.000 claims 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 33
- 239000010410 layer Substances 0.000 description 383
- 239000002131 composite material Substances 0.000 description 42
- 230000008569 process Effects 0.000 description 23
- 238000011065 in-situ storage Methods 0.000 description 19
- 238000012986 modification Methods 0.000 description 17
- 230000004048 modification Effects 0.000 description 17
- 235000012431 wafers Nutrition 0.000 description 17
- 239000007789 gas Substances 0.000 description 16
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 15
- 239000002346 layers by function Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 230000002829 reductive effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000005137 deposition process Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000005685 electric field effect Effects 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004061 bleaching Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002195 synergetic effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B28/00—Production of homogeneous polycrystalline material with defined structure
- C30B28/12—Production of homogeneous polycrystalline material with defined structure directly from the gas state
- C30B28/14—Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The application discloses a furnace uniformity control method of a polycrystalline silicon layer, which comprises the following steps: placing a plurality of substrates in a polycrystalline silicon deposition furnace, wherein the substrates are at least distributed in the furnace at a furnace mouth and a furnace tail; adjusting the conditions in the polycrystalline silicon deposition furnace to polycrystalline silicon deposition conditions, introducing gaseous polycrystalline silicon precursors into the polycrystalline silicon deposition furnace from the furnace mouth and the furnace tail in a simultaneous gas inlet mode for reaction and deposition, and forming a polycrystalline silicon layer on the surfaces of the P + channel and the connecting area; and at least measuring the thickness of the polycrystalline silicon layer formed at the furnace mouth and the furnace tail and obtaining the uniformity value in the furnace, and when the uniformity value in the furnace of the thickness of the polycrystalline silicon layer is larger than a preset value T, carrying out temperature rise treatment on the furnace tail or carrying out temperature reduction treatment on the furnace mouth. The control method can obviously improve the stable performance of the polysilicon field plate in the mass production process, thereby improving the yield and productivity and reducing the cost.
Description
Technical Field
The application belongs to the technical field of semiconductor power devices, and particularly relates to a method for controlling uniformity of a polycrystalline silicon layer in a furnace.
Background
Fast Recovery Diode (FRD) is used as a novel power device which is developed in recent years, is one of power semiconductor devices with the largest use amount in power electronic equipment, and is often used in parallel with a three-terminal power switch device (such as IGBT) in a power electronic circuit as a high-frequency and high-current freewheeling Diode or a rectifier tube due to the advantages of good switching performance, short reverse Recovery time, large forward current, small volume, simplicity and convenience in installation and the like, so that the Fast Recovery Diode has great development prospect and market demand. The continuous development of power electronics and consumer electronics has opened up a wide range of applications for semiconductor power devices, and the controllable characteristics of semiconductor power devices determine the efficiency, volume and weight of power electronics and consumer electronics systems. With the rapid growth of power electronics and consumer electronics, there is an increasing demand for cost reduction.
The polysilicon field plate is one of important devices of semiconductor power devices including a fast recovery diode and the like, and has an important influence on the performance of the semiconductor power devices including the fast recovery diode and the like. For example, a polysilicon functional layer (POLY layer) included in a conventional polysilicon field plate is generally an Undoped Polysilicon (UPOLY) structure, and is formed by depositing a POLY film layer and then passing through POCl 3 Pre-expansion is carried out to dope phosphorus element and activate impurities by high-temperature annealing so as to improve the conductive characteristic of the film layer.
In practical applications, it is found that currently, Undoped Polysilicon (UPOLY) structure is adopted as the polysilicon functional layer, although POCl can be used 3 The surface concentration is improved in a pre-diffusion mode to improve the conductive property of the film layer, but because the polycrystalline film layer is about 5000A thick, doped impurities cannot actually penetrate into the bottom of the film layer, and only a very thin conductive modified layer is formed on the surface or the surface layer of the polycrystalline film layer, so that the conductive property of the polycrystalline film layer is low. This directly results in non-ideal field effect of the existing polysilicon field plate.
In addition, in the actual production process, the uniformity of the thickness of the polysilicon layer in the furnace often cannot meet the requirement in the mass production process of the polysilicon field plate, so that the stability of the mass-produced polysilicon field plate is difficult to guarantee. This becomes one of the important factors restricting the mass production of the polysilicon field plate, and also increases the difficulty of cost control.
Disclosure of Invention
The embodiment of the application aims to overcome the defects in the prior art, and provides the method for controlling the uniformity of the polysilicon layer in the furnace, so that the uniformity of the thickness of the polysilicon layer in the furnace can meet the requirement of mass production in the mass production process of the polysilicon field plate, and the technical problem that the stability of the existing polysilicon field plate is not ideal in the mass production process can be effectively solved.
In order to achieve the purpose of the application, the application provides a method for controlling the uniformity in a polycrystalline silicon layer. The method for controlling the uniformity of the polycrystalline silicon layer in the furnace comprises the following steps:
placing a plurality of substrates in a polycrystalline silicon deposition furnace, wherein the substrates are at least distributed in the furnace at a furnace mouth and a furnace tail; the substrate is provided with a connecting area and a P + ring area, the P + ring area comprises a plurality of isolation islands, each isolation island is in a frame shape and is combined on the surface of the substrate, and the isolation islands are distributed at intervals and sequentially surround the connecting area; a frame-shaped P + channel is formed between two adjacent isolation islands;
adjusting the conditions in the polycrystalline silicon deposition furnace to polycrystalline silicon deposition conditions, introducing gaseous polycrystalline silicon precursors into the polycrystalline silicon deposition furnace from the furnace mouth and the furnace tail in a mode of simultaneously introducing air from the two ends for reaction and deposition, and forming a polycrystalline silicon layer in the P + channel and on the surface of the connecting area;
and at least measuring the thickness of the polycrystalline silicon layer formed at the furnace mouth and the furnace tail and obtaining a furnace uniformity value, and when the furnace uniformity value of the thickness of the polycrystalline silicon layer is larger than a preset value T, performing temperature rise treatment on the furnace tail or performing temperature reduction treatment on the furnace mouth.
Compared with the prior art, the method has the following technical effects:
the method for controlling the uniformity in the polycrystalline silicon layer can ensure that when the polycrystalline silicon layers grow in situ on a plurality of substrates in batches, the thickness of the polycrystalline silicon layer grown in situ on each substrate is uniform and high, namely the value of the uniformity in the furnace of the thickness of each polycrystalline silicon layer is small, so that the stability of the performance of the polycrystalline silicon field plate in the mass production process is obviously improved, the yield of the polycrystalline silicon field plate in mass production is improved, the yield of the polycrystalline silicon field plate is effectively improved, and the cost of the polycrystalline silicon field plate is reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic top view of a polysilicon field plate according to an embodiment of the present application;
FIG. 2 is a schematic structural view taken along section AA' in FIG. 1;
fig. 3 is a schematic structural diagram of the polysilicon layer in fig. 1 and 2 being a composite polysilicon layer;
fig. 4 is a schematic structural diagram of a polysilicon field plate including an electrode structure according to an embodiment of the present application;
fig. 5 is a schematic process flow diagram of a method for manufacturing a polysilicon field plate according to an embodiment of the present application.
FIG. 6 is a schematic flow chart of a method for controlling uniformity in a polysilicon layer;
Detailed Description
In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly apparent, the present application is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In this application, the term "and/or" describes an association relationship of associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a is present alone, A and B are present simultaneously, and B is present alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the present application, "at least one" means one or more, "a plurality" means two or more. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, "at least one (a), b, or c", or "at least one (a), b, and c", may each represent: a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, wherein a, b, and c can be single or multiple respectively.
It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not imply an execution sequence, some or all of the steps may be executed in parallel or executed sequentially, and the execution sequence of each process should be determined by its function and inherent logic, and should not limit the implementation process of the embodiments of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The weight of the related components mentioned in the specification of the embodiments of the present application may not only refer to the specific content of each component, but also refer to the proportional relationship of the weight of each component, and therefore, the proportional enlargement or reduction of the content of the related components according to the specification of the embodiments of the present application is within the scope disclosed in the specification of the embodiments of the present application. Specifically, the mass described in the specification of the examples of the present application may be a mass unit known in the chemical field such as μ g, mg, g, kg, etc.
The terms "first" and "second" are used for descriptive purposes only and are used for distinguishing purposes such as substances from one another, and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. For example, a first XX may also be referred to as a second XX, and similarly, a second XX may also be referred to as a first XX, without departing from the scope of embodiments of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The uniformity in the furnace of the thickness of the deposited polycrystalline silicon layer is difficult to control in the mass production process based on the existing polycrystalline silicon field plate, so that the uniformity in the furnace of the thickness of the polycrystalline silicon layer is not ideal, and the corresponding performances of the polycrystalline silicon field plate produced by the same furnace, such as the performance instability of an electric field effect, and the like, are not high, thereby increasing the cost. Thus, the embodiment of the present application proposes the following.
The following explanation of the relevant terms:
uniformity in the furnace: in the polysilicon process of mass production of the thickness of the polysilicon layer, the same furnace contains a plurality of substrates to be deposited and grown with the polysilicon layer, and the polysilicon is synchronously deposited on the plurality of substrates, wherein the thickness uniformity of the polysilicon layer contained in each substrate can be also called as the uniformity among the chips, and is relative to the uniformity in the chips.
Polysilicon field plate: the polysilicon field plate of the present application may be an existing polysilicon field plate, that is, a polysilicon field plate containing a single-layer undoped polysilicon layer, or a polysilicon field plate containing a composite polysilicon layer as shown in the following embodiments and fig. 1 to 5. Wherein the composite polysilicon layer comprises a doped polysilicon layer/an undoped polysilicon layer/a conductive modified layer which are sequentially laminated and combined as shown in fig. 3.
The embodiment of the application provides a method for controlling the uniformity of a polycrystalline silicon layer in a furnace. The method for controlling the uniformity of the polycrystalline silicon layer in the furnace is shown in FIG. 6, and comprises the following steps:
(1): placing a plurality of substrates in a polycrystalline silicon deposition furnace, wherein the substrates are at least distributed in the furnace at a furnace mouth and a furnace tail; the substrate is provided with a connecting area and a P + ring area, the P + ring area comprises a plurality of isolation islands, each isolation island is in a frame shape and is combined on the surface of the substrate, and the isolation islands are distributed at intervals and sequentially surround the connecting area; a frame-type P + channel is formed between two adjacent isolated islands;
(2): adjusting the conditions in the polycrystalline silicon deposition furnace to polycrystalline silicon deposition conditions, introducing gaseous polycrystalline silicon precursors into the polycrystalline silicon deposition furnace from the furnace mouth and the furnace tail in a simultaneous gas inlet mode for reaction and deposition, and forming a polycrystalline silicon layer on the surfaces of the P + channel and the connecting area;
(3): and at least measuring the thickness of the polycrystalline silicon layer formed at the furnace mouth and the furnace tail and obtaining the uniformity value in the furnace, and when the uniformity value in the furnace of the thickness of the polycrystalline silicon layer is larger than a preset value T, carrying out temperature rise treatment on the furnace tail or carrying out temperature reduction treatment on the furnace mouth.
The substrate in step (1) is a substrate to be processed by a polysilicon field plate to form a polysilicon layer, and therefore, the connection region and the P + ring region provided on the substrate are as described in the following embodiments and as shown in fig. 1 to 5, the substrate, the connection region and the P + ring region included in the polysilicon field plate, specifically as shown in fig. 1, 2 and 3, the substrate 1, the connection region 3 and the P + ring region 2, wherein the functional layer structure included in the connection region 3 also includes a functional layer 31, a P + layer 32 and an N + layer 33 which are connected in sequence as shown in fig. 2 and 4. Specifically, the polysilicon field plate and the substrate in step (1) in the embodiment of the present application are as follows, and for the sake of brevity, the description of the polysilicon field plate and the substrate in step (1) is omitted here.
In the step (2), the deposition of the polysilicon deposition furnace can be the existing polysilicon deposition furnace, and the difference from the existing polysilicon deposition furnace is that the polysilicon deposition furnace is provided with a furnace mouth and two ends of a furnace tail for air inlet such as special air inlet, for example, the polysilicon deposition furnace can be provided with a dispersion tube, so that air inlet in a mode of air inlet at two ends is realized, the thickness uniformity of the polysilicon layers contained in different substrates is improved, and the in-furnace uniformity value of the thickness of the polysilicon layers is reduced.
The polysilicon deposition conditions adjusted in the polysilicon deposition furnace in step (2) may be in accordance with existing polysilicon deposition conditions, such as the first reaction conditions for depositing a doped polysilicon layer in step S02 below. Or a second reaction condition for depositing an undoped polysilicon layer in step S03.
The deposition in step (2) is performed to form a polysilicon layer, which is used as a sample for testing the furnace uniformity value in step (3) to obtain furnace uniformity value data.
In an embodiment, the polysilicon deposition condition in step (2) further includes setting an inclined temperature region in the polysilicon deposition furnace. The inclined temperature zone is arranged to improve the thickness uniformity of the polycrystalline silicon layer deposited on each substrate.
The inclined temperature zone can be provided with a furnace mouth temperature zone, a furnace temperature zone and a furnace tail temperature zone, the temperature of the furnace mouth temperature zone can be controlled to be higher than that of the furnace tail temperature zone, and the temperature of the furnace tail temperature zone is higher than that of the furnace tail temperature zone. The temperature in the inclined temperature area is set to include three temperature areas so as to improve the uniformity of the thickness of the deposited polycrystalline silicon layer, including the uniformity of the thickness between the wafers and the uniformity of the thickness in the wafers.
In the embodiment, the step (2) of introducing the gaseous polysilicon precursor into the polysilicon deposition furnace from the furnace mouth and the furnace tail in a simultaneous air inlet manner can be realized by a dispersion pipe arranged in the polysilicon deposition furnace, that is, the polysilicon precursor is introduced into the polysilicon deposition furnace from two ends of the dispersion pipe.
In addition, the type of the gaseous polycrystalline silicon precursor introduced in the step (2) determines the type of a polycrystalline silicon layer formed by deposition, and if the introduced gaseous polycrystalline silicon precursor is an undoped polycrystalline silicon precursor, the polycrystalline silicon layer formed by deposition is undoped polycrystalline silicon; when the introduced gaseous polycrystalline silicon precursor comprises a doping element precursor and a polycrystalline silicon precursor, depositing to form a polycrystalline silicon layer which is doped polycrystalline silicon; when a precursor containing a doping element and a polysilicon precursor is introduced first and then an undoped polysilicon precursor is introduced, the formed polysilicon layer is a composite polysilicon layer, such as the composite polysilicon layer shown in fig. 3.
In the embodiment, when the polysilicon layer formed in step (2) includes a doped polysilicon layer and an undoped polysilicon layer laminated with the doped polysilicon layer, that is, a composite polysilicon layer including a doped polysilicon layer/an undoped polysilicon layer, in step (2), the method for introducing the gaseous polysilicon precursor into the polysilicon deposition furnace for reaction includes the following steps:
a: synchronously introducing a gaseous doping element precursor and a first polysilicon precursor into a polysilicon deposition furnace from two ends of a furnace mouth and a furnace tail simultaneously to form mixed gas, carrying out a first chemical reaction and deposition, and forming a doped polysilicon layer on the surfaces of a P + channel and a connecting area;
b: vacuumizing the polysilicon deposition furnace and N 2 And after the purging treatment, introducing the gaseous second polycrystalline silicon precursor into a polycrystalline silicon deposition furnace for second chemical reaction and deposition, and forming an undoped polycrystalline silicon layer on the surface of the doped polycrystalline silicon layer.
The doped polysilicon layer formed in step a may be formed in step S02 of the method for manufacturing the crystalline silicon field plate shown in fig. 5, and the conditions may be set and adjusted according to the conditions in step S02
The undoped polysilicon layer formed in step b may be formed in step S03 of the method for manufacturing a crystalline silicon field plate as described in fig. 5 below, and the conditions may be set and adjusted according to the conditions in step S03 below.
In the step (3), the thickness of the polysilicon layer may be measured according to an industry standard method. Because of the characteristics of the polysilicon deposition furnace, the special gas is generally introduced from a furnace mouth, and the vacuum-pumping treatment is performed from the furnace. Therefore, the actual deposition of the polysilicon layer often results in the in-furnace (inter-wafer) uniformity difference of the thickness of the deposited film layer. Therefore, when sampling a substrate sample in the furnace, the substrate sample includes at least a substrate on which polysilicon is deposited at the furnace mouth and the furnace tail. Therefore, the reasonability and representativeness of the test sample can be ensured, and the reference of the in-furnace uniformity value of the thickness of the polycrystalline silicon layer is improved. Wherein, the furnace uniformity value of the thickness of the polycrystalline silicon layer can be calculated or tested according to the furnace uniformity value calculation method of the thickness of the existing film layer.
Because the polycrystalline silicon deposition furnace is continuously vacuumized by connecting a vacuum pump from the furnace tail, the gas atmosphere at the furnace tail position is lost to a certain extent, and the uniformity value in the furnace of the tested thickness of the polycrystalline silicon layer is usually higher than a preset value T. Therefore, when the measured in-furnace uniformity value of the thickness of the polysilicon layer is greater than the predetermined value T, it indicates that there is a difference in the inter-wafer thickness of the polysilicon layer deposited on each substrate, which directly results in unstable performance such as electric field effect and low yield of the polysilicon field plate produced in the same furnace. At this moment, in the embodiment of the application, the temperature of the furnace tail is increased, the temperature of the furnace tail is compensated by adopting the temperature, or the furnace mouth is cooled, and the temperature of the furnace tail is compensated indirectly, so that the uniformity of the thickness among the polycrystalline silicon layers deposited on the substrates is improved, and the uniformity value in the furnace is reduced. The predetermined value T may be set according to the quality requirement of mass production, for example, the uniformity value in the furnace is set to 5% in the embodiment of the present application.
In an embodiment, the temperature raising or lowering in the step (3) may be performed by performing temperature adjustment at a temperature adjustment rate as follows until the in-furnace uniformity value of the thickness of the polysilicon layer is less than or equal to the predetermined value T:
and (3) adjusting the temperature of the furnace tail or the furnace mouth by 0.5-2 ℃ each time, specifically 1 ℃, then carrying out secondary polysilicon layer forming treatment, measuring the thickness of the polysilicon layer formed by the secondary polysilicon layer forming treatment and obtaining a secondary furnace internal uniformity value, and repeating the steps of the secondary polysilicon layer forming treatment and the secondary furnace internal uniformity value until the last obtained furnace internal uniformity value is less than or equal to a preset value T.
In a further embodiment, when the temperature raising treatment or the temperature lowering treatment according to the step (3) is performed until the temperature difference between the furnace tail and the furnace mouth reaches 10 to 20 ℃, specifically, at most 20 ℃, specifically, the temperature of the furnace tail is higher than the temperature of the furnace mouth by 10 to 20 ℃, specifically, by more than 20 ℃, the temperature raising treatment or the temperature lowering treatment in the step (3) is stopped, and the flow rate of introducing the polysilicon precursor is adjusted.
Wherein, the stopping of the temperature increasing treatment or the temperature decreasing treatment in the step (3) and the starting of the flow adjustment of the introduction of the polysilicon precursor are carried out according to a method comprising the following steps:
c: comparing the thicknesses of the polycrystalline silicon layers at the furnace mouth and the furnace tail;
d: and increasing the introduction flow of the polysilicon precursor at the position with relatively small thickness of the polysilicon layer until the in-furnace uniformity value of the thickness of the polysilicon layer is less than or equal to a preset value T.
The thickness of the polycrystalline silicon layer at the furnace mouth and the furnace tail in the step c is the thickness of the polycrystalline silicon layer formed at the last time when the heating treatment or the cooling treatment is carried out until the temperature difference between the temperature of the furnace tail and the temperature of the furnace mouth reaches 10-20 ℃.
Increasing the introduction flow of the polysilicon precursor at the position where the thickness of the polysilicon layer is relatively small in the step d means: when the thickness of the polycrystalline silicon layer formed at the furnace mouth is smaller than that of the polycrystalline silicon layer formed at the furnace tail, the introduction flow of the polycrystalline silicon precursor at the furnace mouth is increased; and when the thickness of the polycrystalline silicon layer formed at the furnace mouth is higher than that of the polycrystalline silicon layer formed at the furnace tail, the introduction flow of the polycrystalline silicon precursor at the furnace tail is increased.
The adjustment of the introduction flow of the polysilicon precursor is started by a repairing scheme of adjusting the deposition temperature of the polysilicon layer at the furnace mouth and the furnace tail.
Therefore, the method for controlling the uniformity of the polycrystalline silicon layer in the furnace can ensure that the uniformity of the thickness among the polycrystalline silicon slices can be effectively adjusted when the polycrystalline silicon layers grow in situ on a plurality of substrates in batches, and the value of the uniformity of each polycrystalline silicon layer in the furnace is small and is not higher than 5%. The uniformity of the thickness among the polycrystalline silicon wafers is high, so that the uniformity of the thickness in the single polycrystalline silicon wafer is higher, and the value of the uniformity in the single polycrystalline silicon wafer, which particularly shows the thickness of each polycrystalline silicon layer, is smaller, such as not higher than 3%. Therefore, the method for controlling the uniformity of the polycrystalline silicon layer in the furnace can obviously improve the stable performance of the polycrystalline silicon field plate in the mass production process, thereby improving the yield of the polycrystalline silicon field plate in mass production, effectively improving the yield of the polycrystalline silicon field plate and reducing the cost of the polycrystalline silicon field plate.
The polysilicon field plate in the method for controlling the uniformity of the polysilicon layer in the furnace according to the embodiment of the above application may specifically include a substrate on which a connection region and a P + ring region are provided.
The P + ring area encloses the connection area, and specifically comprises a plurality of isolation islands, each isolation island is in a frame shape and is combined on the surface of the substrate, and the isolation islands are distributed at intervals and sequentially enclose the connection area. And a frame-type P + channel is formed between two adjacent isolation islands, and a polycrystalline silicon layer is filled in the P + channel. As an embodiment of the present application, a polysilicon field plate according to the embodiment of the present application is shown in fig. 1 and fig. 2, and includes a P + ring region 2 and a connection region 3 on a substrate 1. The P + ring region 2 is provided so as to surround the connection region 3. The P + ring region 2 specifically includes a plurality of isolation islands 21, such as an isolation island 211, an isolation island 212, an isolation island 213, and an isolation island 214, each isolation island of the isolation islands 211, 212, 213, and 214 is in a frame shape and is combined on the surface of the substrate 1, and the plurality of isolation islands 21, such as the isolation islands 211, 212, 213, and 214, are distributed at intervals and sequentially surround the connection region 3. A frame-type P + channel 22 is formed between two adjacent islands 21, specifically, a frame-type P + channel 221 is formed between the island 211 and the island 212, a frame-type P + channel 222 is formed between the island 212 and the island 213, and a frame-type P + channel 223 is formed between the island 213 and the island 214. The polysilicon layer 23 is filled in each P + channel 22, such as P + channel 221, P + channel 222, and P + channel 223. Since each P + channel 22 is of a frame shape, the polysilicon layer 23 filled in each P + channel 22 of the frame shape is also of a frame shape corresponding to the shape of each P + channel 22, and each polysilicon layer 23 is also sequentially arranged on the surface of the substrate 1 to sequentially surround the connection region 3 as each isolation island 21, specifically, the isolation island 211, the isolation island 212, the isolation island 213 and the isolation island 214.
The polysilicon field plates shown in fig. 1 and 2 are only an example of the polysilicon field plates of the embodiments of the present invention, but the polysilicon field plates of the embodiments of the present invention may also be a modification of the structures shown in fig. 1 and 2 or other structures. Regardless of the structure of the polysilicon field plate according to the embodiment of the present invention, as the embodiment of the present invention, the polysilicon layer filled in the P + trench is a composite polysilicon layer, that is, the polysilicon contained in the polysilicon field plate is ideally a composite polysilicon layer compared to a single-layer polysilicon, specifically, as shown in fig. 1 and 2, each polysilicon layer 23 filled in each P + trench 22, specifically, in each P + trench 221, P + trench 222, and P + trench 223, is a composite polysilicon layer. The structure of the composite polysilicon layer is shown in fig. 3, which includes a doped polysilicon layer 231 and an undoped polysilicon layer 232 laminated with the doped polysilicon layer 231, and a conductive modification layer 233 bonded to the surface of the undoped polysilicon layer 232 facing away from the doped polysilicon layer 231. That is, the composite polysilicon layer includes a doped polysilicon layer 231/an undoped polysilicon layer 232/a conductive modification layer 233, which are sequentially stacked. The doped polysilicon layer 231 is bonded to the bottom of the P + channel 21, and specifically, the doped polysilicon layer 231 is bonded to the surface of the bottom substrate 1 of the P + channel 21. The polysilicon layer 23 included in the polysilicon field plate of the embodiment of the present application includes the doped polysilicon layer 231 and the undoped polysilicon layer 232 stacked and combined with each other, and the conductive modified layer 233 forms a composite polysilicon layer structure together, and each layer can play a role in enhancing the conductivity, so that the conductivity of the polysilicon layer 23 is significantly mentioned.
In the embodiment, the thickness of the polysilicon layer 23, that is, the doped polysilicon layer 231 included in the composite polysilicon layer, may be controlled to 2000-2500A, specifically 2500A; the doping amount of the doping element contained in the doped polysilicon layer 231 may be 10 to 20: (100-200) sccm ratio of the doping amount formed in the deposition chamber. In a particular embodiment, the doped polysilicon layer includes a doping element including at least one of P, B, As. The thickness of the doped polysilicon layer 231 and the types and contents of the doping elements are controlled and adjusted, so that the conductivity of the doped polysilicon layer 231 can be improved, the conductivity synergy effect between the doped polysilicon layer 231 and the undoped polysilicon layer 232 and the conductive modified layer 233 can be improved, and the conductivity of the composite polysilicon layer can be improved. The thickness of the doped polysilicon layer 231 can be theoretically increased, and is ideally controlled within the above thickness range in consideration of the efficiency of the manufacturing process and the cost. In one embodiment, the doped polysilicon layer 231 contains the doping element distributed on the surface layer and inside the doped polysilicon layer 231, i.e. uniformly doped and distributed in the doped polysilicon layer 231. The uniform doping can be formed using, for example, in-situ doping deposition of the doping element with silicon as follows.
In an embodiment, the thickness of the undoped polysilicon layer 232 may be 2000-3000A, and specifically may be 2000A. Due to the doped polysilicon layer 231, the thickness of the undoped polysilicon layer 232 can be significantly reduced compared with the thickness (5000A) of the conventional single-layer polysilicon layer, and the thickness can be controlled within the range, so that the conductive synergistic effect between the layers contained in the composite polysilicon layer can be improved.
In an embodiment, the sheet resistance of the conductive modified layer 233 may be 11 ± 3 Ω/opening. The conductive modified layer 233 may be formed of POCl 3 And annealing after the surface of the undoped polysilicon layer is deposited. Specifically, the POCl can be prepared according to the existing POCl 3 The conductive modified layer 233 is formed by a doping modified single-layer polysilicon layer forming method.
In addition, the width of the polysilicon layer 23 filled in each P + trench 22, such as the P + trench 221, the P + trench 222, and the P + trench 223, i.e., the width of the composite polysilicon layer, is 3.0-4.0 μm, i.e., the width of each P + trench is 3.0-4.0 μm. Thus, the composite polysilicon layer is fully filled in accordance with the width of each P + channel 22.
In the polysilicon field plates of the above embodiments, the connection layer is further bonded to the surface of each polysilicon layer, the electrode is further provided on the connection layer, and the electrode bonded to the connection layer is in contact with each isolation island, specifically, as shown in fig. 4, the connection layer 25 is further bonded to the surface of each polysilicon layer 23, the electrode 4 is further provided on the connection layer 25, and the electrode 4 bonded to the connection layer 25 is in contact with each isolation island 21. The connection layer 25 and the electrode 4 may be the connection layer and the electrode included in the existing polysilicon field plate, for example, the connection layer 25 may be formed by doping B element and Pt element, which is configured to enhance the connectivity between the electrode and the polysilicon layer 23, for example, to enhance the conductivity of the connection between the two. The electrode 4 may be of aluminium metal.
The widths of the P + trenches 22, such as the P + trenches 221, 222, 223, included in the P + ring region 2 included in the polysilicon field plates of the above-described embodiments are the same as the widths of the polysilicon layers 23 filled therein. Each of the islands 21, such as the island 211, the island 212, the island 213, and the island 214, may have a height of 2.0 to 2.5 μm and a width of 20 to 35 μm. In an embodiment, the widths of the isolation islands 21 are different, for example, the difference between the widths of any two isolation islands in each isolation island 21 is 4.0-5.0 μm, and in a specific embodiment, the widths of the isolation islands 211, 212, and 213 are different20 μm, 28 μm, and 32 μm, respectively. The width of each isolation island 21 is set, so that the space between the composite polycrystalline silicon layers filled in each P + channel 21 is indirectly controlled, and the performances of the field plate of the polycrystalline silicon and the like are adjusted and improved. In a specific embodiment, the material of the isolated islands 21 may be SiO 2 。
The polysilicon field plate of the above embodiments may have the substrate 1 of silicon. In the substrate 1, a first P + layer 24 as shown in fig. 2 and 4 is further provided in a region opposed to each of the P + channels 22, such as the P + channel 221, the P + channel 222, and the P + channel 223. Since the first P + layers 24 are provided in regions opposed to the respective P + channels 22, such as the P + channel 221, the P + channel 222, and the P + channel 223, the first P + layers 24 are provided at intervals in a plurality of stages, and the number thereof is equal to the number of the P + channels 22.
The polysilicon field plate of the embodiment of the present application includes a connection region surrounded by the P + ring region in the above embodiments, and may include the structure shown in fig. 2 and 4: the connection region 3 is surrounded by the P + ring region 2 in each of the above embodiments, and includes a connection functional layer 31 laminated on the surface of the substrate 1, a P + layer 32 and an N + layer 33 layered in sequence from the connection functional layer 31 toward the inside of the substrate 1. The P + layer 32 and the N + layer 33 are distributed in the substrate 1. The connection functional layer 31 is used to enhance the connectivity between the electrode 4 and the connection region 3, such as to enhance the conductivity of the connection between the two. The thickness, material, and the like of the connection function layer 31 may be the same as those of the connection layer 25 in the P + ring region 2. The P + layer 32 may be formed using B-doped substrate 1, and it may be at the same depth in the substrate 1 as the first P + layer 24. The N + layer 33 may be formed by doping the substrate 1 with P element. Of course, the connection region included in the polysilicon field plate according to the embodiment of the present invention may be the existing polysilicon field plate connection region, or may be an improved structure based on each functional layer included in the existing polysilicon field plate connection region.
In addition, as shown in fig. 2 and fig. 4, the electrode 4 covers the surface of the connection region, that is, the electrode 4 included in the polysilicon field plate of the embodiment of the present application covers both the P + ring region 2 and the surface of the connection region 3.
Further, for the polysilicon field plate of the embodiment of the present application, before it is applied to the semiconductor power device, a protective layer (not shown) is further covered on the outer surface of the electrode 4. The protective layer protects the electrode 4 and other components from oxidation or contamination by other impurities during storage, transportation, etc.
Based on the structure of the polysilicon field plate in each embodiment, the polysilicon layer contained in the polysilicon field plate is set to be the composite polysilicon layer, specifically, the polysilicon layer is formed by the doped polysilicon layer and the undoped polysilicon layer which are mutually stacked and combined, so that each layer has the function of conductive synergy, the conductive performance of the composite polysilicon layer is obviously improved, the composite polysilicon layer is endowed with good conductivity, and the electric field effect of the polysilicon field plate is improved and widened.
As an example of the composite polysilicon layer shown in fig. 3, the process flow of the method for manufacturing a polysilicon field plate including a composite polysilicon layer is schematically shown in fig. 5, and with reference to fig. 1 to 4, the method for manufacturing a polysilicon field plate including a composite polysilicon layer according to the embodiment of the present application includes the following steps:
s01: providing a substrate 1 containing an isolation island, wherein a connection area 3 and a P + ring area 2 are arranged on the substrate, the P + ring area 2 comprises a plurality of isolation islands 21, each isolation island 21 is in a frame shape and is combined on the surface of the substrate 1, and the isolation islands 21 are distributed at intervals and sequentially surround the connection area 3; a frame-shaped P + channel 22 is formed between two adjacent isolated islands 21;
s02: forming a doped polysilicon layer in the P + channel 22 and on the surface of the connection region 3;
s03: forming an undoped polysilicon layer on the surface of the doped polysilicon layer 231 facing away from the substrate 1;
s04: forming a conductive modification layer on the outer surface of the undoped polysilicon layer;
s05: and reserving the doped polycrystalline silicon layer, the undoped polycrystalline silicon layer and the conductive modification layer formed in the P + channel, and removing the doped polycrystalline silicon layer, the undoped polycrystalline silicon layer and the conductive modification layer formed in the rest areas.
Wherein, the substrate of the isolated island of the step S01 is the single substrate in the step (1) in the furnace uniformity control method of the above polysilicon layer.
In a single substrate, the substrate and the connection region and the P + ring region provided on the substrate are all as the substrate, the connection region and the P + ring region included in the polysilicon field plate of the embodiment of the above application, specifically as the substrate 1, the connection region 3 and the P + ring region 2 in fig. 1, 2 and 4, wherein the functional layer structure included in the connection region 3 also includes a functional layer 31, a P + layer 32 and an N + layer 33 sequentially connected as shown in fig. 2 and 4.
The single substrate in S01 can be prepared according to the process including the steps shown in fig. 5 a to j. Wherein, in the process step shown in b, the epitaxial wafer shown in a is subjected to oxidation treatment to form SiO on the surface 2 A layer; in the process step shown in diagram d, it is for SiO 2 Etching the layer to form SiO 2 The layer etch forms a P + ring region 2 and an epitaxial wafer substrate region for forming a connection region 3. The P + ring region 2 includes a plurality of isolated islands 21 spaced from each other and P + channels 22 formed by two adjacent isolated islands 21; in the process step shown in f, N implantation, specifically P implantation, is performed on the exposed epitaxial wafer substrate region for forming the connection region 3; in the process step shown in the diagram h, the N implantation is performed to push the junction, so as to form an N + layer 33; in the process step shown in fig. j, the P + layer 32 is formed by performing a junction push after the B implantation. The process conditions and the like of the graphs a to j in fig. 5 can be controlled and adjusted according to the existing polysilicon field plate preparation process.
In S02, the doped polysilicon layer formed in the furnace including the P + channel 22 may be formed according to the method of forming the doped polysilicon layer of steps (2) and (3) in the above furnace uniformity control method of the polysilicon layer, specifically, the doped polysilicon layer 231 as in fig. 3.
Since the general polysilicon field plate has a smaller overall area and includes a smaller area of the single P + channel 22, the doped polysilicon layer formed in S02 is formed integrally on the overall surface of the substrate in step S01, so as to improve the forming efficiency of the doped polysilicon layer. When a plurality of substrates are simultaneously placed in the polysilicon deposition furnace in step (1) of the above method for controlling the uniformity in the furnace for a polysilicon layer, the doped polysilicon layer is not only formed on a single substrate but also simultaneously formed on a plurality of substrates in step S02. In order to realize that the inter-wafer thickness uniformity of the polycrystalline silicon layer meets the requirement of mass production, the above requirement that the in-furnace uniformity value of the thickness of the polycrystalline silicon layer is not higher than the predetermined value T, specifically not higher than 5%, is adopted to realize the control of the deposition method of the doped polycrystalline silicon layer by the above in-furnace uniformity control method of the polycrystalline silicon layer, and the requirement that the in-furnace uniformity value of the thickness of the polycrystalline silicon layer in mass production reaches the predetermined value T, specifically not higher than 5%.
In an embodiment, the method of forming a doped polysilicon layer at the surface including the inside of the P + channel 22 and the connection region comprises the steps of:
and introducing the gaseous doping element precursor and the first polysilicon precursor into a deposition chamber to form mixed gas, performing a first chemical reaction, and depositing in situ on the surface including the P + channel and the connecting region to form a doped polysilicon layer.
The gaseous doping element precursor and the first polycrystalline silicon precursor are led into the deposition cavity to form mixed gas, so that the doping precursor and the first polycrystalline silicon precursor can form uniform mixed gas, the doping precursor and the first polycrystalline silicon precursor react together, in-situ doping and synchronous deposition of the doping element are achieved, and the doping element can be uniformly distributed and doped in the doped polycrystalline silicon layer and on the surface layer.
In an embodiment, during the first chemical reaction, the doping element precursor and the first polysilicon precursor are continuously introduced into the deposition chamber in a gas flow manner to perform the first chemical reaction. The two precursors are led into the deposition cavity in a continuous mode to react, the concentration of the two precursors in the deposition cavity can be effectively guaranteed, the efficiency of the first chemical reaction is guaranteed, and the deposition efficiency of the doped polycrystalline silicon layer is improved. Meanwhile, the concentration ratio of the two precursors can be effectively ensured, and doping elements can be uniformly distributed and doped in the deposited doped polycrystalline silicon layer, so that the performance of the doped polycrystalline silicon layer is improved. In an embodiment, the dopant element precursor and the first polysilicon precursor may be 10-20 sccm: 100-200sccm, specifically 20 sccm: a rate ratio of 200sccm was introduced into the deposition chamber. The rate ratio can effectively preserve the concentration and the proportion of the two precursors in the deposition cavity, thereby effectively improving the deposition rate of the doped polycrystalline silicon layer and the doping uniformity of the doping elements. In order to further improve the mixing uniformity and the dispersion uniformity of the doping element precursor and the first polysilicon precursor in the deposition chamber and improve the thickness uniformity of the inter-wafer film layer in the mass production process, the doping element precursor and the first polysilicon precursor are introduced by adopting a mode of air inlet at two ends, such as through a dispersion pipe.
The conditions of the first chemical reaction should at least enable the doping element precursor and the first polysilicon precursor to react to generate the doping impurity and the silicon respectively, for example, in an embodiment, the temperature of the first chemical reaction may be 600 ℃ to 650 ℃, and the time may be 1 to 4 hours; the vacuum pressure in the deposition chamber may be 200-300 MT. By controlling and optimizing the conditions of the first chemical reaction, the efficiency of depositing the doped polysilicon layer and the thickness of the doped polysilicon layer can be adjusted, e.g., the thickness of the doped polysilicon layer can be controlled to control the thickness range of the doped polysilicon layer 231 above.
In particular embodiments, the dopant element precursor can include PH 3 、B 2 H 6 、AsH 3 The first polysilicon precursor may include SiH 4 Or SIH 4 And N 2 The mixed gas of (2). When the precursor of the doping element is PH 3 The first polysilicon precursor is SiH 4 When both are reacted under the conditions of the first chemical reaction, wherein SiH 4 Thermally decomposing the silicon into polysilicon at high temperature, and depositing; simultaneous pH 3 Decomposition into phosphorus and hydrogen: 2PH of 3 ＝2P+3H 2 And phosphorus is deposited and simultaneously carries out in-situ doping on the polysilicon to generate a phosphorus-doped polysilicon layer.
In a specific embodiment, the chemical deposition method is adopted and the conditions of the following sequence of first chemical reaction are controlled at pH 3 Is a precursor of a doping element, SiH 4 And leading the first polysilicon precursor into a reaction furnace through a dispersion pipe to perform a first chemical reaction, and performing integrated in-situ doping deposition on the whole surface of the substrate in the step S01 to form a doped polysilicon layer. The concrete design is as followsExamples 1 to 5, and 9 parallel samples were made, wherein examples 1 to 4 are doped polysilicon layers formed by deposition under the conditions set by the furnace in step (2) in the furnace uniformity control method for polysilicon layers of the above-mentioned embodiments. Embodiment 5 is a doped polysilicon layer formed by performing deposition under deposition conditions after performing temperature reduction treatment on a furnace mouth in step (3) in the method for controlling the uniformity of a polysilicon layer in the furnace according to the above-mentioned application. The doped polysilicon layers deposited in the embodiments 1 to 5 were used as samples, and the in-furnace uniformity value was measured and obtained by the method of step (3) in the method for controlling the in-furnace uniformity of the polysilicon layer according to the embodiment of the above application. The thickness values of the polysilicon layers and the in-wafer and inter-wafer uniformity test results are shown in the following table 1:
TABLE 1
As can be seen from table 1, the deposition rate of the in-situ doped polysilicon layer at the same position in the furnace as that in the furnace is selected, and the deposition rates of the in-situ doped polysilicon layers are slower under the addition of the first chemical reaction in example 1 compared with examples 1 to 5. In example 2, the deposition time was appropriately shortened, and the deposition rate of the doped polysilicon layer was found to be increased. In example 3, other process conditions were kept unchanged, and when the deposition time was continuously shortened to about 1H, the deposition rate was slightly increased, and it was found that the deposition rate was faster in the early stage when polysilicon was deposited by low-pressure in-situ doping, and the deposition rate of the doped polysilicon layer gradually slowed down as the film thickness increased due to saturation of the furnace atmosphere in the later stage. In example 4, low pressure deposition + N was used with other process conditions remaining unchanged 2 And when the gas atmosphere in the furnace is reduced by adopting a purging and redepositing mode, the deposition rate of the doped polycrystalline silicon layer is not obviously changed. In example 5, the process conditions were kept constant at other process conditionsOn the premise of the above, the influence of the vacuum pressure in the cavity on the deposition rate is small, and the deposition rate of the doped polycrystalline silicon layer has no obvious change.
Based on the data in table 1, the deposition rate of the doped polysilicon layer is gradually slowed down as the deposition rate increases along with the production of the film layer, and when the doped polysilicon layer is grown to about 2500A in a low-pressure in-situ doping manner, because the gas atmosphere in the furnace tube reaches a relatively saturated state, the growth rate of the doped polysilicon layer is extremely slow at the moment, and the process time is only prolonged so as not to meet the economic and mass production requirements of the product, so that when the doped polysilicon layer is formed, the growth thickness of the doped polysilicon layer is controlled to be 2500A, which is relatively beneficial to mass production.
Meanwhile, as can be seen from table 1, in the in-situ deposition process of the doped polysilicon layer, the thickness of the film layer in the wafer is uniform, and the uniformity in the wafer can be controlled to be less than 3%. When the doped polysilicon layer is formed in a mass production manner, the positions of the substrates in the furnace are different, the thicknesses of the formed doped polysilicon layers are different, for example, the thicknesses of the doped polysilicon layers formed at the furnace opening, the furnace and the furnace tail are different, the in-furnace uniformity control method of the polysilicon layer can be realized by adjusting the process in the embodiment 5 according to the process conditions, and the uniformity among the chips (in the furnace) is actually controlled to be less than 5%.
In S03, an undoped polysilicon layer is integrally formed on the entire surface of the doped polysilicon layer formed in step S02 to improve the efficiency of forming the undoped polysilicon layer. The undoped polysilicon layer formed in this step S03 may also be formed in the method of forming a doped polysilicon layer, specifically, the doped polysilicon layer 231 as in fig. 3, in steps (2) and (3) of the above method of controlling the furnace uniformity of a polysilicon layer.
In an embodiment, the method of forming an undoped polysilicon layer on the surface of a doped polysilicon layer including a P + channel 22 and a connection region stack includes the steps of:
introducing a gaseous second polysilicon precursor into the deposition chamber for a second chemical reaction, and depositing in situ on the surface of the doped polysilicon layer to form an undoped polysilicon layer;
in the embodiment, in the second chemical reaction process, the second polysilicon precursor is also continuously introduced into the deposition chamber in a gas flow manner to carry out the second chemical reaction, so that the concentration of the second polysilicon precursor in the deposition chamber can be effectively ensured, the efficiency of the second chemical reaction can be ensured, and the deposition efficiency of the undoped polysilicon layer can be improved. In one embodiment, the second polysilicon precursor can be introduced into the deposition chamber at a rate of 100-200 sccm. The rate can effectively preserve the concentration of the second polysilicon precursor in the deposition chamber, thereby effectively improving the deposition rate of the undoped polysilicon layer. In order to further improve the uniformity of the dispersion of the second polysilicon precursor in the deposition chamber and the uniformity of the thickness of the inter-wafer film layer in the mass production process, the second polysilicon precursor may also be introduced by means of two-end gas inflow, for example, through a dispersion tube.
The conditions of the second chemical reaction should at least enable the second polysilicon precursor to react to respectively generate silicon, and in the embodiment, the temperature of the second chemical reaction can be 600-650 ℃ for 1-4 hours; the vacuum pressure value in the deposition chamber can be 200-300 MT. By controlling and optimizing the conditions of the second chemical reaction, the efficiency of depositing the undoped polysilicon layer and the thickness of the undoped polysilicon layer can be adjusted, e.g., the thickness of the undoped polysilicon layer can be controlled to control the thickness range of the undoped polysilicon layer 232. Wherein the second polysilicon precursor may be the same as the first polysilicon precursor, e.g., may comprise SiH 4 Or SIH 4 And N 2 The mixed gas of (1).
In addition, as can be seen from Table 2 below, POCl was set aside 3 A deposition process, which is only seen from the step S02 and the step S03, in the method for manufacturing a polysilicon field plate according to the embodiment of the present application, a process for forming a polysilicon layer is divided into two parts, where the first part of the process is a low-voltage in-situ doping manner in the step S02, and a doped polysilicon layer of about 2500A can be directly generated; in the process of the following step S03, the process is performed by N 2 Purging the furnace tube and pipeline to purge the special gas in the furnace tube, cooling, introducing silane, thermally decomposing and depositing silane on the bottom doped polysilicon layer under low pressure to generate top undoped polysilicon layer with thickness controlled to 2000AThe thickness of the over-practically complete doped polysilicon layer + undoped polysilicon layer can be controlled to be 2500A +2000A — 4500A.
Further, as shown in tables 1 and 2, the uniformity of the thickness of each doped polysilicon layer/undoped polysilicon layer in the wafer can be effectively ensured by the method of forming the polysilicon layer in two steps in steps S02 and S03, for example, the uniformity of the thickness of the doped polysilicon layer/undoped polysilicon layer in table 2 is 2.61% or less, and is less than 3% at most, and the uniformity of the thickness of the wafer is high.
Meanwhile, as can be seen from tables 1 and 2, in the actual method of forming a polycrystalline silicon layer in two steps and mass production, the thickness uniformity between the doped polycrystalline silicon layer and the undoped polycrystalline silicon layer formed in two steps is reduced. As probably be because the furnace tail department connects the vacuum pump and continues the evacuation operation as above, lead to this furnace tail position gas atmosphere to have a certain degree loss, the test result piece homogeneity is relatively poor between the piece, and furnace tail position needs to carry out the temperature compensation of pertinence to with piece homogeneity value control within 5%. If the deposition process is adjusted, such as the method of properly heating the temperature of the furnace tail or cooling the furnace mouth according to the deposition rate of a test furnace, or further setting an inclined temperature zone in the polycrystalline silicon deposition furnace and adjusting the temperature of the inclined temperature zone in a targeted manner, the test furnace is performed again until the uniformity value among the wafers is controlled within 5 percent, so that the deposition film thickness data of the doped polycrystalline silicon layer/the undoped polycrystalline silicon layer meets the requirements of the process of 4500 +/-400A, the uniformity value among the wafers of the thickness is less than 3 percent, and the uniformity value among the furnaces (wafers among the wafers) of the thickness is less than 5 percent.
In S04, the entire surface of the undoped polysilicon layer formed in step S03 is integrally formed with a conductive modified layer to improve the efficiency of the formation of the conductive modified layer.
After the conductive modification layer is formed on the outer surface of the undoped polysilicon layer, the doped polysilicon layer/undoped polysilicon layer/conductive modification layer sequentially stacked and combined in the P + channel 22 forms a composite polysilicon layer included in the polysilicon field plate according to the embodiment of the above application, specifically, as shown in fig. 3: including a doped polysilicon layer 231/an undoped polysilicon layer 232/a conductive modification layer 233, which are sequentially stacked. For example, the conditions for forming the conductive modified layer may be controlled so that the sheet resistance of the surface of the formed conductive modified layer is 11 ± 3 Ω/kou.
In an embodiment, a method of forming a conductive modification layer on an outer surface of an undoped polysilicon layer includes the steps of:
adding POCl 3 And introducing the silicon wafer into a deposition cavity for carrying out a third chemical reaction, carrying out in-situ deposition on the surface of the undoped polysilicon layer, and then sequentially carrying out annealing treatment and floating acid treatment to form the conductive modified layer.
By using POCl 3 And (4) performing surface treatment on the undoped polysilicon layer in the step S03 to activate surface impurities, so that a conductive modification layer is formed on the surface of the undoped polysilicon layer, and is bonded on the surface of the undoped polysilicon layer in situ to perform the function of modifying the surface of the undoped polysilicon layer in a conductive manner. Wherein, POCl 3 The third chemical reaction and the annealing treatment can be carried out by selecting proper process temperature and process time to carry out POCl in a temperature range of 950-980 DEG C 3 Deposition + anneal to deposit and activate impurities.
In an embodiment, based on the in-situ doping to form the doped polysilicon layer (designated as DPOLY) in step S02 and the in-situ doping to form the undoped polysilicon layer (designated as UPOLY) in step S03, POCl is performed on the surface of the undoped polysilicon layer 3 And (4) depositing, bleaching, and annealing to form the composite polycrystalline silicon layer contained in the polycrystalline silicon field plate of the embodiment of the application. Wherein, POCl 3 The deposition process conditions are controlled as follows: annealing (Anneal) at 980 ℃ for 30min and 980 ℃ for 30min, LN 2 And LO 2 The flow rate is adjusted according to the surface concentration and the thickness of the oxide layer. The post-deposition bleaching acid post-treatment may be: DHF is added for 3-5min at a ratio of 1:50 to remove the grown oxide layer and residual phosphorus impurities. According to the conditions, the following examples 6 to 8 were specifically designed, and 5 parallel samples were made, for each POCl in examples 6 to 8 3 And measuring the thickness of the composite polycrystalline silicon layer formed by the deposition process, the thickness of the annealed composite polycrystalline silicon layer and the conductive modified layer, namely the sheet resistance and other data on the surface of the composite polycrystalline silicon layer. Wherein, the embodiments 6 to 7 are the trial furnace of the step (2) in the furnace uniformity control method of the polysilicon layer of the embodiment of the above applicationAnd setting the deposition condition to deposit and form the composite polycrystalline silicon layer. Embodiment 8 is a composite polycrystalline silicon layer formed by performing deposition under deposition conditions after performing temperature rise processing on a furnace tail in step (3) in the method for controlling uniformity of a polycrystalline silicon layer in a furnace according to the above-mentioned application. The composite polysilicon layers deposited in each of examples 6 to 8 were used as samples, and the in-wafer and in-furnace uniformity values were measured and obtained by the method of step (3) in the method for controlling the in-furnace uniformity of the polysilicon layer according to the example of the above application. The thickness values of the composite polysilicon layers and the in-wafer and inter-wafer uniformity test results are shown in the following table 2:
TABLE 2
As can be seen from Table 2, the POCl in the present step S04 is combined with the polycrystalline deposition process of the above steps S02 and S03 3 The deposition process can effectively ensure the uniformity in the composite polysilicon layer thickness slice formed by each doped polysilicon layer/undoped polysilicon layer/conductive modified layer, for example, the maximum value of the in-slice uniformity value of the composite polysilicon layer thickness in table 2 is 2.61%, which is less than 3%, and the in-slice thickness uniformity is high.
Meanwhile, comparative example POCl 3 The thickness of the composite polysilicon layer after deposition and annealing is reduced to a certain extent after actual annealing, which may be caused by recrystallization of the polysilicon layer after annealing.
In addition, the above-mentioned process steps of steps S02 and S04 are process steps as shown in fig. 5, fig. K.
In S05, the doped polysilicon layer, the undoped polysilicon layer, and the conductive modification layer formed on the surface of the remaining region such as the connection region are removed, and the doped polysilicon layer, the undoped polysilicon layer, and the conductive modification layer formed in the P + channel are left. The method of removing the doped polysilicon layer and the undoped polysilicon layer formed on the surface of the remaining region such as the connection region may be a method of removing by photolithography and etching. And removing the doped polysilicon layer/undoped polysilicon layer/conductive modification layer formed on the surface of the connection region in the rest region to expose the surface of the connection region, so as to facilitate the formation of other components.
Step S05 is a process step as shown in fig. 5, fig. m.
In addition, according to the structure included in the polysilicon field plate of the embodiment of the present application, after step S05, the method further includes the following steps:
s06: forming a connection layer by performing processes as shown in fig. 5 n to q while leaving the surface of the conductive modification layer and the exposed surface of the connection region after the processing of step S05, and forming a connection layer 25 as shown in fig. 2 and 4 on the surface of the conductive modification layer and the exposed surface of the connection region;
s07: performing a step of forming the electrode 4 as shown in the r diagram to the s diagram in fig. 5 on the surface of the connection layer 25 and the surface of the P + ring region 2;
s08: and (5) forming a protective layer (such as PI) on the surface of the electrode 4 of the polysilicon shown by the s diagram in the figure.
Therefore, the preparation method of the polycrystalline silicon field plate containing the composite polycrystalline silicon layer can effectively form a composite polycrystalline silicon layer structure formed by sequentially laminating and combining the doped polycrystalline silicon layer/the non-reference polycrystalline silicon layer/the conductive modified layer in the P + channel between two adjacent isolation islands, so that each layer contained in the composite polycrystalline silicon layer has a conductive synergistic effect, and the prepared polycrystalline silicon field plate has high and wide electric field effects. Furthermore, the forming method of the doped polycrystalline silicon layer and the non-polycrystalline silicon layer is controlled and adjusted, so that the uniform distribution of doping elements in the doped polycrystalline silicon layer can be improved, and the uniformity of the thickness in a chip and the uniformity among chips can be improved. And the formed polycrystalline silicon layer is a doped polycrystalline silicon layer/undoped polycrystalline silicon layer, so that the subsequent polycrystalline etching difficulty is reduced, and the shape of the etched film layer is better compared with that of the traditional single-layer undoped UPOLY structure under the same dry etching condition. In addition, the preparation method of the polycrystalline silicon field plate containing the composite polycrystalline silicon layer is easy to control, and the prepared composite polycrystalline silicon layer can be stable in structural performance, so that the stable performance of the polycrystalline silicon field plate is ensured, the yield of mass production is improved, the efficiency is high, and the cost is reduced.
The polycrystalline silicon field plate based on the embodiment of the application has the composite polycrystalline silicon layer structure as shown in fig. 3, and has high conductivity and good conductivity. The uniformity in and among the polycrystalline silicon layers can be effectively controlled during mass production, and the yield of mass production is effectively improved, so that the electric field effect of the polycrystalline silicon field plate is improved and widened, and the applicability of the polycrystalline silicon field plate is effectively enhanced. Such as fast recovery diodes, field effect transistors. And the corresponding performance of the semiconductor power devices is improved, for example, when the semiconductor power devices are externally pressurized, the reliability of the semiconductor power devices can be effectively improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method for controlling the uniformity of a polycrystalline silicon layer in a furnace comprises the following steps:
placing a plurality of substrates in a polycrystalline silicon deposition furnace, wherein the substrates are at least distributed in the furnace at a furnace mouth and a furnace tail; the substrate is provided with a connecting area and a P + ring area, the P + ring area comprises a plurality of isolation islands, each isolation island is in a frame shape and is combined on the surface of the substrate, and the isolation islands are distributed at intervals and sequentially surround the connecting area; a frame-shaped P + channel is formed between two adjacent isolation islands;
adjusting the conditions in the polycrystalline silicon deposition furnace to polycrystalline silicon deposition conditions, introducing gaseous polycrystalline silicon precursors into the polycrystalline silicon deposition furnace from the furnace mouth and the furnace tail in a mode of simultaneously introducing gas from two ends of the furnace mouth and the furnace tail to react and deposit, and forming a polycrystalline silicon layer on the surface including the P + channel and the connection region;
and at least measuring the thickness of the polycrystalline silicon layer formed at the furnace mouth and the furnace tail and obtaining the uniformity value in the furnace, and when the uniformity value in the furnace of the thickness of the polycrystalline silicon layer is larger than a preset value T, carrying out temperature rise treatment on the furnace tail or carrying out temperature reduction treatment on the furnace mouth.
2. The furnace uniformity control method of claim 1, wherein: the temperature raising treatment or the temperature lowering treatment is to adjust the temperature according to the following temperature adjusting rate until the uniformity value in the furnace of the thickness of the polycrystalline silicon layer is less than or equal to the preset value T:
after the temperature of the furnace tail or the furnace mouth is adjusted to 0.5-2 ℃ each time, carrying out secondary polysilicon layer forming treatment and measuring the thickness of the polysilicon layer formed by the secondary polysilicon layer forming treatment to obtain a secondary furnace internal uniformity value, and repeating the steps of the secondary polysilicon layer forming treatment and the secondary furnace internal uniformity value obtaining until the last obtained furnace internal uniformity value is less than or equal to the preset value T;
and/or
The predetermined value T is 5%.
3. The furnace uniformity control method according to any one of claims 1-2, wherein: and when the temperature difference between the temperature of the furnace tail and the temperature of the furnace opening reaches 10-20 ℃ due to the temperature rise treatment or the temperature reduction treatment, stopping continuing the temperature rise treatment or the temperature reduction treatment, and regulating the flow of the introduced polycrystalline silicon precursor.
4. The furnace uniformity control method of claim 3, wherein: the method for adjusting the flow of the introduced polysilicon precursor comprises the following steps:
comparing the thicknesses of the polycrystalline silicon layers at the furnace mouth and the furnace tail;
and increasing the introduction flow of the polysilicon precursor at the position with the relatively small thickness of the polysilicon layer until the furnace uniformity value of the thickness of the polysilicon layer is less than or equal to the preset value T.
5. The furnace uniformity control method according to any one of claims 1 to 2 and 4, wherein: an inclined temperature area is arranged in the polycrystalline silicon deposition furnace.
6. The furnace uniformity control method of claim 5, wherein: the inclined temperature zone comprises a furnace mouth temperature zone, a furnace temperature zone and a furnace tail temperature zone; the temperature of the furnace mouth temperature zone is higher than that of the furnace tail temperature zone, and the temperature of the furnace tail temperature zone is higher than that of the furnace temperature zone.
7. The method for controlling uniformity in a furnace according to any one of claims 1 to 2, 4 and 6, wherein: the polycrystalline silicon precursor is introduced into the polycrystalline silicon deposition furnace from two ends of a dispersion pipe; and/or
The polysilicon layer includes a doped polysilicon layer and/or an undoped polysilicon layer.
8. The furnace uniformity control method of claim 7, wherein: the polycrystalline silicon layer comprises a doped polycrystalline silicon layer and an undoped polycrystalline silicon layer which is combined with the doped polycrystalline silicon layer in a laminated mode, and the method for introducing the gaseous polycrystalline silicon precursor into the polycrystalline silicon deposition furnace to react comprises the following steps:
synchronously introducing gaseous doping element precursors and first polysilicon precursors into the polysilicon deposition furnace from the furnace mouth and the two ends of the furnace tail to form mixed gas, carrying out a first chemical reaction and depositing, and forming a doped polysilicon layer in the P + channel and on the surface of the connecting region;
vacuumizing the polysilicon deposition furnace and N 2 And after the purging treatment, introducing a gaseous second polycrystalline silicon precursor into the polycrystalline silicon deposition furnace for a second chemical reaction and deposition, and forming an undoped polycrystalline silicon layer on the surface of the doped polycrystalline silicon layer.
9. The furnace uniformity control method of claim 8, wherein: the above-mentioned
In the first chemical reaction process, the doping element precursor and the first polysilicon precursor are prepared by the following steps of (10-20): (100-200) introducing the rate ratio of sccm into the polysilicon deposition furnace; and/or
The above-mentionedThe doping element precursor comprises PH 3 、B 2 H 6 、ASH 3 At least one of; and/or
The first polysilicon precursor and/or the second polysilicon precursor comprises pure SIH 4 Or SIH 4 And N 2 The mixed gas of (1).
10. The method as claimed in claim 8 or 9, wherein the thickness of the doped polysilicon layer is 2000-2500A; and/or
The thickness of the undoped polysilicon layer is 2000-3000A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210748350.0A CN115132579A (en) | 2022-06-29 | 2022-06-29 | Method for controlling uniformity of polycrystalline silicon layer in furnace |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210748350.0A CN115132579A (en) | 2022-06-29 | 2022-06-29 | Method for controlling uniformity of polycrystalline silicon layer in furnace |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115132579A true CN115132579A (en) | 2022-09-30 |
Family
ID=83380850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210748350.0A Pending CN115132579A (en) | 2022-06-29 | 2022-06-29 | Method for controlling uniformity of polycrystalline silicon layer in furnace |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115132579A (en) |
-
2022
- 2022-06-29 CN CN202210748350.0A patent/CN115132579A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4698104A (en) | Controlled isotropic doping of semiconductor materials | |
| CN103972059B (en) | Method for forming semiconductor region in the trench | |
| CN101471254B (en) | Method for forming dielectric films | |
| CN107026070B (en) | The production method of semiconductor device | |
| WO2001041544A2 (en) | Deposition of gate stacks including silicon germanium layers | |
| JP5018473B2 (en) | Manufacturing method of semiconductor device | |
| US8102052B2 (en) | Process for the simultaneous deposition of crystalline and amorphous layers with doping | |
| JP2911694B2 (en) | Semiconductor substrate and method of manufacturing the same | |
| CN115132579A (en) | Method for controlling uniformity of polycrystalline silicon layer in furnace | |
| JPH03173420A (en) | Implantation of impurity in semiconductor inner wall | |
| CN115425073A (en) | Semiconductor device and manufacturing method thereof | |
| KR20230132455A (en) | Method for manufacturing epitaxial wafers | |
| CN115064587A (en) | Polysilicon field plate and preparation method and application thereof | |
| WO2021140763A1 (en) | Epitaxial wafer manufacturing method and epitaxial wafer | |
| US8158495B2 (en) | Process for forming a silicon-based single-crystal portion | |
| CN117747422B (en) | Low-stress deep trench polycrystalline gate and preparation method thereof | |
| KR20090017074A (en) | Method for deposition epitaxial silicon layer | |
| US20230223333A1 (en) | Semiconductor device with horizontally arranged capacitor | |
| CN117558762A (en) | Groove type MOSFET and preparation method | |
| JPH021124A (en) | Manufacture of dielectric film | |
| US20140231893A1 (en) | Capacitor and preparation method thereof | |
| CN117672815A (en) | SiC epitaxial wafer and preparation method thereof | |
| JPH08306863A (en) | Manufacture of capacitor | |
| CN117373907A (en) | Method for manufacturing semiconductor structure | |
| CN114335248A (en) | Method for preparing passivated contact cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |