CN115117151A - IGBT chip with composite cellular structure and manufacturing method thereof - Google Patents
IGBT chip with composite cellular structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
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- 210000004027 cell Anatomy 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 230000001413 cellular effect Effects 0.000 claims description 15
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- 238000000151 deposition Methods 0.000 claims description 14
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
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- 239000001301 oxygen Substances 0.000 claims description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention provides an IGBT chip with a composite cellular structure and a manufacturing method thereof, wherein a first P well region in the IGBT chip is positioned in a first region of a monocrystalline silicon substrate, a second P well region is positioned in a second region of the monocrystalline silicon substrate, the depth of the first P well region is greater than that of the second P well region, a first part of a polycrystalline silicon gate region is positioned in the first P well region, and a second part of the polycrystalline silicon gate region is positioned in the second P well region. According to the invention, two kinds of cells with different threshold voltages are designed in the cell area of the chip, in the process of turning off the chip, the channel of the high-threshold cell is firstly closed, but the channel of the low-threshold cell is still kept open for a period of time, so that the electron current component is reduced in a step manner, the partial current ratio of the space charge area is born, the increase of hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Description
Technical Field
The invention relates to the technical field of IGBT chip preparation, in particular to an IGBT chip with a composite cellular structure and a manufacturing method thereof.
Background
The IGBT is a high-power semiconductor discrete device, combines the advantages of high switching frequency and easy control of an MOS device and the high-current processing capacity of a BJT device, and has wide application in the fields of industrial frequency conversion, consumer electronics, rail transit, new energy, aerospace, and the like.
In the IGBT chip of the trench gate, under the blocking state, a PN junction composed of a front surface P trap and an N drift region bears bus voltage, the bus voltage under the normal condition is only 50% -70% of the nominal voltage of the IGBT chip, namely, the PN junction can completely bear a spike electric field generated by the bus voltage, and the PN junction is rarely subjected to avalanche breakdown under the static blocking state.
However, in the dynamic process of turning on the IGBT chip to the off state, carriers in the drift region of the device near the front cathode side are swept out first, the current component of the carriers in the region begins to change, and since the channel of the IGBT device is turned off first in the off process, electron current is no longer injected into the drift region from the cathode side, but due to the presence of load inductance in an external circuit, the current cannot suddenly change, so that the hole current component rises sharply, and further the effective doping concentration Neff = ND + p-n in the region is greater than the fixed charge density ND, and the slope of the electric field rises, so that the electric field spike at the PN junction is raised, and the dynamic avalanche voltage that the device can bear is much lower than the static avalanche voltage. When the turn-on voltages of all trench cells in the active region are consistent, the channel is almost simultaneously closed, no electron current is injected any more in the process of expanding the space charge region, and almost all the region is hole current, so that the risk of dynamic avalanche is increased.
Disclosure of Invention
In view of this, the invention provides a method for manufacturing an IGBT chip with a composite cell structure, which solves the technical problem in the prior art that when the turn-on voltages of all trench cells in an active region of an IGBT chip with a trench gate are consistent, the risk of occurrence of dynamic avalanche is easily increased.
In order to achieve the above object, the present invention provides an IGBT chip with a composite cell structure, including a cell region and a terminal region; the cell region comprises a monocrystalline silicon substrate, a gate oxide layer, a polycrystalline silicon gate region, a first P well region, a second P well region, an N-type doped region, a P + contact region, an insulating dielectric layer, a front metal layer, a passivation layer, a back buffer layer, a back anode region and a back metal layer, wherein the first P well region is located in a first region of the monocrystalline silicon substrate, the second P well region is located in a second region of the monocrystalline silicon substrate, the depth of the first P well region is larger than that of the second P well region, a first part of the polycrystalline silicon gate region is located in the first P well region, and a second part of the crystalline silicon gate region is located in the second P well region.
In order to achieve the above object, the present invention further provides a method for manufacturing an IGBT chip having a composite cell structure, including the steps of:
s1, growing a field oxide layer and doping a field limiting ring region of the terminal region;
s2, selectively corroding the field oxide layer in the cell area, photoetching, opening a part of area patterns in the cell area, injecting P-type ions into the cell area for the first time, and pushing impurities after removing the photoresist;
s3, injecting P-type ions into the cell area for the second time to form a first P well area and a second P well area, wherein the depth of the first P well area is greater than that of the second P well area;
s4, growing a gate oxide layer and filling polycrystalline silicon;
s5, doping an N-type source region;
s6, depositing an isolation medium layer and etching a contact hole;
s7, forming a front metallization and a passivation layer;
and S8, thinning and metalizing the back of the wafer.
Preferably, the step S1 specifically includes:
selecting an N-type monocrystalline silicon substrate, and growing a field oxide layer by adopting a wet oxygen process;
selectively corroding the field oxide layer in the field limiting ring area of the terminal area, injecting B + ions, and pushing impurities after photoresist removal.
Preferably, in the step S2;
the first P-type ion implantation in the cell region is B + ion with implantation dosage of 1E13-5E14 and implantation energy of 120-300 keV;
the temperature of impurity promotion after photoresist removal is 1050-.
Preferably, the step S3 specifically includes:
injecting P-type ions into the cell region for the second time, wherein the injection dosage is 5E12-1E14, and the injection energy is 80-140 keV;
the impurities are pushed at the temperature of 900-1150 ℃ for 90-150 min.
Preferably, the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD (plasma enhanced chemical vapor deposition) process, and etching a cell area groove;
growing a sacrificial oxide layer, and removing the sacrificial oxide layer;
and growing a gate oxide layer, performing polysilicon filling growth based on an LPCVD (low pressure chemical vapor deposition) process, etching the polysilicon layer, and forming a gate electrode and a Busbar wire.
Preferably, the step S5 specifically includes:
turning the wafer, removing polysilicon on the back, turning the wafer and cleaning;
etching the oxide layer in the cellular area, and reducing the thickness of the oxide layer;
and (3) source region N-type ion implantation: injecting P + ions for the first time, injecting As + ions for the second time, and annealing in a furnace tube after photoresist removal.
Preferably, the step S6 specifically includes:
depositing an isolation dielectric layer to form a USG + BPSG double-layer structure, and etching a contact hole;
and (3) injecting a contact hole region: injecting BF2 ions for the first time, injecting B + ions for the second time, and annealing in a furnace tube after photoresist removal.
Preferably, the step S7 specifically includes:
depositing a metal layer on the front surface, carrying out dry etching patterning, forming a passivation layer by using PI glue Coating, and carrying out photoetching patterning.
Preferably, the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, reducing the thickness, and injecting P + ions into the back to form a buffer layer;
injecting B + ions into the anode on the back, annealing the furnace tube to activate impurities, and depositing a metal layer on the back.
The beneficial effects of adopting the above embodiment are:
the channel length of the first P well region unit cell is larger than that of the second P well region, so that the threshold voltage of the first P well region unit cell is higher than that of the second P well region, the channel of the first P well region unit cell is firstly closed in the process of turning off a chip, but the channel of the second P well region unit cell is still kept on for a period of time, so that the electronic current component is in a step-shaped reduction, partial current proportion of a space charge region is born, the increase of hole current is effectively inhibited, the increase of effective doping concentration Neff of the region is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Furthermore, the invention designs two kinds of unit cells with different threshold voltages in the unit cell area of the chip, in the process of turning off the chip, the channel of the high-threshold unit cell is firstly closed, but the channel of the low-threshold unit cell is still kept to be opened for a period of time, so that the electron current component is reduced in a step shape, the partial current ratio of the space charge area is born, the increase of the hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural change diagram of an embodiment of an IGBT chip after step S1 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 2 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S2 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 3 is a schematic structural change diagram of an embodiment of an IGBT chip after step S3 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 4 is a schematic structural change diagram of an embodiment of an IGBT chip after step S4 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 5 is a schematic structural change diagram of an embodiment of an IGBT chip after step S5 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 6 is a schematic structural change diagram of an embodiment of an IGBT chip after step S6 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 7 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S7 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 8 is a schematic structural change diagram of an embodiment of the IGBT chip after step S8 is executed in the method for manufacturing the IGBT chip with the composite cell structure according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing embodiments of the present invention, a brief description of related terms or common sense will be made:
the IGBT structure: the IGBT generally includes a cell region and a terminal region, and the cell region structures are all structures whose central axes are symmetric, so that each structure is not labeled in the drawings in this specification, and if not labeled, it is determined according to the symmetric labeling.
For an accurate description of the reference numerals, they are first presented in table 1.
Table 1: reference numeral correspondence table
The invention provides an IGBT chip with a composite cellular structure and a manufacturing method thereof.A channel of a high-threshold cellular is firstly closed, but a channel of a low-threshold cellular is still kept opened for a period of time in a cellular area of the chip through two cellular designs with different threshold voltages, so that an electron current component is reduced in a step manner, partial current occupation ratio of a space charge area is born, increase of hole current is effectively inhibited, increase of effective doping concentration Neff of the area is relieved, and dynamic avalanche breakdown voltage of the chip is improved.
In an embodiment of the present invention, referring to fig. 1 to 8, the present invention provides a method for manufacturing an IGBT chip having a composite cell structure, including the following steps:
s1, growing a field oxide layer and doping a field limiting ring region of the terminal region; referring to fig. 1, the step S1 specifically includes:
selecting an N-type FZ monocrystalline silicon substrate 101/201, wherein the surface of the monocrystalline silicon wafer is a (100) crystal plane, the resistivity is 30-90 omega cm, and growing a field oxide layer by adopting a wet oxygen process to form a field oxide layer 102/202, wherein the temperature of the wet oxygen process is 800-1050 ℃, and the thickness of the oxide layer is 1-3 mu m;
selectively etching the field oxide layer in the field limiting ring region of the terminal region, implanting B + ions to form a P-type doped region 203, wherein the implantation dosage is 8E13-5E14, the implantation energy is 80-140keV, the impurity is driven after photoresist removal, the temperature is 1000-1200 ℃, and the time is 300-600 min.
S2, doping the first P well region; referring to fig. 2, the step S2 specifically includes:
selectively corroding the field oxide layer in the cell area, photoetching, and opening partial area patterns in the cell area;
the first P well region P type ion implantation (B + ion) in the cell region forms a P type doped region 103, the implantation dosage is 1E13-5E14, and the implantation energy is 120-300 keV;
after photoresist removal, impurities are pushed forward at 1050 ℃ and 1150 ℃ for 200 min and 350 min.
S3, doping the second P well region; referring to fig. 3, the step S3 specifically includes:
performing second P-type ion implantation (B + ion) in the P-well region of the cell region, wherein the implantation dose of the B + ion is 5E12-1E14, and the implantation energy is 80-140 keV;
after impurity propulsion, a first P well region 1031 and a second P well region 1032 are formed, and the depth of the first P well region 1031 is greater than that of the second P well region 1032, wherein the impurity propulsion temperature is 900-1150 ℃, and the time is 90-150 min.
It should be noted that, steps S2 to S3 are one of the core innovations of the present invention, and a first P-well region and a second P-well region with different depths are formed through two P-well region P-type ion implantations, and the channel length of the first P-well region unit cell is longer than that of the second P-well region, so that the threshold voltage is also higher than that of the second P-well region, and in the process of turning off the chip, the channel of the first P-well region unit cell is first turned off, but the channel of the second P-well region unit cell is still turned on for a while, so that the electron current component is reduced in a stepwise manner, and the partial current ratio of the space charge region is borne, thereby effectively suppressing the increase of the hole current, and alleviating the increase of the effective doping concentration Neff of the region, thereby increasing the dynamic avalanche breakdown voltage of the chip.
S4, growing a gate oxide layer and filling polycrystalline silicon; referring to fig. 4, the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD process, wherein the thickness is 5000-10000A, and the depth of a trench in a cellular area is 4-7 mu m;
growing a sacrificial oxide layer with the thickness of 800-1200A, and removing the sacrificial oxide layer;
the gate oxide layer grows with the thickness of 1000-1200A, the polysilicon filling growth is carried out based on the LPCVD process, the thickness is 8000-12000A, the polysilicon is etched, and a gate electrode (namely a polysilicon gate region 104/204) and a Busbar routing are formed.
S5, doping an N-type source region; referring to fig. 5, the step S5 specifically includes:
turning over the wafer, removing polysilicon on the back, turning over the wafer, and cleaning;
etching the oxide layer in the cellular region, and reducing the thickness of the oxide layer to 100-500A;
and (3) forming an N-type doped region 105 by source region N-type ion implantation: injecting P + ions for the first time, wherein the injection dosage is 1E15-8E15, and the injection energy is 40-80 keV; implanting As + ions for the second time at an implantation dose of 1E15-8E15 and an implantation energy of 40-100keV, and performing furnace annealing (simultaneously performing polysilicon oxidation) after photoresist stripping at a temperature of 800-.
S6, depositing an isolation medium layer and etching a contact hole; referring to fig. 6, the step S6 specifically includes:
carrying out 106/206 deposition on an isolation medium layer to form a USG + BPSG double-layer structure with the total thickness of 9000-12000A, and etching the contact hole, wherein the over-etching depth of the lower layer Si is 0.2-0.5 mu m;
and (3) injecting a contact hole region: implanting BF2 ions for the first time, wherein the implantation dosage is 5E14-8E15, and the implantation energy is 20-80 keV; implanting B + ions for the second time, with the implantation dosage of 1E14-5E15, the implantation energy of 40-100keV, and annealing in a furnace tube after photoresist stripping at the temperature of 700-1000 ℃ for 30-60 min.
S7, forming a front metallization and a passivation layer; referring to fig. 7, the step S7 specifically includes:
depositing a metal layer 107/207 on the front surface, wherein the thickness is 4-8 μm, performing dry etching patterning, forming a passivation layer 108/208 by using PI glue Coating, and performing photoetching patterning, wherein the thickness is 8-12 μm.
S8, thinning and metalizing the back of the wafer; referring to fig. 8, the step S8 specifically includes:
grinding the back of the wafer, removing the silicon oxide, reducing the thickness to 60-150 μm, implanting P + ions to the back to form a buffer layer, with the implantation dose being 2E11-1E13 and the implantation energy being 200-900 keV;
injecting B + ions into the anode on the back side, wherein the injection dosage is 1E12-8E13, the injection energy is 20-50keV, the impurity is activated by furnace tube annealing at the temperature of 300-.
It should be noted that, in fig. 8, the two P well regions with different depths formed through steps S2 and S3 are a first P well region 1031 and a second P well region 1032, respectively, and it can be seen that the first P well region 1031 is located in a first region of the single-crystal silicon substrate 101, the second P well region 1032 is located in a second region of the single-crystal silicon substrate 101, the depth of the first P well region 1031 is greater than that of the second P well region 1032, the channel length of the first P well region 1031 is greater than that of the second P well region 1032, a first portion (i.e., close to the first region) of the polysilicon gate region is located in the first P well region 1031, and a second portion (i.e., close to the second region) of the polysilicon gate region is located in the second P well region 1032.
Through the preparation processes of the steps S1-S8, the IGBT chip with the composite cellular structure provided by the invention is obtained.
In an embodiment of the present invention, the IGBT chip having a composite cell structure provided in the above embodiments includes a cell region and a terminal region.
The cell region includes a single crystal silicon substrate 101, a gate oxide layer 102, a polysilicon gate region 104, a first P well region 1031, a second P well region 1032, an N-type doped region 105, a P + contact region (not shown), an isolation dielectric layer 106, a front metal layer 107, a passivation layer 108, a back buffer layer (not shown), a back anode region and a back metal layer 110, wherein the first P well 1031 is located in a first region of the single crystal silicon substrate 101, the second P well region 1032 is located in a second region of the single crystal silicon substrate 101, the depth of the first P well region 1031 is greater than that of the second P well region 1032, the channel length of the first P well region 1031 is greater than that of the second P well region 1032, and a first portion (i.e., proximate to the first region) of the polysilicon gate region is located at the first P-well region 1031 and a second portion (i.e., proximate to the second region) of the polysilicon gate region is located at the second P-well region 1032. Specifically, the length of the channel of the first P-well cellular is greater than that of the second P-well cellular, so that the threshold voltage of the first P-well cellular is also greater than that of the second P-well cellular, and in the process of turning off the chip, the channel of the first P-well cellular is firstly closed, but the channel of the second P-well cellular is still kept on for a period of time, so that the electron current component is reduced in a step manner, the proportion of partial current in the space charge region is born, the increase of hole current is effectively inhibited, the increase of the effective doping concentration Neff in the region is alleviated, and the dynamic avalanche breakdown voltage of the chip is increased.
The basic structure of the terminal area comprises a monocrystalline silicon substrate 201, a terminal P-type main junction and a field limiting ring, a Busbar wiring (Poly) of a groove-type polycrystalline silicon grid 203, a USG/BPSG dielectric layer 206, a grid metal 207, a source metal, a PI glue passivation layer 208, a back Buffer layer (N-doping), a back anode, a back metal layer 210 and the like.
In summary, the length of the channel of the first P well region unit cell is greater than that of the second P well region, so that the threshold voltage is also higher than that of the second P well region, and in the process of turning off the chip, the channel of the first P well region unit cell is firstly closed, but the channel of the second P well region unit cell is still kept opened for a period of time, so that the electron current component is reduced in a step manner, the partial current ratio of the space charge region is born, the increase of the hole current is effectively inhibited, the increase of the effective doping concentration Neff of the region is alleviated, and the dynamic avalanche breakdown voltage of the chip is improved.
Furthermore, the invention designs two kinds of cells with different threshold voltages in the cell area of the chip, in the process of turning off the chip, the channel of the high-threshold cell is firstly closed, but the channel of the low-threshold cell is still kept on for a period of time, so that the electron current component is in a step-shaped reduction, the partial current ratio of the space charge area is born, the increase of the hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
The method for manufacturing the IGBT chip with the composite cell structure provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as limiting the present invention.
Claims (10)
1. An IGBT chip with a composite cellular structure is characterized by comprising a cellular region and a terminal region;
the cell region comprises a monocrystalline silicon substrate, a gate oxide layer, a polycrystalline silicon gate region, a first P well region, a second P well region, an N-type doped region, a P + contact region, an insulating dielectric layer, a front metal layer, a passivation layer, a back buffer layer, a back anode region and a back metal layer, wherein the first P well region is located in a first region of the monocrystalline silicon substrate, the second P well region is located in a second region of the monocrystalline silicon substrate, the depth of the first P well region is larger than that of the second P well region, a first part of the polycrystalline silicon gate region is located in the first P well region, and a second part of the crystalline silicon gate region is located in the second P well region.
2. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the method for manufacturing the IGBT chip comprises the steps of:
s1, growing a field oxide layer and doping a field limiting ring region of the terminal region;
s2, selectively corroding the field oxide layer in the cell area, photoetching, opening a part of area patterns in the cell area, injecting P-type ions into the cell area for the first time, and pushing impurities after removing the photoresist;
s3, injecting P-type ions into the cell area for the second time to form a first P well area and a second P well area, wherein the depth of the first P well area is greater than that of the second P well area;
s4, growing a gate oxide layer and filling polycrystalline silicon;
s5, doping an N-type source region;
s6, depositing an isolation medium layer and etching a contact hole;
s7, forming a front metallization and a passivation layer;
and S8, thinning and metalizing the back of the wafer.
3. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S1 specifically includes:
selecting an N-type monocrystalline silicon substrate, and growing a field oxide layer by adopting a wet oxygen process;
selectively corroding the field oxide layer in the field limiting ring area of the terminal area, injecting B + ions, and pushing impurities after photoresist removal.
4. The method for manufacturing an IGBT chip with a composite cell structure according to claim 2, wherein in the step S2;
the first P-type ion implantation in the cell region is B + ion with implantation dosage of 1E13-5E14 and implantation energy of 120-300 keV;
the temperature of impurity promotion after photoresist removal is 1050-.
5. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S3 specifically includes:
injecting P-type ions into the cell region for the second time, wherein the injection dosage is 5E12-1E14, and the injection energy is 80-140 keV;
the impurities are pushed at the temperature of 900-1150 ℃ for 90-150 min.
6. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD (plasma enhanced chemical vapor deposition) process, and etching a cell area groove;
growing a sacrificial oxide layer, and removing the sacrificial oxide layer;
and growing a gate oxide layer, performing polysilicon filling growth based on an LPCVD (low pressure chemical vapor deposition) process, etching the polysilicon layer, and forming a gate electrode and a Busbar wire.
7. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S5 specifically includes:
turning the wafer, removing polysilicon on the back, turning the wafer again, and cleaning;
etching the oxide layer in the cellular area, and reducing the thickness of the oxide layer;
and (3) source region N-type ion implantation: injecting P + ions for the first time, injecting As + ions for the second time, and annealing in a furnace tube after photoresist removal.
8. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S6 specifically includes:
depositing an isolation dielectric layer to form a USG + BPSG double-layer structure, and etching a contact hole;
and (3) injecting a contact hole region: injecting BF2 ion for the first time, injecting B + ion for the second time, and annealing in a furnace tube after removing the photoresist.
9. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S7 specifically includes:
depositing a metal layer on the front surface, carrying out dry etching patterning, forming a passivation layer by using PI glue Coating, and carrying out photoetching patterning.
10. The method for manufacturing the IGBT chip with the composite cell structure according to claim 2, wherein the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, reducing the thickness, and injecting P + ions into the back to form a buffer layer;
injecting B + ions into the anode on the back, annealing the furnace tube to activate impurities, and depositing a metal layer on the back.
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