CN108682688A - A kind of composite grid igbt chip with three dimension channel - Google Patents
A kind of composite grid igbt chip with three dimension channel Download PDFInfo
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- CN108682688A CN108682688A CN201810148909.XA CN201810148909A CN108682688A CN 108682688 A CN108682688 A CN 108682688A CN 201810148909 A CN201810148909 A CN 201810148909A CN 108682688 A CN108682688 A CN 108682688A
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- 239000002131 composite material Substances 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 75
- 229920005591 polysilicon Polymers 0.000 claims abstract description 74
- 230000001413 cellular effect Effects 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 230000005611 electricity Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a kind of composite grid igbt chips with three dimension channel, include multiple cellulars, cellular includes：Trench polysilicon silicon gate electrode positioned at the intermediate region of cellular；Surround the first oxide layer of trench polysilicon silicon gate electrode；Pass through the p-well region formed to cellular in the two side areas implanting p-type impurity of groove；By the doped region formed by the two side areas of groove is injected separately into impurity to p-well region, wherein the width of the doped region is less than the width of p-well region, doped region includes N++ doped regions and P++ doped regions；Positioned at second oxide layer of the cellular in the two side areas of doped region, the second oxide layer is to cover the surface of the two side areas of two p-well regions, surface and the part doped region of doped region are not arranged for p-well region；The planar polysilicon gate electrode formed in the second oxide layer；The third oxide layer of overlay planes polygate electrodes.The present invention can promote the current density of igbt chip, to reduce its conduction voltage drop.
Description
Technical field
The present invention relates to technical field of semiconductor device more particularly to a kind of composite grid IGBT cores with three dimension channel
Piece.
Background technology
From IGBT before and after 1980 (Insulated Gate Bipolar Transistor, insulated gate bipolar crystal
Pipe) device come out since, since it had not only had the characteristics that bipolar transistor on-state voltage drop was low, current density is big, but also have
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor field
Effect transistor) the features such as pipe input impedance is high, fast response time, it is widely used in rail traffic, intelligent grid, industry become
The fields such as frequency and new energy development.
Fig. 1 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art with planar gate structure.Such as Fig. 1 institutes
Show, includes mainly：Substrate 101, N well regions 102, p-well region 103, N+ doped regions 104, P+ doped regions 105, planar gate 106, grid
Oxide layer 107, passivation layer 108 and metal layer 109.The major advantage of igbt chip shown in FIG. 1 with planar gate structure
It is that technique makes simply, it is low for equipment requirements, and planar gate good pressure-resistant performance, sturdy degree is high, thus can be used for working environment
Compare severe place.But since its channel region is on surface, gully density is limited by chip list size, is caused
Conductivity modulation effect in igbt chip body is weaker, and conduction voltage drop is higher.
Fig. 2 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art with trench gate structure.Such as Fig. 2 institutes
Show, includes mainly：Substrate 201, N well regions 202, p-well region 203, N+ doped regions 204, P+ doped regions 205, trench-gate 206, grid
Oxide layer 207, passivation layer 208 and metal layer 209.In order to reduce the conduction voltage drop of igbt chip, using ditch as shown in Figure 2
Slot grid structure replaces planar gate structure.As shown in Fig. 2, forming trench-gate by etching technics so that raceway groove enters substrate body
It is interior, it realizes raceway groove by being laterally converted into longitudinal direction, to realize one-dimensional current channel, effectively eliminates the JFET in plane gate groove
Effect, while cellular size is reduced, so that gully density is no longer limited by chip list area, greatly improves cellular density to big
Amplitude promotes chip current density.But with the increase of groove grid density, chip saturation current is excessive, weakens chip
Short-circuit capability, to affect the safety operation area of chip.
Fig. 3 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art for having and accompanying grid and trench gate structure.
As shown in figure 3, including mainly：Substrate 301, N well regions 302, p-well region 303, N+ doped regions 304, P+ doped regions 305, trench-gate
306, grid 307, gate oxide 308, passivation layer 309 and metal layer 310 are accompanied.In order to balance between short-circuit capability and current density
Tradeoff, trench gate structure as shown in Figure 2 is replaced using the structure for accompanying grid and trench-gate to coexist as shown in Figure 3.
There is certain limitation in the bottom of trench-gate in Fig. 2 and Fig. 3 to the damping ability of igbt chip.Itself and Fig. 1 institutes
The igbt chip with planar gate structure shown is compared, and it is resistance to also to sacrifice plane gate part while promoting igbt chip performance
Pressure and sturdy performance.
Invention content
In view of the above technical problems, the present invention provides a kind of composite grid igbt chip with three dimension channel, including it is more
A cellular, the cellular include：
The groove made of the intermediate region of the cellular downwards etching, it is more that the interior setting polysilicon of the groove forms groove
Crystal silicon gate electrode；
Surround the first oxide layer of the trench polysilicon silicon gate electrode；
Pass through two p-well regions formed to the cellular in the two side areas implanting p-type impurity of the groove, wherein institute
The junction depth for stating p-well region is less than the depth of the groove；
Pass through two doped regions formed by the two side areas of the groove is injected separately into impurity to described two p-well regions
Domain, wherein the width of the doped region is less than the width of the p-well region, the doped region includes that adjacent doped N-type is miscellaneous
The N++ doped regions of matter and the P++ doped regions of doped p-type impurity；
Cover the surface of the two side areas of described two p-well regions, the p-well region be not arranged the doped region surface and
Two the second oxide layers of the part doped region；
Two planar polysilicon gate electrodes of polysilicon formation are respectively set in described two second oxide layers；
It is covered each by two third oxide layers of two planar polysilicon gate electrodes.
In one embodiment, the cellular further include be located at the p-well region below and with the lower surface of the p-well region and
The N well regions of side contact, the width of the N well regions are more than the width of the p-well region.
In one embodiment, second oxide layer includes close to the first zoneofoxidation of the doped region, away from institute
It states the second zoneofoxidation of doped region and is smoothly connected the third zoneofoxidation of first zoneofoxidation and the second zoneofoxidation, it is described
First zoneofoxidation at least covers surface and the part doped region that the doped region is not arranged for the p-well region, and described
The thickness in titanium dioxide area is more than the thickness of first zoneofoxidation；
The planar polysilicon gate electrode thickness is uniformly arranged.
In one embodiment, multiple N++ doped regions and P++ doped regions prolong in the groove along first cellular surface
It is intervally arranged on the direction stretched.
In one embodiment, the planar polysilicon gate electrode is not electrically connected with the trench polysilicon silicon gate electrode.
In one embodiment, the planar polysilicon gate electrode passes through external gate with the trench polysilicon silicon gate electrode
Cabling is electrically connected.
In one embodiment, the cellular further includes：
It is covered each by two passivation layers of two third oxide layers；
On the region for not covering the third oxide layer and passivation layer in described two passivation layers and the doped region
The metal layer of formation.
In one embodiment, the third oxidated layer thickness is uniformly arranged, and the passivation layer thickness is uniformly arranged.
In one embodiment, the junction depth of the doped region is less than the junction depth of the p-well region.
In one embodiment, the cellular is bar shaped structure cell, rectangular structure cell or hexagonal cells structure.
Compared with prior art, one or more embodiments of the invention can have the following advantages that：
1) igbt chip provided by the invention has the composite grid of planar polysilicon gate electrode and trench polysilicon silicon gate electrode
Structure had not only been utilized the high feature of raceway groove and gully density in trench polysilicon silicon gate electrode body, but also planar polysilicon grid is utilized
The small feature of electrode parasitic capacitance, to significantly promoted igbt chip density, and retain trench polysilicon silicon gate electrode low pass consumption,
The characteristic of high current density and the wide safety operation area of plane polygate electrodes.
2) trench polysilicon silicon gate electrode peace face polygate electrodes of the invention share same active area, are formed and surround N+
The three dimension channel in+area can promote the gully density of igbt chip, to promote the conducting electric current ability of igbt chip, with drop
Its low conduction voltage drop.
3) thicker gate oxide is arranged in non-channel region by the present invention, forms the planar polysilicon grid electricity of step structure
Pole can reduce the output capacitance of igbt chip, to reduce parasitic capacitance effect when igbt chip switch.
4) N++ doped regions and P++ doped regions are intervally arranged in igbt chip provided by the invention, can not only make full use of
Channel area also reduces the dead resistance of igbt chip base area, to improve the latch-up immunity of igbt chip.
Other features and advantages of the present invention will be illustrated in the following description, and partly becomes from specification
It is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by wanting in specification, right
Specifically noted structure is sought in book and attached drawing to realize and obtain.
Description of the drawings
Attached drawing is used to provide further understanding of the present invention, and a part for constitution instruction, the reality with the present invention
It applies example and is used together to explain the present invention, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 shows the diagrammatic cross-section of half cellular of the igbt chip in the prior art with planar gate structure；
Fig. 2 shows the sections of half cellular of the igbt chip in the prior art with trench polysilicon gate electrode structure
Schematic diagram；
Fig. 3 shows half cellular in the prior art for having and accompanying the igbt chip of grid and trench polysilicon gate electrode structure
Diagrammatic cross-section；
Fig. 4 shows the structural representation of the composite grid igbt chip with three dimension channel in first embodiment of the invention
Figure；
Fig. 5 shows the structural representation of the composite grid igbt chip with three dimension channel in second embodiment of the invention
Figure.
Specific implementation mode
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to be applied to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technique effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
It is formed by technical solution within protection scope of the present invention.
First embodiment
The composite grid igbt chip of the present embodiment includes multiple cellulars.In order to illustrate more clearly of the composite grid of the present embodiment
Igbt chip is described in detail by taking the structural schematic diagram of single bar shaped cellular shown in Fig. 4 as an example below.
Fig. 4 is the structural schematic diagram of the composite grid igbt chip with three dimension channel in first embodiment of the invention.Such as
Shown in Fig. 4, including substrate 1, the cellular being set on substrate 1 and the N-type buffer layer 2,3 and of P-type layer that are set to below substrate 1
Anode metal layer 4.Wherein, cellular includes mainly：Trench polysilicon silicon gate electrode 5, the p-well region 7, two of the first oxide layer 6, two are mixed
Miscellaneous region (doped region includes N++ doped regions 8 and P++ doped regions 9), two the second oxide layers, 10, two planar polysilicon grid
11, two third oxide layers 12 of electrode, passivation layer 13 and cathode metal layer 14.
Specifically, trench polysilicon silicon gate electrode 5 is set in the groove of cellular intermediate region, and the first oxide layer 2 surrounds ditch
Slot polygate electrodes 5.Wherein, groove is to etch downwards to be formed in the intermediate region of cellular, and grid oxygen is arranged in grooved inner surface
Change layer, be provided in the groove of gate oxide and be filled with polysilicon, forms trench polysilicon silicon gate electrode 5, trench polysilicon Si-gate electricity
The upper surface of pole 5 covers gate oxide.It is the first oxide layer 2 that the gate oxide of trench polysilicon silicon gate electrode 5 is surrounded at this.
Two p-well regions 7 are the knots of p-well region 7 by being formed to cellular in the two side areas implanting p-type impurity of groove
The deep depth for being less than groove.In the present embodiment, p type impurity can be boron impurity.
Two doped regions are formed by the two side areas of groove is injected separately into impurity by two p-well regions 7,
The width of middle doped region is less than the width of p-well region 7, and the junction depth of doped region is less than the junction depth of p-well region 7.Doped region includes
The N++ doped regions 8 of doped N-type impurity and the P++ doped regions 9 of doped p-type impurity.In the present embodiment, N-type impurity can be phosphorus
Impurity, p type impurity can be boron impurity.
In a preferred embodiment of the invention, doped region includes multiple N++ doped regions 8 and P++ doped regions 9, and N++ mixes
Miscellaneous area 8 and P++ doped regions 9 are intervally arranged along the direction of first cellular surface.Specifically, multiple N++ can be respectively formed by mask
Doped region 8 and P++ doped regions 9, N++ doped regions 8 are parallel with P++ doped regions 9 to be arranged side by side.The three-dimensional of xyz as shown in Figure 4 is sat
In mark system, if groove along the direction that first cellular surface extends be z-axis, N++ doped regions 8 and P++ doped regions 9 in groove along first cellular surface
It is intervally arranged on the direction (i.e. z-axis direction) of extension, it is ensured that source electrode N++ doped regions 8 and the fully short circuit of P++ doped regions 9, from
And can ensure enough gully densities, while promoting the latch-up immunity of igbt chip.
Two the second oxide layer 10 covering substrates 1 are not arranged in the surface of the two side areas of two p-well regions 7, p-well region 1 to be mixed
The surface in miscellaneous region and part doped region.Two planar polysilicon gate electrodes 11 are located in two the second oxide layers 10.
Two third oxide layers 12 are covered each by two planar polysilicon gate electrodes 11.In the present embodiment, planar polysilicon gate electrode
11 are formed using polysilicon.
In a preferred embodiment of the invention, the second oxide layer 10 includes the first zoneofoxidation of close doped region, the back of the body
The second zoneofoxidation from doped region and the third zoneofoxidation for being smoothly connected the first zoneofoxidation and the second zoneofoxidation, the first oxidation
Area at least covers surface and the part doped region that doped region is not arranged for p-well region 7, and the thickness of the second zoneofoxidation is more than the first oxygen
Change the thickness in area.Two 11 thickness of planar polysilicon gate electrode are uniformly arranged, and form the planar polysilicon gate electrode of step structure
11.Since thicker gate oxide being arranged in non-channel region, the planar polysilicon gate electrode of step structure is formed, can be reduced
The output capacitance of igbt chip, to reduce parasitic capacitance effect when igbt chip switch.It should be noted that " lean on herein
The distance between the first zoneofoxidation that first zoneofoxidation of nearly doped region " refers to and doped region are less than the first default threshold
Value, it is default that " the second zoneofoxidation for deviating from doped region " refers to that the distance between the second zoneofoxidation and doped region are more than second
Threshold value, the second predetermined threshold value are more than the first predetermined threshold value.First predetermined threshold value and the second predetermined threshold value can be according to actual product need
Depending on asking.
Particularly, it by reasonably controlling the implantation dosage and diffusion junction depth of p-well region 7 and N++ doped regions 8, may be implemented
The igbt chip is below planar polysilicon gate electrode and trench polisilicon gate electrode sidewall is formed simultaneously raceway groove, constitutes and surrounds N+
The three dimension channel of+doped region 8.Specifically, as shown in figure 4, the starting point for the raceway groove that planar polysilicon gate electrode 11 controls is located at N++
Doped region 8 it is laterally outermost, the terminal of raceway groove that planar polysilicon gate electrode 11 controls is located at the laterally outermost of p-well region 7.
The starting point for the raceway groove that trench polysilicon silicon gate electrode 5 controls is located at the lower surface of N++ doped regions 8, and trench polysilicon silicon gate electrode 5 controls
The terminal of raceway groove be located at the lower surface of p-well region 7.
In a preferred embodiment of the invention, planar polysilicon gate electrode 11 can be with 5 electricity of trench polysilicon silicon gate electrode
Property connects to form common compound gate electrode.Specifically, planar polysilicon gate electrode 11 can lead to trench polysilicon silicon gate electrode 5
Cross the electric connection of external gate cabling.Planar polysilicon gate electrode 11 takes synchronous control with trench polysilicon silicon gate electrode 5, i.e., together
Shi Kaiqi is simultaneously turned off.As long as should be noted that the raceway groove and trench polysilicon Si-gate electricity that planar polysilicon gate electrode 11 controls
The threshold voltage of raceway groove that pole 5 controls is in range relatively, so that it may be opened while to realize raceway groove at two and simultaneously
Shutdown.
In a preferred embodiment of the invention, planar polysilicon gate electrode 11 can not also be with trench polysilicon silicon gate electrode
5 are electrically connected, respectively as two independent gate electrode co- controlling igbt chips.In the present embodiment, with plane polycrystalline
Silicon gate electrode 11 is used as master control grid, using trench polysilicon silicon gate electrode 5 as auxiliary control gate.Trench polysilicon silicon gate electrode 5 can be with
Postpone to open after 11 a period of time of planar polysilicon gate electrode, planar polysilicon gate electrode 11 turns off for a period of time in advance.
During this, the raceway groove that trench polysilicon silicon gate electrode 5 controls can inject electronics when igbt chip is opened, and enhance igbt chip
Conductivity modulation effect, reduce the conduction voltage drop of igbt chip.The raceway groove that trench polysilicon silicon gate electrode 5 controls is closed in igbt chip
Pinch off before disconnected reduces electron injection, reduces nonequilibrium carrier concentration in igbt chip body in advance, is closed to accelerate igbt chip
It is disconnected, and then reduce turn-off time and the shutdown power consumption of igbt chip.
Alternatively, using trench polysilicon silicon gate electrode 5 as master control grid, controlled using planar polysilicon gate electrode 11 as auxiliary
Grid.Planar polysilicon gate electrode 11 can postpone to open after 5 a period of time of trench polysilicon silicon gate electrode, in advance trench polisilicon
Gate electrode 5 turns off for a period of time.In the process, the raceway groove that planar polysilicon gate electrode 11 controls can be opened in igbt chip
When inject electronics, enhance the conductivity modulation effect of igbt chip, reduce the conduction voltage drop of igbt chip.Planar polysilicon gate electrode
The raceway groove of 11 controls pinch off before igbt chip turns off, reduces electron injection, reduces non-equilibrium current-carrying in igbt chip body in advance
Sub- concentration to accelerate igbt chip shutdown, and then reduces turn-off time and the shutdown power consumption of igbt chip.
Passivation layer 13 is covered each by two third oxide layers 12, and cathode metal layer 14 is located in passivation layer 13 and doped region
On the region for not covering third oxide layer 12.In a preferred embodiment of the invention, 12 thickness of third oxide layer is uniformly arranged,
13 thickness of passivation layer is uniformly arranged.
N-type buffer layer 2 is located at the lower surface of substrate 1, and P-type layer 3 is located at the lower surface of N-type buffer layer 2, anode metal layer 4
Positioned at the lower surface of P-type layer 3.
Cellular in the present embodiment uses bar shaped structure cell.It is of course also possible to by adjusting p-well region 7 and source region domain
Realize rectangular structure cell and hexagonal cells structure.
In conclusion first, the composite grid igbt chip provided by the invention with three dimension channel had both had plane polycrystalline
The surface channel of silicon gate electrode control also has the internal raceway groove of groove gate control, constitutes the three-dimensional ditch around N++ doped regions
Road greatly increases the gully density of igbt chip, to improve the current density of igbt chip.Second, the present invention carries
Thicker gate oxide is set in the composite grid igbt chip with three dimension channel supplied in non-channel region, step structure is formed
Planar polysilicon gate electrode, the output capacitance of igbt chip can be reduced, to reduce igbt chip switch when parasitism electricity
Hold effect.Third, N++ doped regions and P++ adulterate section in the composite grid igbt chip provided by the invention with three dimension channel
Every arrangement, channel area can be not only made full use of, also reduces the dead resistance of igbt chip base area, to improve IGBT
The latch-up immunity of chip.
Second embodiment
The present embodiment is advanced optimized to first embodiment.
Fig. 5 is the structural schematic diagram of the composite grid igbt chip with three dimension channel in second embodiment of the invention.Such as
Shown in Fig. 5, increase N well regions 15 in cellular shown in Fig. 4.N well regions 15 be located at the lower section of p-well region 7 and with the lower surface of p-well region 7
It is contacted with side, the width of N well regions 15 is more than the width of p-well region 7.
In the present embodiment, N well regions are increased in the periphery of p-well region, further increase igbt chip drift region electricity
Lead mudulation effect.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not limited to the present invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But protection scope of the present invention still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of composite grid igbt chip with three dimension channel, which is characterized in that including multiple cellulars, the cellular includes：
The groove made of the intermediate region of the cellular downwards etching, the interior setting polysilicon of the groove form trench polisilicon
Gate electrode；
Surround the first oxide layer of the trench polysilicon silicon gate electrode；
By two p-well regions formed to the cellular in the two side areas implanting p-type impurity of the groove, wherein the P
The junction depth of well region is less than the depth of the groove；
By two doped regions formed by the two side areas of the groove is injected separately into impurity to described two p-well regions,
The width of the wherein described doped region is less than the width of the p-well region, and the doped region includes adjacent doped N-type impurity
The P++ doped regions of N++ doped regions and doped p-type impurity；
Cover the surface of the two side areas of described two p-well regions, the surface and part of the doped region are not arranged for the p-well region
Two the second oxide layers of the doped region；
Two planar polysilicon gate electrodes of polysilicon formation are respectively set in described two second oxide layers；
It is covered each by two third oxide layers of two planar polysilicon gate electrodes.
2. composite grid igbt chip according to claim 1, which is characterized in that the cellular further includes being located at the p-well
The N well regions contacted below area and with the lower surface of the p-well region and side, the width of the N well regions are more than the width of the p-well region
Degree.
3. composite grid igbt chip according to claim 1 or 2, it is characterised in that：
Second oxide layer includes the first zoneofoxidation close to the doped region, the second oxidation away from the doped region
Area and the third zoneofoxidation for being smoothly connected first zoneofoxidation and the second zoneofoxidation, first zoneofoxidation at least cover institute
Surface and the part doped region that the doped region is not arranged for p-well region are stated, the thickness of second zoneofoxidation is more than institute
State the thickness of the first zoneofoxidation；
The planar polysilicon gate electrode thickness is uniformly arranged.
4. composite grid igbt chip according to claim 1 or 2, which is characterized in that multiple N++ doped regions and P++
Doped region is intervally arranged in the groove along the direction that first cellular surface extends.
5. composite grid igbt chip according to claim 1 or 2, which is characterized in that the planar polysilicon gate electrode is not
It is electrically connected with the trench polysilicon silicon gate electrode.
6. composite grid igbt chip according to claim 1 or 2, which is characterized in that the planar polysilicon gate electrode with
The trench polysilicon silicon gate electrode is electrically connected by external gate cabling.
7. composite grid igbt chip according to claim 3, which is characterized in that the cellular further includes：
It is covered each by two passivation layers of two third oxide layers；
It does not cover in described two passivation layers and the doped region and is formed on the region of the third oxide layer and passivation layer
Metal layer.
8. composite grid igbt chip according to claim 7, which is characterized in that the third oxidated layer thickness is uniformly set
It sets, the passivation layer thickness is uniformly arranged.
9. composite grid igbt chip according to claim 1 or 2, which is characterized in that the junction depth of the doped region is less than
The junction depth of the p-well region.
10. composite grid igbt chip according to claim 1 or 2, which is characterized in that the cellular is bar shaped cellular knot
Structure, rectangular structure cell or hexagonal cells structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810148909.XA CN108682688B (en) | 2018-02-13 | 2018-02-13 | Composite gate IGBT chip with three-dimensional channel |
| PCT/CN2018/106113 WO2019157819A1 (en) | 2018-02-13 | 2018-09-18 | Igbt chip having composite gate and three-dimensional trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810148909.XA CN108682688B (en) | 2018-02-13 | 2018-02-13 | Composite gate IGBT chip with three-dimensional channel |
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| CN108682688B CN108682688B (en) | 2020-11-10 |
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| CN110444594A (en) * | 2019-08-02 | 2019-11-12 | 扬州国扬电子有限公司 | A kind of the grid-controlled type power device and its manufacturing method of low dead resistance |
| CN111933687A (en) * | 2020-07-07 | 2020-11-13 | 电子科技大学 | Lateral power device with high safety working area |
| CN115083895A (en) * | 2022-07-21 | 2022-09-20 | 深圳芯能半导体技术有限公司 | Manufacturing method of field stop IGBT chip with back variable doping structure |
| CN115117151A (en) * | 2022-08-25 | 2022-09-27 | 深圳芯能半导体技术有限公司 | IGBT chip with composite cellular structure and manufacturing method thereof |
| CN115394834A (en) * | 2022-07-29 | 2022-11-25 | 安世半导体科技(上海)有限公司 | IGBT cellular structure with control grid and carrier storage layer and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
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| CN108682688B (en) | 2020-11-10 |
| WO2019157819A1 (en) | 2019-08-22 |
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