CN114995576B - Bidirectional self-bias bipolar current mirror circuit adapting to low-voltage operation - Google Patents
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Abstract
The invention provides a bi-directional self-bias bipolar current mirror circuit adapting to low-voltage operation, which comprises: a current source current mirror circuit and a current sinking current mirror circuit; the current source current mirror circuit and the current sinking current mirror circuit are both used as power supply connecting ends by a public power supply positive end and a public power supply negative end; the current source current mirror circuit comprises a current source input side PNP tube P1, a first base current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2; the current sinking current mirror circuit comprises a current sinking input side NPN tube N1, a second base current compensation circuit, a second beta-helper circuit, a current sinking output side NPN tube and a bias current source I1. The invention uses the emitter current of the first emitter follower as the current source of the second base current compensation circuit to supply, the emitter current of the second emitter follower as the current source of the first base current compensation circuit to supply bias current mutually, and the invention does not depend on an extra bias circuit, and simultaneously meets the low-voltage work.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a bidirectional self-bias bipolar current mirror circuit suitable for low-voltage operation.
Background
1. The existing current mirror has the problem of precision when being correspondingly used as a current source or a current sink, and the reason is that the base electrode of the current mirror flows to too much current; in addition, the triode device is arranged at different positions of the chip layout, so that the wiring lengths of the emitters are different, the resistance values of parasitic resistances are different, and the collector currents of the BJT device are very sensitive to the BE junction voltage, so that the parasitic resistances of the emitter wirings have a great influence on the mirror image precision.
2. The existing precision optimization scheme generally adopts a mode of reducing the base flow direction current of a current mirror structure and setting an emitter feedback resistor to improve the precision, for example, the base flow direction current is reduced by adopting a beta-helper structure (the electric connection between the collector and the base of a triode at the input side of the current mirror is replaced by triode gain connection, the current at the input side of the current mirror is more precisely matched with the current at the output side of the current mirror by reducing the current distribution of the collector to the base of the triode at the input side of the current mirror), or the base current compensation scheme is adopted, but the precision is further optimized, as shown in (formula) in fig. 1 to 5, and more bias circuits are needed to realize stable voltage or current supply, and the bias voltage can require higher working voltage when the current mirror current source and the current mirror sink are adopted.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a bidirectional self-bias bipolar current mirror circuit which is suitable for low-voltage operation, so as to solve the technical problem that the mirror image precision of the current mirror circuit needs more bias circuits to stabilize voltage or current supply.
The invention provides a bi-directional self-bias bipolar current mirror circuit adapting to low-voltage operation, which comprises: a current source current mirror circuit and a current sinking current mirror circuit; the current source current mirror circuit and the current sinking current mirror circuit are both used as power supply connecting ends by a public power supply positive end and a public power supply negative end;
the current source current mirror circuit comprises a current source input side PNP tube P1, a first base current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2;
the bias current source I2 supplies collector current of a PNP tube P1 at the current source input side;
the first base current compensation circuit is used for reducing current shunt of the bias current source I2 at the collector electrode of the PNP tube P1 at the current source input side; the first base current compensation circuit comprises a first emitter follower, and the emitter current of the first emitter follower is used for providing bias current for the second base current compensation circuit;
the current sinking current mirror circuit comprises a current sinking input side NPN tube N1, a second base current compensation circuit, a second beta-helper circuit, a current sinking output side NPN tube and a bias current source I1;
the bias current source I1 supplies collector current to an NPN tube N1 at the current sink input side;
the second base current compensation circuit is used for reducing current shunt of the bias current source I1 at the collector electrode of the NPN tube N1 at the current sinking input side; the second base current compensation circuit comprises a second emitter follower, and the emitter current of the second emitter follower is used for providing bias current for the first base current compensation circuit.
Optionally, the first β -helper circuit and the second β -helper circuit each include at least two transistors.
Optionally, the first β -helper circuit and the first base current compensation circuit comprise a common NPN transistor;
the second beta-helper circuit and the second base current compensation circuit comprise a common PNP triode.
Optionally, the working tube of the first emitter follower in the first base current compensation circuit is a PNP tube P2, the first emitter follower is used as a bias current source I3, and bias current is provided for the emitter of the common PNP triode through the collector of the PNP tube P2;
the working tube of the second emitter follower in the second base current compensation circuit is an NPN tube N2, the second emitter follower is used as a bias current source I4, and bias current is provided for the emitter of the common NPN triode through the collector of the NPN tube N2.
Optionally, the emitter of the PNP pipe P2 is connected with the positive end of the public power supply through a resistor R4, and the collector of the PNP pipe P2 is connected with the emitter of the common PNP triode; the collector electrode of the common PNP triode is connected with the negative end of the public power supply; the base electrode of the PNP pipe P2 and the base electrode of the shared NPN triode are connected with the collector electrode of the PNP pipe P1 at the current source input side so as to jointly reduce the current shunt of the bias current source I2 at the collector electrode of the PNP pipe P1 at the current source input side;
the emitter of the NPN tube N2 is connected with the negative end of the public power supply through a resistor R3, and the collector of the NPN tube N2 is connected with the emitter of the common NPN triode; the collector electrode of the common NPN triode is connected with the positive end of the public power supply; the base electrode of the NPN transistor N2 and the base electrode of the common PNP triode are connected with the collector electrode of the current sinking input side NPN transistor N1 so as to jointly reduce current shunt of the bias current source I1 at the collector electrode of the current sinking input side NPN transistor N1.
Optionally, the first β -helper circuit further includes an NPN tube N5 and a PNP tube P4, where an emitter of the NPN tube N5 is connected to an emitter of the PNP tube P4, a base of the PNP tube P1 at an input side of the current source, and a base of the PNP tube at an output side of the current source, a collector of the PNP tube P1 is connected to a positive terminal of the common power source, and a base of the PNP tube P2 is connected to an emitter of the PNP tube P2; the base electrode of the PNP pipe P4 is connected with the emitter electrode of the common NPN triode, and the collector electrode of the PNP pipe P4 is connected with the negative end of the common power supply;
the second beta-helper circuit further comprises a PNP pipe P5 and an NPN pipe N4, wherein the emitter of the PNP pipe P5 is connected with the emitter of the NPN pipe N4, the base of the NPN pipe N1 at the current sinking input side and the base of the NPN pipe at the current sinking output side, the collector of the PNP pipe P is connected with the negative end of the public power supply, and the base of the PNP pipe P is connected with the emitter of the NPN pipe N2; and the base electrode of the NPN tube N4 is connected with the emitter electrode of the common PNP triode, and the collector electrode of the NPN tube N4 is connected with the positive end of the common power supply.
Optionally, the bias current sources I1, I2 comprise a current mirror structure and the current is supplied by the current mirror structure.
Optionally, the output of the current mirror structure of bias current source I2 is a mirrored current source of the current mirror structure of bias current source I1.
Optionally, the current mirror structure of the bias current source I1 comprises a wilson current mirror structure.
Optionally, the number of PNP tubes at the output side of the current source and NPN tubes at the output side of the current sink is multiple.
Compared with the prior art, the invention has the following beneficial effects:
the invention combines the technical innovations of bidirectional self-bias, cascade complementary emitter following, device function multiplexing and the like based on the base compensation technology and the beta-helper technology, and organically fuses the precision improvement and the low-voltage work matching. The first base current compensation circuit is used for reducing current division of the current source I2 at the collector of the PNP pipe P1 at the current source input side, the second base current compensation circuit is used for reducing current division of the current source I1 at the collector of the NPN pipe N1 at the current sink input side, the precision of a current mirror is improved, meanwhile, the emitter current of the first emitter follower in the first base current compensation circuit is used for being supplied as the current source of the second base current compensation circuit, and the emitter current of the second emitter follower in the second base current compensation circuit is used for being supplied as the current source of the first base current compensation circuit, so that bias currents are provided for each other, an additional bias circuit is not relied on, and the requirement of a plurality of external bias matching precision is avoided; the requirement of the working voltage of the circuit is reduced through cascade complementary following of the common PNP triode and the NPN tube N4 and the common NPN triode and the PNP tube P4.
Drawings
FIG. 1 is a circuit diagram of a basic current mirror in the prior art;
FIG. 2 is a prior art beta-helper current mirror structure;
FIG. 3 is a circuit diagram of a prior art two-stage beta-helper current mirror;
FIG. 4 is a circuit diagram of a current mirror with base current compensation in the prior art;
FIG. 5 is a circuit diagram of a prior art current mirror with base current compensation and two stages of beta-helper;
FIG. 6 is a circuit diagram of a current mirror with simultaneous base current compensation and two-stage beta-helper and cascaded complementary shot-to-shot and bi-directional self-bias modifications in accordance with the present invention;
FIG. 7 is a schematic diagram of the structure of FIG. 6 in accordance with the present invention;
FIG. 8 is a circuit diagram of the current mirror of FIG. 6 according to another embodiment of the present invention;
FIG. 9 is a schematic diagram of the structure of FIG. 8 in accordance with the present invention.
Reference numerals illustrate:
100. a current source input side PNP tube P1; 110. a first base current compensation circuit; 120. a first beta-helper circuit; 130. PNP tube at output side of current source; 200. an NPN tube N1 at the input side of the current sink; 210. a second base current compensation circuit; 220. a second beta-helper circuit; 230. an NPN tube at the output side of the current sink; 300. a current mirror; 310. wilson current mirror.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present invention more apparent, the technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Symbol description designed in all formulas of the present invention:
I X the number after which indicates the dc current source and the sequence number of the dc current source. I PXX A current of a certain port of a certain PNP device is represented, where I represents a current symbol, P in the subscript PXX represents a PNP bipolar transistor symbol, the first X represents a device number, and numbers 1,2, 3, etc., and the second X represents a port of the device, which is C (collector), B (base), and E (emitter), respectively. I NXX The current of a certain port of an NPN device is represented, wherein I represents a current symbol, N in a subscript NXX represents an NPN bipolar transistor symbol, the first X represents a device number, arabic numbers are 1,2, 3 and the like, and the second X represents the port of the device, which is respectively C (collector), B (base) and E (emitter). V (V) BEPX The voltage of the BE junction of a PNP device is represented, wherein V represents a current symbol, BE represents the BE junction in the subscript BEPX, P represents a PNP bipolar transistor symbol, X represents a device number, and Arabic numerals are numbered 1,2, 3 and the like. V (V) BENX The BE junction voltage of a PNP device is represented, wherein V represents a current symbol, BE in the subscript BENXX represents a BE junction, and N represents NPN double-polePolar transistor symbols, X, represent device numbers, numbered 1,2, 3, etc. arabic numerals. K (K) XXXX Representing the ratio of the emitter areas of two bipolar transistor devices, wherein the first and third X represent the device type, P or N respectively; the second, four X represent device numbers, being arabic numerals of 1,2, 3, etc. V (V) RX The voltage across a resistive element is represented, where V represents a voltage symbol, R represents a resistive symbol, X represents an element number, and the numbers are Arabic numerals 1,2, 3, etc.
Referring to fig. 1, when the current source I1 and the current source I2 are equal in size, i.e., i1=i2, the current source I1 is mirrored by the NPN transistor N1 to the current sink output side NPN transistor NS (hereinafter abbreviated as NS), and the current source I2 is mirrored by the PNP transistor P1 to the current source output side PNP transistor PS (hereinafter abbreviated as PS). If PS and NS are precisely matched, the mirror image proportion is the same, the collector currents of each device of NS and PS are correspondingly equal, the sum of the collector currents of NS is equal to the sum of the collector currents of PS, and when the devices of the same type are highly matched, the mirror image error mainly comes from two aspects: emitter trace parasitic resistance and base current.
In practice, since each NPN device of NPN tube N1 and NS is placed at a different position of the chip layout, the wiring length from the emitter of each NPN device to the VEE pin is different, and the resistance of the parasitic resistance is also different. Since the collector current of a BJT device is very sensitive to its BE junction voltage, the parasitic resistance of the emitter trace has a great influence on the mirror accuracy. P1 and PS are the same as each PNP device;
let the mirror ratio of N1 to NS set be 1 to K, the common emitter current gain of NPN be beta N When the error caused by parasitic resistance of the emitter wiring is ignored, there are
I 1 ＝I N1C +I N1B +I NSB
I N1C ＝β N I N1B
I NSC ＝β N I NSB
I NSC ＝KI N1C
Wherein I is N1C Collector current of N1, I N1B Base current of N1, I NSC Is the sum of the collector currents of the NS group, I NSB Is the sum of the base currents of the NS group. From the above formulae, can be obtained
Since NS and PS are exactly matched, the mirror ratio of P1 to PS is also 1 to K. Let the common emitter current gain of PNP be beta P Is of the same kind
I 2 ＝I P1C +I P1B +I PSB
I P1C ＝β P I P1B
I PSC ＝β P I PSB
I PSC ＝KI P1C
Wherein I is P1C Collector current of P1, I P1B Is the base current of P1, I PSC Is the sum of the collector currents of the PS group, I PSB Is the sum of the base currents of the NP set.
Since i1=i2, it is possible to obtain
And because the current amplification factor is usually far larger than the mirror image multiple K, the current amplification factor can be obtained according to the Maclalin formula
The relative error based on the reference is (I) PSC ≠0)
The current amplification coefficients of NPN and PNP cannot be completely matched in the process, and the relative error of the current amplification coefficient of NPN relative to the current amplification coefficient of PNP is set as delta, namely
β N ＝(1+δ)β P
Then
It can be seen that if delta is small, the relative error in NS and PS output currents is proportional to delta, and that the larger the mirror multiple K or the smaller the current amplification factor, the larger the ERR.
Referring to fig. 2, in order to increase the mirror image precision, in the conventional scheme, the resistors in R1 and NS are matched according to the mirror image multiple, the resistors in R2 and PS are matched according to the mirror image multiple, these resistors are collectively called as emitter negative feedback resistors, and the organization of the emitter negative feedback resistors can effectively reduce the mirror image error caused by the parasitic resistance of the emitter wirings.
NPN tube N2 and PNP tube P2 are used for reducing the influence of base current on mirror error, the structure is called beta-helper, and I is caused by the current gain of NPN tube N2 and PNP tube P2 1 And I 2 The current shunted through the base is reduced, thereby improving accuracy.
The current relationships under this structure are updated as follows:
I 1 ＝I N1C +I N2B
I N1C ＝β N I N1B
I NSC ＝β N I NSB
I NSB +I N1B ＝(β N +1)I N2B
I NSC ＝KI N1C
I 2 ＝I P1C +I P2B
I P1C ＝β P I P1B
I PSC ＝β P I PSB
I PSB +I P1B ＝(β P +1)I P2B
I PSC ＝KI P1C
can obtain
Then in I PSC The relative error based on the reference is (I) PSC ≠0)
Since the current amplification factor of BJT is much larger than 1, so
It can be seen that the ERR is greatly reduced, but still a perfect match is not achieved, and the relationship that ERR is greater with greater K, smaller BJT current gain, and greater ERR with smaller δ remains, e.g., when δ is small, 1+δ≡1,2+δ≡2, so ERR is proportional to δ.
Since the emitter current of N2 is equal to the sum of the base currents of NPN transistors N1 and NS, and the emitter current of PNP transistor P2 is equal to the sum of the base currents of P1 and PS, the bias currents of NPN transistor N2 and PNP transistor P2 are low, and the current amplification coefficients of NPN transistor N2 and PNP transistor P2 are attenuated by the low currents, thereby introducing additional errors.
Referring to fig. 3, in order to further optimize the scheme of the mirror image precision based on fig. 2, two stages of β -heat are adopted to further reduce the current value of the I1 and I2 shunted through the base, so as to improve the amplification effect of the current gain of the two stages of BJTs, at this time, the base currents of the NPN tube N20 and the PNP tube P20 are already very small, but two problems still face, the first is that the bias currents of the NPN tube N20 and the PNP tube P20 are further reduced, so that the current gain is further attenuated, the current of the base is still difficult to be reduced to an expected value, and the problem of final mirror image matching occurs; secondly, this structure is difficult to operate at very low voltages;
for example, I1 adopts a structure with minimum consumption voltage margin, i.e. the current mirror of the common-emitter configuration without the emitter degeneration resistor, if it works in the amplifying region, the CE junction voltage is required to BE not less than the BE junction voltage V BEI1 . Let the BE junction voltages of N1, N2, N20 BE V BEN1 、V BEN2 、V BEN20 The voltage drop across resistor R1 is VR1, and the minimum supply voltage is V BEI1 +V BEN1 +V BEN2 +V BEN20 +V R1 . Since the BE junction voltage of a BJT is typically greater than 0.7V under normal operation, the minimum operating voltage must BE greater than 2.8V, making it difficult for the chip to operate at lower voltages.
Referring to fig. 4, in order to further solve the problem of current precision between bases on the basis of fig. 3, base currents with opposite directions are adopted to compensate each other, so as to further solve the problem of mirror image matching, I1, I2, I3, I4 are current sources, I1, I2 are matching current signals needing mirror images, and i1=i2. I3, I4 are bias currents of P3, N3;
when the base currents of the NPN tube N2 and the PNP tube P3 are equal, the base currents of the NPN tube N3 and the PNP tube P2 are equal
I 1 ＝I N1C
I NSC ＝KI N1C
I 2 ＝I P1C
I PSC ＝KI P1C
Calculation of derivable I NSC ＝KI N1C ＝KI 1 ＝KI 2 ＝KI P1C ＝I PSC 。
Referring to FIG. 5, the two-stage beta-helper scheme is to use a two-stage cascade emitter follower to further reduce the input base current, with base current compensationBased on the compensation circuit, the two-stage beta-helper scheme can enable the bias currents of NPN and PNP for base current compensation to be more matched, and the bias currents of NPN tube N21 are enabled to be I due to the current gain of the NPN tube N21B Relative to I 5 The output current of NS can be ignored, so that the matching property of the base currents of NPN tube N2 and PNP tube P3 is not affected, and the base currents of NPN tube N2 and PNP tube P3 can be adjusted by adjusting I 3 And I 5 To achieve a match. Due to I 3 And I 5 The NPN tube N2 and the PNP tube P3 can operate at the optimum operating point because there is no very small current. Can be obtained with higher precision
I NSC ＝KI 1
In the same way, can obtain with higher precision
I PSC ＝KI 2
It can be seen that the two-stage beta-helper scheme further solves the problem of image matching in combination with base current compensation.
Referring to fig. 6 and 7, in order to meet the requirement of low voltage operation, while avoiding the need for more bias circuits to achieve a stable voltage or current supply;
the invention provides a bi-directional self-bias bipolar current mirror circuit adapting to low-voltage operation, which comprises: a current source current mirror circuit and a current sinking current mirror circuit; the current source current mirror circuit and the current sinking current mirror circuit are both used as power supply connecting ends by a public power supply positive end and a public power supply negative end;
the current source current mirror circuit comprises a current source input side PNP tube P1 (100), a first base current compensation circuit (110), a first beta-helper circuit (120), a current source output side PNP tube (130) and a bias current source I2;
the bias current source I2 supplies collector current of a current source input side PNP tube P1 (100);
the first base current compensation circuit (110) is used for reducing current shunt of the bias current source I2 at the collector (100) of the PNP tube P1 at the current source input side; wherein the first base current compensation circuit (110) comprises a first emitter follower whose emitter current is used to provide a bias current for a second base current compensation circuit (210);
the current sinking current mirror circuit comprises a current sinking input side NPN tube N1 (200), a second base current compensation circuit (210), a second beta-helper circuit (220), a current sinking output side NPN tube (230) and a bias current source I1;
the bias current source I1 supplies collector current of an NPN tube N1 (200) at the current sinking input side;
the second base current compensation circuit (210) is used for reducing current shunt of the bias current source I1 at the collector of the NPN tube N1 (200) at the current sinking input side; the second base current compensation circuit (210) comprises a second emitter follower, and the emitter current of the second emitter follower is used for providing bias current for the first base current compensation circuit (110).
In one embodiment of the invention, on the basis of adopting a two-stage beta-helper and basic current compensation scheme in the prior art, an extra bias circuit is avoided by further adopting a bidirectional self-bias structure;
the bases of the NPN tube N3 and the PNP tube P2 in the first base current compensation circuit (110) are connected with the collector of the PNP tube P1 (100) at the current source input side for jointly reducing the current split of the current source I2 at the collector of the PNP tube P1 (100) at the current source input side, the bases of the NPN tube N2 and the PNP tube P3 in the second base current compensation circuit (210) are connected with the collector of the NPN tube N1 (200) at the current sink input side for jointly reducing the current split of the current source I1 at the collector of the NPN tube N1 (200) at the current sink input side, and the effect is as described in fig. 4;
the NPN transistor N3 is used as a shared NPN triode in the first beta-helper circuit (120) and the first base current compensation circuit (110);
the PNP pipe P3 is used as a common PNP triode in the second beta-helper circuit (220) and the second base current compensation circuit (210).
The bidirectional self-bias adopts the collector current of the PNP tube P2 of the first emitter follower to provide bias current for the common PNP tube P3; the collector electrode of the second emitter follower NPN tube N2 provides bias current for the common NPN tube N3, the current magnitude of which is provided by the internal feedback circuit, the PNP tube P2 and the PNP tube P3, the NPN tube N2 and the NPN crown N3 provide upper and lower currents for each other, the current source I3, the current source I4, the current source I5 and the current source I6 in fig. 5 are replaced, the circuit structure is simplified, and the implementation is independent of the additional bias circuit.
The NPN tube N3, the PNP tube P4, and the NPN tube N5 form a first β -helper circuit (120), the PNP tube P3, the NPN tube N4, and the PNP tube P5 form a second β -helper circuit (220), the NPN tube N3, the PNP tube P4, the PNP tube P3, and the NPN tube N4 respectively adopt two-stage β -helper technologies, and complementary cascades are formed respectively, so that collector currents of the NPN tube N2 and the NPN tube N3, and collector currents of the PNP tube P2 and the PNP tube P3 are exactly equal (as illustrated in fig. 5). Meanwhile, compared with the common cascade connection of the NPN tube N2 and the NPN tube N21, the PNP tube P2 and the PNP tube P21 in FIG. 5, the NPN tube N3 and the PNP tube P4, the PNP tube P3 and the NPN tube N4 are in complementary cascade connection, the base electrode of the NPN tube N4 is connected with the emitter electrode of the PNP tube P3, VBE of the NPN tube N3 and the PNP tube P4 are mutually offset, voltage margin is not consumed, cascade complementary emission is formed, and the NPN tube N3 and the PNP tube P4 are the same. Let all devices work in the amplifying region, the lowest working voltage is:
V BEN1 +V BEN4 +V BEP2 +V R1 +V R4
if collector currents of the NPN tube N2 and the PNP tube P2 are set to be 50 mu A, resistance values of R3 and R4 are set to be 1k omega, the minimum working voltage is calculated to be 0.7V+0.7V+0.7V+0.05+0.05=2.2V, and the requirement of low-voltage working is met;
further, the NPN tube N2, the NPN tube N4, the PNP tube P3, and the PNP tube P5 form a structure of the class ab output stage (the PNP tube P5 objectively forms the class ab output stage structure with the NPN tube N4, but does not play a role of the class ab output stage), the PNP tube P5 is mainly used to provide the bias current for the NPN tube N4, the PNP tube P5 can ensure that when the base current of the PNP tube P5 may be smaller, the NPN tube N4 is prevented from not being at an optimal operating point, and meanwhile, has a negative feedback function, if the base of the NPN tube N2 is higher than a point, and the emitter of the PNP tube P3 is unchanged, so that the current of the NPN tube N2 increases, and the current of the PNP tube P3 decreases, but the whole is still stable, so that the currents of the NPN tube N2 and the PNP tube P3 cannot be guaranteed to be equal; by arranging the PNP tube P5, the base electrode of the PNP tube P5 is raised due to the increase of the current of the NPN tube N2, so that the base electrode of the NPN tube N1 is raised, the base electrode of the NPN tube N2 is pulled down, negative feedback is formed, and the equal currents of N2 and P3 are ensured.
The NPN tube N3, the NPN tube N5, the PNP tube P2, and the PNP tube P4 form a structure of a class a and class b output stage (the NPN tube N5 and the PNP tube P4 have the effects as described above and do not play a role of the class a and class b output stage), and the structure of the class a and class b output stage balances the BE junction voltages of the related devices with each other, that is, satisfies the relationships vben2+vbep3=vben4+vbep5 and vben3+vbep2=vben5+vbep4. And then the currents of the NPN pipe N2, the NPN pipe N4, the PNP pipe P3 and the PNP pipe P5 can be matched, and the currents of the NPN pipe N3, the NPN pipe N5, the PNP pipe P2 and the PNP pipe P4 can be matched.
Setting the resistance ratio of R1 and R3 as K N1N2 Then
I N2C ＝K N1N2 I N1C
Setting the resistance ratio of R2 and R4 to be K P1P2 Then
I P2C ＝K P1P2 I P1C
It can be seen that the collector currents of NPN tube N2, NPN tube N3, PNP tube P2 match.
Setting device parameters to enable K N4N2 ＝K P5P3 ，K N5N3 ＝K P4P2 Then
I N4C ＝I P5C ＝I N5C ＝I P4C ＝K N4N2 I N2C ＝K P1P2 I P1C
The bases of NS and PS are driven by the emitter follower (respectively by the complementary output stage of NPN tube N4 and PNP tube P5, the complementary output stage of PNP tube P4 and NPN tube N5), so the starting time is faster and the problem of driving capability is avoided;
the collector voltage of the NPN tube N1 is only VBEN2+VR3, so I1 can be preferably realized by adopting a cam structure, and the applicability of the circuit under low voltage is not affected. Similarly, I2 may be preferably implemented using a cascode structure, without affecting the applicability of the circuit at low voltages. The working voltage of the front-stage current source can be as low as VCC-0.75V, and the working voltage of the front-stage current sink can be as high as VEE+0.75V.
With reference to figures 8 and 9 of the drawings,the present invention provides another embodiment, which uses a current source IREF, and uses a Wilson current mirror (310) with higher output resistance to output accurate mirror current; NPN tube N6, NPN tube N7, NPN tube N8, resistor R5, resistor R6 and resistor R7 form a current mirror (300), because the circuit only comprises one reference current source IREF, and the current source outputs through NPN tube N7 and NPN tube N8 in a one-to-one mirror image manner, although IREF and I are N7C 、I N8C There are differences, but I N7C 、I N8C Are closely matched with each other; the PNP transistors P6, P7, and P8 form a wilson current mirror (310), the collector current of the PNP transistor P8 corresponds to the current source I1 in fig. 6, and the collector current of the NPN transistor N8 corresponds to the current source I2 in fig. 6, and since the collector current of the NPN transistor N8 is strictly matched with the current of the collector of the PNP transistor P8, the current of the PS collector is also strictly matched with the current of the NS collector, and the other structures are the same as those in fig. 6, which results in the same technical effects and will not be repeated.
The number of the PNP tubes (130) at the output side of the current source and the NPN tubes (230) at the output side of the current sink can be set to be multiple according to the load, and mirror image errors caused by parasitic resistance of an emitter wiring are solved by arranging the emitter negative feedback resistor as shown in fig. 2.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (7)
1. A bi-directional self-biasing bipolar current mirror circuit adapted for low voltage operation, comprising: a current source current mirror circuit and a current sinking current mirror circuit; the current source current mirror circuit and the current sinking current mirror circuit are both used as power supply connecting ends by a public power supply positive end and a public power supply negative end;
the current source current mirror circuit comprises a current source input side PNP tube P1, a first base current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2;
the bias current source I2 supplies collector current of a PNP tube P1 at the current source input side;
the first base current compensation circuit is used for reducing current shunt of the bias current source I2 at the collector electrode of the PNP tube P1 at the current source input side; the first base current compensation circuit comprises a first emitter follower, and the emitter current of the first emitter follower is used for providing bias current for the second base current compensation circuit;
the current sinking current mirror circuit comprises a current sinking input side NPN tube N1, a second base current compensation circuit, a second beta-helper circuit, a current sinking output side NPN tube and a bias current source I1;
the bias current source I1 supplies collector current to an NPN tube N1 at the current sink input side;
the second base current compensation circuit is used for reducing current shunt of the bias current source I1 at the collector electrode of the NPN tube N1 at the current sinking input side; the second base current compensation circuit comprises a second emitter follower, and the emitter current of the second emitter follower is used for providing bias current for the first base current compensation circuit;
the first beta-helper circuit and the second beta-helper circuit each comprise at least two triodes;
the first beta-helper circuit and the first base current compensation circuit comprise a shared NPN triode; the second beta-helper circuit and the second base current compensation circuit comprise a common PNP triode; the working tube of the first emitter follower in the first base current compensation circuit is a PNP tube P2, the first emitter follower is used as a bias current source I3, and bias current is provided for the emitter of the common PNP triode through the collector of the PNP tube P2;
the working tube of the second emitter follower in the second base current compensation circuit is an NPN tube N2, the second emitter follower is used as a bias current source I4, and bias current is provided for the emitter of the common NPN triode through the collector of the NPN tube N2.
2. The bi-directional self-biasing bipolar current mirror circuit for low voltage operation according to claim 1 wherein,
the emitter of the PNP pipe P2 is connected with the positive end of the public power supply through a resistor R4, and the collector of the PNP pipe P2 is connected with the emitter of the common PNP triode; the collector electrode of the common PNP triode is connected with the negative end of the public power supply; the base electrode of the PNP pipe P2 and the base electrode of the shared NPN triode are connected with the collector electrode of the PNP pipe P1 at the current source input side so as to jointly reduce the current shunt of the bias current source I2 at the collector electrode of the PNP pipe P1 at the current source input side;
the emitter of the NPN tube N2 is connected with the negative end of the public power supply through a resistor R3, and the collector of the NPN tube N2 is connected with the emitter of the common NPN triode; the collector electrode of the common NPN triode is connected with the positive end of the public power supply; the base electrode of the NPN transistor N2 and the base electrode of the common PNP triode are connected with the collector electrode of the current sinking input side NPN transistor N1 so as to jointly reduce current shunt of the bias current source I1 at the collector electrode of the current sinking input side NPN transistor N1.
3. A bi-directional self-biasing bipolar current mirror circuit adapted for low voltage operation according to claim 2 wherein,
the first beta-helper circuit further comprises an NPN tube N5 and a PNP tube P4, wherein the emitter of the NPN tube N5 is connected with the emitter of the PNP tube P4, the base of the PNP tube P1 at the input side of the current source and the base of the PNP tube at the output side of the current source, the collector of the NPN tube N5 is connected with the positive end of the common power supply, and the base of the NPN tube N5 is connected with the emitter of the PNP tube P2; the base electrode of the PNP pipe P4 is connected with the emitter electrode of the common NPN triode, and the collector electrode of the PNP pipe P4 is connected with the negative end of the common power supply;
the second beta-helper circuit further comprises a PNP pipe P5 and an NPN pipe N4, wherein the emitter of the PNP pipe P5 is connected with the emitter of the NPN pipe N4, the base of the NPN pipe N1 at the current sinking input side and the base of the NPN pipe at the current sinking output side, the collector of the PNP pipe P is connected with the negative end of the public power supply, and the base of the PNP pipe P is connected with the emitter of the NPN pipe N2; and the base electrode of the NPN tube N4 is connected with the emitter electrode of the common PNP triode, and the collector electrode of the NPN tube N4 is connected with the positive end of the common power supply.
4. A bi-directional self-biasing bipolar current mirror circuit adapted for low voltage operation as in claim 3 wherein,
the bias current sources I1 and I2 comprise current mirror structures, and current is supplied by the current mirror structures.
5. The bi-directional self-biasing bipolar current mirror circuit for low voltage operation according to claim 4 wherein,
the output of the current mirror structure of bias current source I2 acts as a mirror current source for the current mirror structure of bias current source I1.
6. A bi-directional self-biasing bipolar current mirror circuit adapted for low voltage operation according to claim 4 or 5 wherein,
the current mirror structure of the bias current source I1 comprises a wilson current mirror structure.
7. A bi-directional self-biasing bipolar current mirror circuit adapted for low voltage operation according to any of claims 1-5 wherein,
the number of PNP tubes at the output side of the current source and NPN tubes at the output side of the current sink is a plurality of.
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