TWI546644B - Fixed voltage generating circuit - Google Patents

Fixed voltage generating circuit Download PDF

Info

Publication number
TWI546644B
TWI546644B TW103107507A TW103107507A TWI546644B TW I546644 B TWI546644 B TW I546644B TW 103107507 A TW103107507 A TW 103107507A TW 103107507 A TW103107507 A TW 103107507A TW I546644 B TWI546644 B TW I546644B
Authority
TW
Taiwan
Prior art keywords
resistor
transistor
coupled
voltage
resistance
Prior art date
Application number
TW103107507A
Other languages
Chinese (zh)
Other versions
TW201435541A (en
Inventor
陳智聖
趙傳珍
Original Assignee
立積電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 立積電子股份有限公司 filed Critical 立積電子股份有限公司
Priority to TW103107507A priority Critical patent/TWI546644B/en
Publication of TW201435541A publication Critical patent/TW201435541A/en
Application granted granted Critical
Publication of TWI546644B publication Critical patent/TWI546644B/en

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45244—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45392—Indexing scheme relating to differential amplifiers the AAC comprising resistors in the source circuit of the AAC before the common source coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45508—Indexing scheme relating to differential amplifiers the CSC comprising a voltage generating circuit as bias circuit for the CSC

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Description

固定電壓產生電路 Fixed voltage generating circuit

本發明係有關於一種固定電壓產生電路，尤指一種適用於砷化鎵(GaAs)製程的固定電壓產生電路。 The present invention relates to a fixed voltage generating circuit, and more particularly to a fixed voltage generating circuit suitable for a gallium arsenide (GaAs) process.

砷化鎵製程可製作出具有良好性能及高效率的RF功率放大器。其特點包括在高頻工作時不易產生信號失真、雜訊值低、功率耗損小、增益值大及元件面積小等，因此可以達到元件小、高效率、低耗電等效果，適合應用在手機及各項通訊設備產品。 The gallium arsenide process produces RF power amplifiers with good performance and high efficiency. The utility model is characterized in that it is not easy to generate signal distortion, low noise value, small power loss, large gain value and small component area in high frequency operation, so that the components can be small, high efficiency, low power consumption, etc., and are suitable for application in mobile phones. And various communication equipment products.

為使砷化鎵功率放大器在大範圍輸入電壓變動的情形下仍可正常動作，便需要提供穩定電壓給功率放大器以確保其工作正常。 In order for the GaAs power amplifier to operate normally with a wide range of input voltage variations, it is necessary to provide a regulated voltage to the power amplifier to ensure proper operation.

通常固定電壓產生電路使用CMOS製程，其中會使用到PMOS。然而PMOS並不適合用在砷化鎵製程，因此無法整合此固定電壓產生電路於同一砷化鎵製程，而需另外提供一個由CMOS製程製作的固定電壓產生電路以提供砷化鎵功率放大器穩定電壓。如此會增加製程所需要的面積及降低集成度(integration)。 Usually the fixed voltage generating circuit uses a CMOS process in which a PMOS is used. However, PMOS is not suitable for use in a gallium arsenide process, so the fixed voltage generating circuit cannot be integrated in the same gallium arsenide process, and a fixed voltage generating circuit fabricated by a CMOS process is additionally provided to provide a stable voltage of the gallium arsenide power amplifier. This will increase the area required for the process and reduce the integration.

本發明之一實施例提供一種固定電壓產生電路，包含第一電阻、第一電晶體、第二電晶體、第三電晶體、第四電晶體、第二電阻及第三電阻。第一電阻包含第一端及第二端，該第一電阻的第二端耦接於電壓源。第一電 晶體包含第一端、第二端，以及控制端，第一電晶體的控制端耦接於第一電阻的第一端，第一電晶體的第一端耦接於一接地端，第一電晶體的第二端耦接於第一電晶體的控制端。第二電晶體包含第一端、第二端，以及控制端，第二電晶體的控制端耦接於第一電晶體的控制端，第二電晶體的第一端耦接於接地端。第三電晶體包含第一端、第二端，以及控制端，第三電晶體的控制端用以接收第一差動電壓，第三電晶體的第一端耦接於第二電晶體的第二端。第四電晶體包含第一端、第二端，以及控制端，第四電晶體的控制端用以接收第二差動電壓，第四電晶體的第一端耦接於第二電晶體的第二端。第二電阻包含第一端以及第二端，第二電阻的第一端耦接於第三電晶體的第二端，第二電阻的第二端耦接於電壓源。第三電阻包含第一端以及第二端，第三電阻的第一端耦接於第四電晶體的第二端，第三電阻的第二端耦接於電壓源。其中第二電阻的阻值及第三電阻的阻值與第一電阻的阻值有關。 An embodiment of the present invention provides a fixed voltage generating circuit including a first resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a second resistor, and a third resistor. The first resistor includes a first end and a second end, and the second end of the first resistor is coupled to the voltage source. First electricity The crystal includes a first end, a second end, and a control end, the control end of the first transistor is coupled to the first end of the first resistor, and the first end of the first transistor is coupled to a ground end, the first The second end of the crystal is coupled to the control end of the first transistor. The second transistor includes a first end, a second end, and a control end. The control end of the second transistor is coupled to the control end of the first transistor, and the first end of the second transistor is coupled to the ground. The third transistor includes a first end, a second end, and a control end, the control end of the third transistor is configured to receive the first differential voltage, and the first end of the third transistor is coupled to the second transistor Two ends. The fourth transistor includes a first end, a second end, and a control end, the control end of the fourth transistor is configured to receive the second differential voltage, and the first end of the fourth transistor is coupled to the second transistor Two ends. The second resistor includes a first end and a second end. The first end of the second resistor is coupled to the second end of the third transistor, and the second end of the second resistor is coupled to the voltage source. The third resistor includes a first end and a second end. The first end of the third resistor is coupled to the second end of the fourth transistor, and the second end of the third resistor is coupled to the voltage source. The resistance of the second resistor and the resistance of the third resistor are related to the resistance of the first resistor.

100、200、300、400、500、800、900、1000‧‧‧固定電壓產生電路 100, 200, 300, 400, 500, 800, 900, 1000‧‧‧ fixed voltage generating circuits

102‧‧‧第一電阻 102‧‧‧First resistance

104‧‧‧第二電阻 104‧‧‧second resistance

106‧‧‧第三電阻 106‧‧‧ Third resistor

108‧‧‧第一電晶體 108‧‧‧First transistor

110‧‧‧第二電晶體 110‧‧‧Second transistor

112‧‧‧第三電晶體 112‧‧‧ Third transistor

114‧‧‧第四電晶體 114‧‧‧fourth transistor

202‧‧‧第四電阻 202‧‧‧fourth resistor

302‧‧‧第五電阻 302‧‧‧ fifth resistor

304‧‧‧第六電阻 304‧‧‧ sixth resistance

520‧‧‧二極體 520‧‧‧ diode

60‧‧‧場效電晶體 60‧‧‧ field effect transistor

70‧‧‧雙極性接面電晶體 70‧‧‧Bipolar junction transistor

VDD‧‧‧電壓源 VDD‧‧‧voltage source

VD‧‧‧輸出電壓 VD‧‧‧ output voltage

I‧‧‧偏壓電流 I‧‧‧Butable current

第1圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 1 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第2圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 2 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第3圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 3 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第4圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 4 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第5圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 5 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第6圖為一利用場效電晶體實現二極體的電路圖。 Figure 6 is a circuit diagram of a diode using a field effect transistor.

第7圖為一利用雙極性接面電晶體實現二極體的電路圖。 Figure 7 is a circuit diagram of a diode using a bipolar junction transistor.

第8圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 8 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第9圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 9 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

第10圖為本發明一實施例之固定電壓產生電路的電路圖。 Fig. 10 is a circuit diagram of a fixed voltage generating circuit according to an embodiment of the present invention.

請參考第1圖，第1圖為本發明的第一實施例說明一種固定電壓 產生電路100的示意圖。固定電壓產生電路100包含第一電阻102、第二電阻104、第三電阻106、第一電晶體108、第二電晶體110、第三電晶體112及第四電晶體114。第一電阻102包含第一端及第二端，其中第一電阻102的第二端耦接於電壓源VDD。第一電晶體108包含控制端、第一端及第二端，其中第一電晶體108的控制端耦接於第一電阻102的第一端，第一電晶體108的第一端耦接於接地端，及第一電晶體108的第二端耦接於第一電晶體108的控制端。第二電晶體110包含控制端、第一端及第二端，其中第二電晶體110的控制端耦接於第一電晶體108的控制端，及第二電晶體110第一端耦接於接地端。第三電晶體112包含控制端、第一端及第二端，其中第三電晶體112的控制端用以接收第一差動電壓，及第三電晶體112的第一端耦接於第二電晶體110的第二端。第四電晶體114包含控制端、第一端及第二端，其中第四電晶體114的控制端用以接收第二差動電壓，及第四電晶體114的第一端耦接於第二電晶體110的第二端。第二電阻104包含第一端及第二端，其中第二電阻104的第一端耦接於第三電晶體112的第二端，及第二電阻104的第二端耦接於電壓源VDD。第三電阻106包含第一端及第二端，其中第三電阻106的第一端耦接於第四電晶體114的第二端，及第三電阻106的第二端耦接於電壓源VDD。在此實施例中，第一電阻102、第二電阻104與第三電阻106的阻值比例係為1：2：2，且第二電阻104及第三電阻106的阻值實質上相等。在此實施例中，第一電晶體108及第二電晶體110的尺寸比例為1：1。 Please refer to FIG. 1. FIG. 1 illustrates a fixed voltage according to a first embodiment of the present invention. A schematic diagram of the circuit 100 is produced. The fixed voltage generating circuit 100 includes a first resistor 102, a second resistor 104, a third resistor 106, a first transistor 108, a second transistor 110, a third transistor 112, and a fourth transistor 114. The first resistor 102 includes a first end and a second end, wherein the second end of the first resistor 102 is coupled to the voltage source VDD. The first transistor 108 includes a control end, a first end, and a second end. The control end of the first transistor 108 is coupled to the first end of the first resistor 102. The first end of the first transistor 108 is coupled to the first end. The ground end and the second end of the first transistor 108 are coupled to the control end of the first transistor 108. The second transistor 110 includes a control end, a first end, and a second end. The control end of the second transistor 110 is coupled to the control end of the first transistor 108, and the first end of the second transistor 110 is coupled to the second end. Ground terminal. The third transistor 112 includes a control end, a first end and a second end, wherein the control end of the third transistor 112 is configured to receive the first differential voltage, and the first end of the third transistor 112 is coupled to the second end The second end of the transistor 110. The fourth transistor 114 includes a control end, a first end and a second end, wherein the control end of the fourth transistor 114 is configured to receive the second differential voltage, and the first end of the fourth transistor 114 is coupled to the second end The second end of the transistor 110. The second resistor 104 includes a first end and a second end. The first end of the second resistor 104 is coupled to the second end of the third transistor 112, and the second end of the second resistor 104 is coupled to the voltage source VDD. . The third resistor 106 includes a first end and a second end. The first end of the third resistor 106 is coupled to the second end of the fourth transistor 114, and the second end of the third resistor 106 is coupled to the voltage source VDD. . In this embodiment, the resistance ratio of the first resistor 102, the second resistor 104, and the third resistor 106 is 1:2:2, and the resistances of the second resistor 104 and the third resistor 106 are substantially equal. In this embodiment, the first transistor 108 and the second transistor 110 have a size ratio of 1:1.

在第1圖的電路中，第一電阻102根據電壓源VDD於第一電晶 體108的控制端產生一偏壓。第一電晶體108及第二電晶體110組成電流鏡，即鏡像電流源(Mirror Current Source)。其中，第二電晶體110的控制端受偏於第一電晶體108的控制端之偏壓，因此第二電晶體110產生映射流經第一 電晶體108電流的偏壓電流I。偏壓電流I可透過計算流經第一電晶體108的電流而得到，如式(1)所示。 In the circuit of FIG. 1, the first resistor 102 is in the first transistor according to the voltage source VDD. The control terminal of body 108 produces a bias voltage. The first transistor 108 and the second transistor 110 constitute a current mirror, that is, a Mirror Current Source. Wherein, the control end of the second transistor 110 is biased by the control terminal of the first transistor 108, so the second transistor 110 generates a mapping flow through the first The bias current I of the transistor 108 current. The bias current I can be obtained by calculating the current flowing through the first transistor 108, as shown in the formula (1).

其中Vt1是第一電晶體108的導通電壓，而R1為第一電阻102的 阻值。偏壓電流I流過由第三電晶體112、第四電晶體114、第二電阻104及第三電阻106組成的差動對，由於差動對左右兩側的組件對稱，因此流過差動對的右側，包含第四電晶體114及第三電阻106的電流為偏壓電流I的一半。差動對亦耦接於電壓源VDD，因此於第四電晶體114的第二端會產生輸出電壓VD，如式(2)。 Where V t1 is the turn-on voltage of the first transistor 108 and R1 is the resistance of the first resistor 102. The bias current I flows through the differential pair composed of the third transistor 112, the fourth transistor 114, the second resistor 104, and the third resistor 106. Since the differential is symmetric to the components on the left and right sides, the differential flows. On the right side of the pair, the current including the fourth transistor 114 and the third resistor 106 is half of the bias current I. The differential pair is also coupled to the voltage source VDD, so an output voltage VD is generated at the second end of the fourth transistor 114, as in equation (2).

其中R3為第三電阻106的阻值，Re1為第二電阻104及第三電阻 106的等效阻值。由於差動對左右兩側為並聯結構，第二電阻104及第三電阻106的等效阻值為第二電阻104及第三電阻106並聯後的阻值，且第二電 阻104及第三電阻106的阻值實質上相等，所以。在此實施例中， 第一電阻102、第二電阻104與第三電阻106的阻值比例係為1：2：2，所以Re1=R1。由式(2)，輸出電壓VD的電壓值為一固定值。 Where R3 is the resistance of the third resistor 106, and Re1 is the equivalent resistance of the second resistor 104 and the third resistor 106. Since the difference between the left and right sides is a parallel structure, the equivalent resistance of the second resistor 104 and the third resistor 106 is the resistance of the second resistor 104 and the third resistor 106 in parallel, and the second resistor 104 and the third resistor The resistance of 106 is substantially equal, so . In this embodiment, the resistance ratio of the first resistor 102, the second resistor 104, and the third resistor 106 is 1:2:2, so Re1=R1. From equation (2), the voltage value of the output voltage VD is a fixed value.

另外，由式(1)，當電壓源VDD變化時，流過差動對的偏壓電流I亦隨之改變。若電壓源VDD的電壓變化為dVDD，偏壓電流I的變化為dI，則dI如式(3)，而輸出電壓VD的變化dVD如式(4)。於式(4)中，若R1=Re1，亦即第一電阻102的阻值實質上等於第二電阻104及第三電阻106的等效阻 值Re1，則輸出電壓VD的變化dVD為零。輸出電壓VD為固定電壓而不隨電壓源VDD的電壓變化dVDD而改變，以使該差動對得以輸出穩定的輸出電壓。 Further, from the equation (1), when the voltage source VDD changes, the bias current I flowing through the differential pair also changes. If the voltage of the voltage source VDD changes to dVDD, the change of the bias current I is dI, then dI is as in equation (3), and the change in output voltage VD is dVD as in equation (4). In the formula (4), if R1=Re1, that is, the resistance of the first resistor 102 is substantially equal to the equivalent resistance of the second resistor 104 and the third resistor 106. With the value Re1, the change dVD of the output voltage VD is zero. The output voltage VD is a fixed voltage and does not change with the voltage change dVDD of the voltage source VDD, so that the differential pair can output a stable output voltage.

由上述可知，固定電壓產生電路100之輸出電壓VD的電壓值會 被維持在固定值，而且不會隨著電壓源VDD的變動而產生變化，因此可以在大範圍輸入電壓變動的情形下正常地工作。通常在CMOS產生固定電壓的電路製程中，第二電阻104及第三電阻106是由PMOS所取代，但由於CMOS製程中所使用到的PMOS並不適合用在砷化鎵製程中，因此要將CMOS製程中的電路結構予以套用在砷化鎵製程中並不符合實際應用，但由於以上之第一實施例中藉由調整多個電阻阻值的比例以及電阻連接於電壓源VDD的方式，可在砷化鎵製程中產生固定電壓，而不須另使用CMOS製程以提供固定電壓，如此可減少製程所需要的面積及增加集成度。 As can be seen from the above, the voltage value of the output voltage VD of the fixed voltage generating circuit 100 will It is maintained at a fixed value and does not change with fluctuations in the voltage source VDD. Therefore, it can operate normally in the case of a wide range of input voltage fluctuations. Generally, in the circuit process in which CMOS generates a fixed voltage, the second resistor 104 and the third resistor 106 are replaced by PMOS, but since the PMOS used in the CMOS process is not suitable for use in a gallium arsenide process, the CMOS is required. The circuit structure in the process is not suitable for practical application in the gallium arsenide process, but since the ratio of the resistance values of the plurality of resistors and the manner in which the resistors are connected to the voltage source VDD are used in the above first embodiment, A fixed voltage is generated in the gallium arsenide process without the need for a separate CMOS process to provide a fixed voltage, which reduces the area required for the process and increases integration.

第1圖電路中，第一電晶體108及第二電晶體110的尺寸比例可 從1：1改為1：N，N為正整數，此時只要將第二電阻104及第三電阻106的等 效阻值設計為，則仍可使得輸出電壓VD的電壓值維持在固定值， 且不會隨著電壓源VDD的變動而產生變化。此外，Re1電阻阻值降低，可進一步減少製程所需要的面積。當N=2時，第一電阻102、第二電阻104及第三電阻106的阻值相等，此實施例中，所有電阻設計為同一尺寸，可減少製程變異造成的誤差。 In the circuit of FIG. 1, the size ratio of the first transistor 108 and the second transistor 110 can be changed from 1:1 to 1:N, and N is a positive integer. In this case, the second resistor 104 and the third resistor 106 are The equivalent resistance is designed as Then, the voltage value of the output voltage VD can be maintained at a fixed value and does not change with the fluctuation of the voltage source VDD. In addition, the resistance of the Re1 resistor is reduced, which further reduces the area required for the process. When N=2, the resistances of the first resistor 102, the second resistor 104 and the third resistor 106 are equal. In this embodiment, all the resistors are designed to have the same size, which can reduce the error caused by the process variation.

第1圖的電路中，第一電晶體108及第二電晶體110的尺寸比例 也可從1：1改為N：1，N為正整數，當第二電阻104及第三電阻106並聯後的等效阻值設計為Re1=N＊R1，仍可使得輸出電壓VD的電壓值維持在固定值。而Re1電阻阻值增加，亦可降低電流消耗。 In the circuit of FIG. 1, the size ratio of the first transistor 108 and the second transistor 110 can also be changed from 1:1 to N:1, and N is a positive integer. When the second resistor 104 and the third resistor 106 are connected in parallel, the equivalent resistance is designed to Re1 = N * R 1, so that the voltage value of the output voltage still VD is maintained at a fixed value. The resistance of the Re1 resistor increases, which also reduces current consumption.

請參照第2圖，第2圖為本發明的第二實施例說明固定電壓產生 電路200的示意圖。固定電壓產生電路200包含固定電壓產生電路100的元件以及另一第四電阻202。其中第二電阻104及第三電阻106不直接耦接至電壓源VDD而是經由第四電阻202耦接至電壓源VDD。第四電阻202包含第一端及第二端，其中第四電阻202的第一端耦接於第二電阻104的第二端及第三電阻106的第二端，及第四電阻202的第二端耦接於電壓源VDD。第二電阻104、第三電阻106及第四電阻202的等效阻值Re2實質上等於第一電阻102的阻值，且第二電阻104及第三電阻106的阻值實質上相等。 Please refer to FIG. 2, which is a second embodiment of the present invention illustrating fixed voltage generation. A schematic diagram of circuit 200. The fixed voltage generating circuit 200 includes an element of the fixed voltage generating circuit 100 and another fourth resistor 202. The second resistor 104 and the third resistor 106 are not directly coupled to the voltage source VDD but are coupled to the voltage source VDD via the fourth resistor 202. The fourth resistor 202 includes a first end and a second end, wherein the first end of the fourth resistor 202 is coupled to the second end of the second resistor 104 and the second end of the third resistor 106, and the fourth resistor 202 The two ends are coupled to a voltage source VDD. The equivalent resistance Re2 of the second resistor 104, the third resistor 106, and the fourth resistor 202 is substantially equal to the resistance of the first resistor 102, and the resistances of the second resistor 104 and the third resistor 106 are substantially equal.

第2圖的偏壓電流原理及動作同式(1)及式(3)所述。其中偏壓電流 I流過第四電阻202之後，會分流至由第三電晶體112、第四電晶體114、第二電阻104及第三電阻106組成的差動對。由於差動對左右兩側的組件對稱，因此流過差動對的右側，包含第四電晶體114及第三電阻106的電流為偏壓電流I的一半，因此於第四電晶體114的第二端產生的輸出電壓VD係如式(5)所示。 The principle and operation of the bias current in Fig. 2 are as described in equations (1) and (3). Bias current After flowing through the fourth resistor 202, the current is shunted to a differential pair composed of the third transistor 112, the fourth transistor 114, the second resistor 104, and the third resistor 106. Since the differential is symmetrical to the components on the left and right sides, the current flowing through the right side of the differential pair, the current including the fourth transistor 114 and the third resistor 106 is half of the bias current I, and thus the fourth transistor 114 The output voltage VD generated at the two terminals is as shown in equation (5).

其中，R3為第三電阻106的阻值，R4為第四電阻202阻值，Re2 為第二電阻104、第三電阻106及第四電阻202的等效阻值。由於差動對左右兩側為並聯結構，第二電阻104及第三電阻106的等效阻值為第二電阻104及第三電阻106並聯後的阻值，而第二電阻104、第三電阻106及第四電阻202的等效阻值為第二電阻104及第三電阻106的等效阻值加上第四電阻202的阻值，且由於第二電阻104及第三電阻106的阻值實質上相等，因此 。在此實施例中，Re2=R1。由式(5)，輸出電壓VD之電壓值為 Vt1。 Wherein R3 is the resistance of the third resistor 106, R4 is the resistance of the fourth resistor 202, and Re2 is the equivalent resistance of the second resistor 104, the third resistor 106, and the fourth resistor 202. Since the difference between the left and right sides is a parallel structure, the equivalent resistance of the second resistor 104 and the third resistor 106 is the resistance of the second resistor 104 and the third resistor 106 in parallel, and the second resistor 104 and the third resistor The equivalent resistance of the 106 and the fourth resistor 202 is the equivalent resistance of the second resistor 104 and the third resistor 106 plus the resistance of the fourth resistor 202, and the resistance values of the second resistor 104 and the third resistor 106 are Essentially equal, so . In this embodiment, Re2 = R1. From equation (5), the voltage value of the output voltage VD is V t1 .

當電壓源VDD的電壓變化(dVDD)時，偏壓電流I亦隨之改變 (dI)，dI如式(3)，而輸出電壓VD的變化dVD如式(6)。於式(6)中，若R1=Re2，亦即第一電阻102的阻值實質上等於第二電阻104、第三電阻106及第四電阻202的等效阻值Re2，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD為穩定的固定電壓且不隨著電壓源VDD的電壓變化dVDD而改變。 When the voltage of the voltage source VDD changes (dVDD), the bias current I also changes. (dI), dI is as in equation (3), and the variation dVD of the output voltage VD is as shown in equation (6). In the formula (6), if R1=Re2, that is, the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re2 of the second resistor 104, the third resistor 106, and the fourth resistor 202, the output voltage VD The change dVD is zero. That is, the output voltage VD is a stable fixed voltage and does not change with the voltage change dVDD of the voltage source VDD.

由上述可知，固定電壓產生電路200之輸出電壓VD的電壓值維 持在固定值，而且不會隨著電壓源VDD的變動而產生變化，因此可在不使用CMOS製程情況下，於砷化鎵製程中產生固定電壓並在大範圍輸入電壓變動的情形下正常地工作。另外，第2圖的第二電阻104、第三電阻106及第四電阻202的電阻相加總值會小於第1圖的第二電阻104及第三電阻106的電阻相加總值，如此可有效減少電阻的佈局面積，進一步增加集成度。 As can be seen from the above, the voltage value dimension of the output voltage VD of the fixed voltage generating circuit 200 Holds a fixed value and does not change with the variation of the voltage source VDD, so it can generate a fixed voltage in the gallium arsenide process without using a CMOS process and normally in the case of a wide range of input voltage fluctuations. jobs. In addition, the total value of the resistance addition of the second resistor 104, the third resistor 106, and the fourth resistor 202 in FIG. 2 is smaller than the total value of the resistances of the second resistor 104 and the third resistor 106 in FIG. Effectively reduce the layout area of the resistor, further increasing the integration.

請參照第3圖，第3圖為本發明的第三實施例說明固定電壓產生 電路300的示意圖。固定電壓產生電路300包含固定電壓產生電路200的元件以及第五電阻302和第六電阻304，其中第五電阻302係耦接於第三電晶體112的第一端與第二電晶體110的第二端之間，而第六電阻304則係耦接於第四電晶體114的第一端與第二電晶體110的第二端之間。第五電阻302及第六電阻304是射極退化電阻，為了產生負反饋作用，增加差動對的輸入電阻及增大差動電壓輸入電壓範圍。 Please refer to FIG. 3, which shows a fixed voltage generation according to a third embodiment of the present invention. A schematic diagram of circuit 300. The fixed voltage generating circuit 300 includes the components of the fixed voltage generating circuit 200 and the fifth resistor 302 and the sixth resistor 304. The fifth resistor 302 is coupled to the first end of the third transistor 112 and the second transistor 110. The sixth resistor 304 is coupled between the first end of the fourth transistor 114 and the second end of the second transistor 110. The fifth resistor 302 and the sixth resistor 304 are emitter degeneration resistors, and in order to generate a negative feedback action, the input resistance of the differential pair is increased and the differential voltage input voltage range is increased.

第3圖中，偏壓電流I流過第四電阻202、差動對、第五電阻302 及第六電阻304，當第二電阻104阻值等於第三電阻106阻值，第五電阻302阻值等於第六電阻304阻值時，流過差動對右側的電流仍為偏壓電流I的一半，此時第3圖的原理及動作同式(1)、式(3)、式(5)、式(6)所述。因此只要R1=Re2，亦即若第一電阻102的阻值實質上等於第二電阻104、第三電阻106及第四電阻202的等效阻值Re2，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD的電壓值為一穩定的固定值，不隨著電壓源VDD的電壓變化dVDD而改變。 In FIG. 3, the bias current I flows through the fourth resistor 202, the differential pair, and the fifth resistor 302. And the sixth resistor 304, when the resistance of the second resistor 104 is equal to the resistance of the third resistor 106, and the resistance of the fifth resistor 302 is equal to the resistance of the sixth resistor 304, the current flowing through the differential to the right is still the bias current I Half of the principle and operation of Fig. 3 are the same as those of equations (1), (3), (5), and (6). Therefore, as long as R1=Re2, that is, if the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re2 of the second resistor 104, the third resistor 106, and the fourth resistor 202, the change dVD of the output voltage VD is zero. That is, the voltage value of the output voltage VD is a stable fixed value and does not change with the voltage change dVDD of the voltage source VDD.

請參照第4圖，第4圖為本發明的第四實施例說明固定電壓產生 電路400的示意圖。固定電壓產生電路400包含固定電壓產生電路100的元件、第五電阻302及第六電阻304。其中第五電阻302係耦接於第三電晶體112的第一端與第二電晶體110的第二端之間；而第六電阻304則係耦接於第四電晶體114的第一端與第二電晶體110的第二端之間。 Please refer to FIG. 4, which shows a fixed voltage generation according to a fourth embodiment of the present invention. A schematic diagram of circuit 400. The fixed voltage generating circuit 400 includes an element of the fixed voltage generating circuit 100, a fifth resistor 302, and a sixth resistor 304. The fifth resistor 302 is coupled between the first end of the third transistor 112 and the second end of the second transistor 110; and the sixth resistor 304 is coupled to the first end of the fourth transistor 114. Between the second end of the second transistor 110.

第4圖中，偏壓電流I流過差動對、第五電阻302及第六電阻304， 當第二電阻104阻值等於第三電阻106阻值，第五電阻302阻值等於第六電阻304阻值時，流過差動對右側的電流仍為偏壓電流I的一半，此時第4圖的原理及動作同式(1)、式(2)、式(3)、式(4)所述。因此只要R1=Re1，亦即 若第一電阻102的阻值實質上等於第二電阻104及第三電阻106的等效阻值Re1，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD的電壓值為一固定值且不隨電壓源VDD的電壓變化dVDD而改變。 In FIG. 4, the bias current I flows through the differential pair, the fifth resistor 302, and the sixth resistor 304, When the resistance of the second resistor 104 is equal to the resistance of the third resistor 106, and the resistance of the fifth resistor 302 is equal to the resistance of the sixth resistor 304, the current flowing through the differential to the right is still half of the bias current I. The principle and operation of Figure 4 are as described in equations (1), (2), (3), and (4). So as long as R1=Re1, ie If the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re1 of the second resistor 104 and the third resistor 106, the change dVD of the output voltage VD is zero. That is, the voltage value of the output voltage VD is a fixed value and does not change with the voltage change dVDD of the voltage source VDD.

請參照第5圖，第5圖為本發明的第五實施例說明固定電壓產生 電路500的示意圖。固定電壓產生電路500包含固定電壓產生電路100的元件以及n個二極體520，其中n為正整數。第一電阻102與n個二極體520串聯，且於此串聯線路當中每一個二極體520皆以順偏壓的方式連接，亦即每一個二極體520的陽極之電位要比陰極的電位來得高。於第5圖的實施例中，n個二極體520可串聯於電壓源VDD及第一電阻102之間，而於另一實施例中，第一電阻102可串聯於電壓源VDD及n個二極體520之間，於又一實施例中，第一電阻102亦可串聯於任意兩個二極體520之間，此外，第一電阻102可為由分佈於電壓源VDD及第一電晶體108的控制端之間的複數個電阻所組成，然而本發明並不以此為限。 Please refer to FIG. 5. FIG. 5 is a diagram showing a fixed voltage generation according to a fifth embodiment of the present invention. A schematic diagram of circuit 500. The fixed voltage generating circuit 500 includes elements of the fixed voltage generating circuit 100 and n diodes 520, where n is a positive integer. The first resistor 102 is connected in series with the n diodes 520, and each of the diodes 520 is connected in a biased manner, that is, the potential of the anode of each of the diodes 520 is higher than that of the cathode. The potential is high. In the embodiment of FIG. 5, the n diodes 520 can be connected in series between the voltage source VDD and the first resistor 102. In another embodiment, the first resistor 102 can be connected in series to the voltage source VDD and n. In another embodiment, the first resistor 102 can also be connected in series between any two diodes 520. In addition, the first resistor 102 can be distributed between the voltage source VDD and the first resistor. The plurality of resistors between the control terminals of the crystal 108 are formed, but the invention is not limited thereto.

於一實施例中，二極體520可為接面二極體、場效電晶體或雙極 性接面電晶體。請參考第6圖，第6圖說明了場效電晶體60如何實現二極體520的作法。場效電晶體60包含控制端60A，第一端60B及第二端60C。於一實施例中，場效電晶體60為N型場效電晶體，而其控制端60A耦接於場效電晶體60的第一端60B並等效為二極體520的陽極，而場效電晶體60的第二端60C則等效為二極體520的陰極。於另一實施例中，場效電晶體60為P型場效電晶體，而其控制端60A耦接於場效電晶體60的第一端60B並等效為二極體520的陰極，而場效電晶體60的第二端60C則等效為二極體520的陽極。請參考第7圖，第7圖說明了雙極性接面電晶體70如何實現二極體520的作法。雙極性接面電晶體70包含控制端70A，第一端70B及第二端70C。於一實施例中，雙極性接面電晶體70為PNP型雙極性接面電晶體， 而其控制端70A耦接於雙極性接面電晶體70的第一端70B並等效為二極體520的陰極，而雙極性接面電晶體70的第二端70C則等效為二極體520的陽極。於另一實施例中，雙極性接面電晶體70為NPN型雙極性接面電晶體，而其控制端70A耦接於雙極性接面電晶體70的第一端70B並等效為二極體520的陽極，而雙極性接面電晶體70的第二端70C則等效為二極體520的陰極。 In one embodiment, the diode 520 can be a junction diode, a field effect transistor, or a bipolar. Sex junction transistor. Please refer to FIG. 6. FIG. 6 illustrates how the field effect transistor 60 implements the diode 520. The field effect transistor 60 includes a control terminal 60A, a first end 60B and a second end 60C. In one embodiment, the field effect transistor 60 is an N-type field effect transistor, and the control terminal 60A is coupled to the first end 60B of the field effect transistor 60 and is equivalent to the anode of the diode 520. The second end 60C of the effect transistor 60 is equivalent to the cathode of the diode 520. In another embodiment, the field effect transistor 60 is a P-type field effect transistor, and the control terminal 60A is coupled to the first end 60B of the field effect transistor 60 and is equivalent to the cathode of the diode 520. The second end 60C of the field effect transistor 60 is equivalent to the anode of the diode 520. Please refer to FIG. 7. FIG. 7 illustrates how the bipolar junction transistor 70 implements the diode 520. The bipolar junction transistor 70 includes a control terminal 70A, a first end 70B and a second end 70C. In one embodiment, the bipolar junction transistor 70 is a PNP type bipolar junction transistor. The control terminal 70A is coupled to the first end 70B of the bipolar junction transistor 70 and is equivalent to the cathode of the diode 520, and the second terminal 70C of the bipolar junction transistor 70 is equivalent to the diode. The anode of body 520. In another embodiment, the bipolar junction transistor 70 is an NPN-type bipolar junction transistor, and the control terminal 70A is coupled to the first end 70B of the bipolar junction transistor 70 and is equivalent to a diode. The anode of the body 520, and the second end 70C of the bipolar junction transistor 70 is equivalent to the cathode of the diode 520.

固定電壓產生電路500與固定電壓產生電路100之差異在於固定 電壓產生電路500之第一電晶體108之控制端的偏壓係由第一電阻102及n個二極體520根據電壓源VDD產生，由於第二電晶體110為第一電晶體108的電流鏡，因此第二電晶體110的控制端亦會根據此偏壓產生偏壓電流I，如式(7)所示。 The difference between the fixed voltage generating circuit 500 and the fixed voltage generating circuit 100 is that it is fixed The bias voltage of the control terminal of the first transistor 108 of the voltage generating circuit 500 is generated by the first resistor 102 and the n diodes 520 according to the voltage source VDD. Since the second transistor 110 is the current mirror of the first transistor 108, Therefore, the control terminal of the second transistor 110 also generates a bias current I according to the bias voltage, as shown in the equation (7).

其中Vt1是電晶體108的導通電壓，而VDk則係第k個二極體520 的順向偏壓。偏壓電流I流過由第三電晶體112、第四電晶體114、第二電阻104及第三電阻106組成的差動對，由於差動對左右兩側的組件對稱，因此流過差動對的右側，包含第四電晶體114及第三電阻106的電流為偏壓電流I的一半。差動對亦耦接於電壓源VDD，因此於第四電晶體114的第二端會產生輸出電壓VD，如式(8)。 Where V t1 is the turn-on voltage of the transistor 108 and V Dk is the forward bias of the kth diode 520. The bias current I flows through the differential pair composed of the third transistor 112, the fourth transistor 114, the second resistor 104, and the third resistor 106. Since the differential is symmetric to the components on the left and right sides, the differential flows. On the right side of the pair, the current including the fourth transistor 114 and the third resistor 106 is half of the bias current I. The differential pair is also coupled to the voltage source VDD, so an output voltage VD is generated at the second end of the fourth transistor 114, as in equation (8).

其中式(8)中的Re1與式(2)中的Re1同為第二電阻104及第三電阻 106的等效阻值。由於差動對左右兩側為並聯結構，第二電阻104及第三電阻106的等效阻值為第二電阻104及第三電阻106並聯後的阻值，且第二電 阻104及第三電阻106的阻值實質上相等，所以。在此實施例中， 第一電阻102、第二電阻104與第三電阻106的阻值比例為1：2：2，所以 Re1=R1。由式(8)，輸出電壓VD的電壓值為，亦即只要透過改變 二極體520的個數n即可調整輸出電壓VD的電壓值。 Re1 in the formula (8) and Re1 in the formula (2) are the equivalent resistance values of the second resistor 104 and the third resistor 106. Since the difference between the left and right sides is a parallel structure, the equivalent resistance of the second resistor 104 and the third resistor 106 is the resistance of the second resistor 104 and the third resistor 106 in parallel, and the second resistor 104 and the third resistor The resistance of 106 is substantially equal, so . In this embodiment, the resistance ratio of the first resistor 102, the second resistor 104, and the third resistor 106 is 1:2:2, so Re1=R1. From equation (8), the voltage value of the output voltage VD is That is, the voltage value of the output voltage VD can be adjusted by changing the number n of the diodes 520.

另外，根據式(7)，當電壓源VDD變化時，流過差動對的偏壓電 流I亦隨之改變。若電壓源VDD的電壓變化為dVDD，偏壓電流I的變化為dI，則dI如式(9)，而輸出電壓VD的變化dVD如式(10)。於式(10)中，若R1=Re1，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD仍為固定電壓且不隨電壓源VDD的電壓變化dVDD而改變。 In addition, according to equation (7), when the voltage source VDD changes, the bias current flowing through the differential pair Stream I also changes. If the voltage of the voltage source VDD changes to dVDD, the change of the bias current I is dI, then dI is as in equation (9), and the change in output voltage VD is dVD as in equation (10). In the equation (10), if R1 = Re1, the change dVD of the output voltage VD is zero. That is, the output voltage VD is still a fixed voltage and does not change with the voltage change dVDD of the voltage source VDD.

由上述可知，如第5圖的電路結構可產生不隨電壓源VDD變化 的輸出電壓VD，並且可以藉由調整二極體的數量來改變輸出電壓VD的電壓值，且於上述調整過程中，僅需調整多個電阻阻值的比例及二極體的數量，因此無須另使用CMOS製程，而可在砷化鎵製程中產生固定電壓，如此可減少製程所需要的面積及增加集成度。 As can be seen from the above, the circuit structure as shown in FIG. 5 can be generated without changing with the voltage source VDD. The output voltage VD, and the voltage value of the output voltage VD can be changed by adjusting the number of diodes, and in the above adjustment process, only the ratio of the resistance values of the plurality of resistors and the number of the diodes need to be adjusted, so there is no need Another CMOS process is used to generate a fixed voltage in the GaAs process, which reduces the area required for the process and increases integration.

請參照第8圖，第8圖為本發明的第六實施例說明固定電壓產生 電路800的示意圖。固定電壓產生電路800包含固定電壓產生電路200的元件以及n個二極體520。第一電阻102與n個二極體520串聯，且於此串聯線路當中每一個二極體520皆以順偏壓的方式連接，亦即每一個二極體520的陽極之電位要比陰極的電位來得高。 Please refer to FIG. 8. FIG. 8 is a diagram showing a fixed voltage generation according to a sixth embodiment of the present invention. A schematic diagram of circuit 800. The fixed voltage generating circuit 800 includes elements of the fixed voltage generating circuit 200 and n diodes 520. The first resistor 102 is connected in series with the n diodes 520, and each of the diodes 520 is connected in a biased manner, that is, the potential of the anode of each of the diodes 520 is higher than that of the cathode. The potential is high.

第8圖中的固定電壓產生電路800與第2圖中的固定電壓產生電 路200有相同的原理及操作，其差別僅在於第8圖中的偏壓電流I係如式(7)所示。於第8圖中，偏壓電流I流過第四電阻202及由第三電晶體112、第四電晶體114、第二電阻104及第三電阻106組成的差動對。由於差動對左右兩側的組件對稱，導致流過第四電晶體114及第三電阻106的電流為偏壓電流I的一半，因此輸出電壓VD係如式(11)所示。 The fixed voltage generating circuit 800 in FIG. 8 generates electricity with the fixed voltage in FIG. The circuit 200 has the same principle and operation, the only difference being that the bias current I in Fig. 8 is as shown in equation (7). In FIG. 8, the bias current I flows through the fourth resistor 202 and a differential pair composed of the third transistor 112, the fourth transistor 114, the second resistor 104, and the third resistor 106. Since the differential is symmetric with respect to the components on the left and right sides, the current flowing through the fourth transistor 114 and the third resistor 106 is half of the bias current I, and thus the output voltage VD is as shown in the equation (11).

由於差動對左右兩側為並聯結構，第二電阻104及第三電阻106 的等效阻值為第二電阻104及第三電阻106並聯後的阻值，而第二電阻104、第三電阻106及第四電阻202的等效阻值為第二電阻104及第三電阻106的等效阻值加上第四電阻202的阻值，且第二電阻104及第三電阻106的阻值實質上相等，所以。由式(11)，輸出電壓VD之電壓值為 Since the difference between the left and right sides is a parallel structure, the equivalent resistance of the second resistor 104 and the third resistor 106 is the resistance of the second resistor 104 and the third resistor 106 in parallel, and the second resistor 104 and the third resistor The equivalent resistance of the 106 and the fourth resistor 202 is the equivalent resistance of the second resistor 104 and the third resistor 106 plus the resistance of the fourth resistor 202, and the resistance values of the second resistor 104 and the third resistor 106 are substantially Equal on, so . From equation (11), the voltage value of the output voltage VD is

由式(7)，當電壓源VDD變化時，偏壓電流I亦隨之改變。偏壓 電流I的變化dI如式(9)，而輸出電壓VD的變化dVD如式(12)。於式(12)中，若R1=Re2，亦即第一電阻102的阻值實質上等於第二電阻104、第三電阻106及第四電阻202的等效阻值Re2，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD為穩定的固定電壓，且不隨著電壓源VDD的電壓變化dVDD而改變。 From equation (7), when the voltage source VDD changes, the bias current I also changes. bias The change dI of the current I is as in the equation (9), and the change dVD of the output voltage VD is as in the equation (12). In the formula (12), if R1=Re2, that is, the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re2 of the second resistor 104, the third resistor 106, and the fourth resistor 202, the output voltage VD The change dVD is zero. That is, the output voltage VD is a stable fixed voltage and does not change with the voltage change dVDD of the voltage source VDD.

由上述可知，固定電壓產生電路800之輸出電壓VD不會隨著電 壓源VDD的變動而產生變化，且可以透過改變二極體520的數量來改變輸出電壓VD的電壓值。因此可在不使用CMOS製程情況下，於砷化鎵製程中產生固定電壓，並可在大範圍輸入電壓變動的情形下正常工作。 As can be seen from the above, the output voltage VD of the fixed voltage generating circuit 800 does not follow the electricity. The variation of the voltage source VDD changes, and the voltage value of the output voltage VD can be changed by changing the number of the diodes 520. Therefore, a fixed voltage can be generated in the gallium arsenide process without using a CMOS process, and it can work normally under a wide range of input voltage variations.

請參照第9圖，第9圖為本發明的第七實施例說明固定電壓產生 電路900的示意圖。固定電壓產生電路900包含固定電壓產生電路300的元件以及n個二極體520。第一電阻102與n個二極體520串聯，且於此串聯線路當中每一個二極體520皆以順偏壓的方式連接，亦即每一個二極體520的陽極之電位要比陰極的電位來得高。 Please refer to FIG. 9. FIG. 9 is a diagram showing a fixed voltage generation according to a seventh embodiment of the present invention. A schematic diagram of circuit 900. The fixed voltage generating circuit 900 includes elements of the fixed voltage generating circuit 300 and n diodes 520. The first resistor 102 is connected in series with the n diodes 520, and each of the diodes 520 is connected in a biased manner, that is, the potential of the anode of each of the diodes 520 is higher than that of the cathode. The potential is high.

第9圖中，偏壓電流I流過差動對、第四電阻202、第五電阻302 及第六電阻304，當第二電阻104阻值等於第三電阻106阻值，第五電阻302阻值等於第六電阻304阻值時，流過差動對右側的電流仍為偏壓電流I的一半。第9圖的原理及動作同式(7)、式(9)、式(11)、式(12)所述。因此只要R1=Re2，亦即若第一電阻102的阻值實質上等於第二電阻104、第三電阻106及第四電阻202的等效阻值Re2，則輸出電壓VD的變化dVD為零。亦即輸出 電壓VD為一穩定的固定電壓且不隨著電壓源VDD的電壓變化dVDD而改變，且輸出電壓VD的電壓值可透過串聯二極體520的數量來調整。 In FIG. 9, the bias current I flows through the differential pair, the fourth resistor 202, and the fifth resistor 302. And the sixth resistor 304, when the resistance of the second resistor 104 is equal to the resistance of the third resistor 106, and the resistance of the fifth resistor 302 is equal to the resistance of the sixth resistor 304, the current flowing through the differential to the right is still the bias current I Half of it. The principle and operation of Fig. 9 are as described in the equations (7), (9), (11), and (12). Therefore, as long as R1=Re2, that is, if the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re2 of the second resistor 104, the third resistor 106, and the fourth resistor 202, the change dVD of the output voltage VD is zero. Output The voltage VD is a stable fixed voltage and does not change with the voltage change dVDD of the voltage source VDD, and the voltage value of the output voltage VD can be adjusted by the number of series diodes 520.

請參照第10圖，第10圖為本發明的第八實施例說明固定電壓產 生電路1000的示意圖。固定電壓產生電路1000包含固定電壓產生電路400的元件以及n個二極體520。其中n為大於0之正整數。第一電阻102與n個二極體520串聯，且於此串聯線路當中每一個二極體520皆以順偏壓的方式連接，亦即每一個二極體520的陽極之電位要比陰極的電位來得高。 Please refer to FIG. 10, which shows a fixed voltage production according to an eighth embodiment of the present invention. Schematic diagram of the circuit 1000. The fixed voltage generating circuit 1000 includes elements of the fixed voltage generating circuit 400 and n diodes 520. Where n is a positive integer greater than zero. The first resistor 102 is connected in series with the n diodes 520, and each of the diodes 520 is connected in a biased manner, that is, the potential of the anode of each of the diodes 520 is higher than that of the cathode. The potential is high.

第10圖中，偏壓電流I流過差動對、第五電阻302及第六電阻 304，當第二電阻104阻值等於第三電阻106阻值，第五電阻302阻值等於第六電阻304阻值時，流過差動對右側的電流仍為偏壓電流I的一半。第10圖的原理及動作同式(7)、式(8)、式(9)、式(10)所述。因此只要R1=Re1，亦即若第一電阻102的阻值實質上等於第二電阻104及第三電阻106的等效阻值Re1，則輸出電壓VD的變化dVD為零。亦即輸出電壓VD為一穩定的固定電壓且不會隨電壓源VDD的電壓變化dVDD而改變，且輸出電壓VD的電壓值可透過串聯二極體520的數量來調整。 In Fig. 10, the bias current I flows through the differential pair, the fifth resistor 302, and the sixth resistor. 304, when the resistance of the second resistor 104 is equal to the resistance of the third resistor 106, and the resistance of the fifth resistor 302 is equal to the resistance of the sixth resistor 304, the current flowing through the differential to the right side is still half of the bias current I. The principle and operation of Fig. 10 are as described in the equations (7), (8), (9), and (10). Therefore, as long as R1=Re1, that is, if the resistance of the first resistor 102 is substantially equal to the equivalent resistance Re1 of the second resistor 104 and the third resistor 106, the change dVD of the output voltage VD is zero. That is, the output voltage VD is a stable fixed voltage and does not change with the voltage change dVDD of the voltage source VDD, and the voltage value of the output voltage VD can be adjusted by the number of series diodes 520.

如第5圖的實施例，在第8至10圖的實施例中，n個二極體520 可串聯於電壓源VDD及第一電阻102之間，或第一電阻102可串聯於電壓源VDD及n個二極體520之間，或者第一電阻102亦可串聯於任意兩個二極體520之間，此外，第一電阻102可為由分佈於電壓源VDD及第一電晶體108的控制端之間的複數個電阻所組成，然而本發明並不以此為限。 As in the embodiment of Fig. 5, in the embodiment of Figs. 8 to 10, n diodes 520 The first resistor 102 can be connected in series between the voltage source VDD and the first resistor 102, or the first resistor 102 can be connected in series between any two diodes. In addition, the first resistor 102 may be composed of a plurality of resistors distributed between the voltage source VDD and the control terminal of the first transistor 108, but the invention is not limited thereto.

綜上所述，本發明提出的固定電壓產生電路可產生穩定的輸出電壓，而且不會隨著電壓源的變動而產生變化，因此可以在大範圍輸入電壓變動的情形下正常地工作。另外，本發明亦可透過串聯多個二極體來調整輸出 電壓的電壓值以符合系統的需求。由於本發明係藉由調整多個電阻之阻值的比例以及電阻連接於電壓源的方式來提供輸出電壓，因此可以在砷化鎵製程中產生固定電壓，而不須另使用CMOS製程，如此可減少製程所需要的面積及增加集成度。 In summary, the fixed voltage generating circuit proposed by the present invention can generate a stable output voltage and does not change with the variation of the voltage source, so that it can operate normally under a wide range of input voltage variations. In addition, the present invention can also adjust the output by connecting a plurality of diodes in series. The voltage value of the voltage is in accordance with the requirements of the system. Since the present invention provides an output voltage by adjusting the ratio of the resistances of the plurality of resistors and the manner in which the resistors are connected to the voltage source, a fixed voltage can be generated in the gallium arsenide process without using a CMOS process. Reduce the area required for the process and increase integration.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧固定電壓產生電路 100‧‧‧Fixed voltage generating circuit

102‧‧‧第一電阻 102‧‧‧First resistance

104‧‧‧第二電阻 104‧‧‧second resistance

106‧‧‧第三電阻 106‧‧‧ Third resistor

108‧‧‧第一電晶體 108‧‧‧First transistor

110‧‧‧第二電晶體 110‧‧‧Second transistor

112‧‧‧第三電晶體 112‧‧‧ Third transistor

114‧‧‧第四電晶體 114‧‧‧fourth transistor

VDD‧‧‧電壓源 VDD‧‧‧voltage source

VD‧‧‧輸出電壓 VD‧‧‧ output voltage

I‧‧‧偏壓電流 I‧‧‧Butable current

Claims (10)

一種固定電壓產生電路，包含：一第一電阻，包含第一端及第二端，該第一電阻的第二端耦接於一電壓源；一第一電晶體，包含第一端、第二端，以及控制端，該第一電晶體的控制端耦接於該第一電阻的第一端，該第一電晶體的第一端耦接於一接地端，及該第一電晶體的第二端耦接於該第一電晶體的控制端；一第二電晶體，包含第一端、第二端，以及控制端，該第二電晶體的控制端耦接於該第一電晶體的控制端，及該第二電晶體的第一端，耦接於該接地端；一第三電晶體，包含第一端、第二端，以及控制端，該第三電晶體的控制端用以接收一第一差動電壓，該第三電晶體的第一端耦接於該第二電晶體的第二端；一第四電晶體，包含第一端、第二端，以及控制端，該第四電晶體的控制端用以接收一第二差動電壓，該第四電晶體的第一端耦接於該第二電晶體的第二端，及該第四電晶體的第二端用以輸出一固定電壓；一第二電阻，包含第一端以及第二端，該第二電阻的第一端耦接於該第三電晶體的第二端，該第二電阻的第二端耦接於該電壓源；及一第三電阻，包含第一端以及第二端，該第三電阻的第一端耦接於該第四電晶體的第二端，該第三電阻的第二端耦接於該電壓源；其中該第二電阻的阻值及該第三電阻的阻值與該第一電阻的阻值有關。 A fixed voltage generating circuit comprising: a first resistor comprising a first end and a second end, the second end of the first resistor being coupled to a voltage source; a first transistor comprising a first end, a second And a control end, the control end of the first transistor is coupled to the first end of the first resistor, the first end of the first transistor is coupled to a ground end, and the first transistor The second end is coupled to the control end of the first transistor; the second transistor includes a first end, a second end, and a control end, and the control end of the second transistor is coupled to the first transistor The control terminal, and the first end of the second transistor, is coupled to the ground end; a third transistor includes a first end, a second end, and a control end, and the control end of the third transistor is used Receiving a first differential voltage, the first end of the third transistor is coupled to the second end of the second transistor; a fourth transistor includes a first end, a second end, and a control end, The control end of the fourth transistor is configured to receive a second differential voltage, and the first end of the fourth transistor is coupled to the second The second end of the crystal and the second end of the fourth transistor are configured to output a fixed voltage; the second resistor includes a first end and a second end, and the first end of the second resistor is coupled to the first end a second end of the third transistor, the second end of the second resistor is coupled to the voltage source; and a third resistor includes a first end and a second end, the first end of the third resistor is coupled to the The second end of the fourth transistor is coupled to the voltage source; wherein the resistance of the second resistor and the resistance of the third resistor are related to the resistance of the first resistor. 如請求項1所述的固定電壓產生電路，另包含：一第四電阻，包含第一端及第二端，該第四電阻的第一端耦接於該第二電阻的第二端及該第三電阻的第二端，及該第四電阻的第二端耦接 於該電壓源。 The fixed voltage generating circuit of claim 1, further comprising: a fourth resistor comprising a first end and a second end, the first end of the fourth resistor being coupled to the second end of the second resistor and the a second end of the third resistor and a second end of the fourth resistor are coupled For this voltage source. 如請求項2所述的固定電壓產生電路，另包含：一第五電阻，耦接於該第三電晶體的第一端與該第二電晶體的第二端之間；及一第六電阻，耦接於該第四電晶體的第一端與該第二電晶體的第二端之間。 The fixed voltage generating circuit of claim 2, further comprising: a fifth resistor coupled between the first end of the third transistor and the second end of the second transistor; and a sixth resistor And being coupled between the first end of the fourth transistor and the second end of the second transistor. 如請求項2或3所述的固定電壓產生電路，其中該第二電阻、該第三電阻，及該第四電阻的等效阻值等於該第一電阻的阻值，且該第一電晶體及該第二電晶體的尺寸比例係為1：1。 The fixed voltage generating circuit of claim 2 or 3, wherein an equivalent resistance of the second resistor, the third resistor, and the fourth resistor is equal to a resistance of the first resistor, and the first transistor And the size ratio of the second transistor is 1:1. 如請求項1所述的固定電壓產生電路，另包含：一第五電阻，耦接於該第三電晶體的第一端與該第二電晶體的第二端之間；及一第六電阻，耦接於該第四電晶體的第一端與該第二電晶體的第二端之間。 The fixed voltage generating circuit of claim 1, further comprising: a fifth resistor coupled between the first end of the third transistor and the second end of the second transistor; and a sixth resistor And being coupled between the first end of the fourth transistor and the second end of the second transistor. 如請求項1或5所述的固定電壓產生電路，其中該第二電阻與該第三電阻的等效阻值等於該第一電阻的阻值，該第一電晶體及該第二電晶體的尺寸比例係為1：1。 The fixed voltage generating circuit of claim 1 or 5, wherein an equivalent resistance of the second resistor and the third resistor is equal to a resistance of the first resistor, and the first transistor and the second transistor The size ratio is 1:1. 如請求項1至3及5中任一項所述的固定電壓產生電路，另包含n個二極體，耦接於該電壓源與該第一電晶體的控制端之間，其中n為正整數。 The fixed voltage generating circuit according to any one of claims 1 to 3, further comprising n diodes coupled between the voltage source and a control end of the first transistor, wherein n is positive Integer. 如請求項7所述的固定電壓產生電路，其中該些二極體為接面二極體、場效電晶體或雙極性接面電晶體。 The fixed voltage generating circuit of claim 7, wherein the diodes are junction diodes, field effect transistors or bipolar junction transistors. 如請求項1至3及5中任一項所述的固定電壓產生電路，其中該第一電晶體及該第二電晶體形成一電流鏡，該第一電晶體及該第二電晶體的尺寸比例係為1：N或N：1，N為正整數。 The fixed voltage generating circuit according to any one of claims 1 to 3, wherein the first transistor and the second transistor form a current mirror, and the size of the first transistor and the second transistor The ratio is 1:N or N:1, and N is a positive integer. 如請求項1至3及5中任一項所述的固定電壓產生電路，其中該固定電壓產生電路為使用一砷化鎵製程。 The fixed voltage generating circuit according to any one of claims 1 to 3, wherein the fixed voltage generating circuit is a gallium arsenide process.
TW103107507A 2013-03-05 2014-03-05 Fixed voltage generating circuit TWI546644B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW103107507A TWI546644B (en) 2013-03-05 2014-03-05 Fixed voltage generating circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW102107705 2013-03-05
TW103107507A TWI546644B (en) 2013-03-05 2014-03-05 Fixed voltage generating circuit

Publications (2)

Publication Number Publication Date
TW201435541A TW201435541A (en) 2014-09-16
TWI546644B true TWI546644B (en) 2016-08-21

Family

ID=51466271

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103107507A TWI546644B (en) 2013-03-05 2014-03-05 Fixed voltage generating circuit

Country Status (3)

Country Link
US (1) US20140253087A1 (en)
CN (1) CN104035466B (en)
TW (1) TWI546644B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9088252B2 (en) * 2013-03-05 2015-07-21 Richwave Technology Corp. Fixed voltage generating circuit
US10848109B2 (en) 2017-01-26 2020-11-24 Analog Devices, Inc. Bias modulation active linearization for broadband amplifiers
TWI734221B (en) * 2019-10-16 2021-07-21 立積電子股份有限公司 Radio frequency apparatus and voltage generating device thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495425A (en) * 1982-06-24 1985-01-22 Motorola, Inc. VBE Voltage reference circuit
US4492929A (en) * 1983-05-13 1985-01-08 Motorola, Inc. Operational amplifier having enhanced gain through current feedback
JP3016317B2 (en) * 1993-02-05 2000-03-06 日本電気株式会社 Variable gain amplifier
JPH07106875A (en) * 1993-09-30 1995-04-21 Nec Corp Semiconductor integrated circuit
KR19990008200A (en) * 1996-02-28 1999-01-25 요트.게.아. 롤페즈 Reference voltage source with temperature compensation
US5856749A (en) * 1996-11-01 1999-01-05 Burr-Brown Corporation Stable output bias current circuitry and method for low-impedance CMOS output stage
JP3147082B2 (en) * 1997-10-15 2001-03-19 日本電気株式会社 Differential amplifier circuit
JP2000174562A (en) * 1998-12-09 2000-06-23 Sony Corp Input circuit
JP2009021685A (en) * 2007-07-10 2009-01-29 Mitsubishi Electric Corp Constant current source circuit and differential amplifier device
JP5003346B2 (en) * 2007-08-21 2012-08-15 日本電気株式会社 Reference voltage generation circuit and reference voltage distribution method
US9088252B2 (en) * 2013-03-05 2015-07-21 Richwave Technology Corp. Fixed voltage generating circuit

Also Published As

Publication number Publication date
TW201435541A (en) 2014-09-16
CN104035466A (en) 2014-09-10
US20140253087A1 (en) 2014-09-11
CN104035466B (en) 2016-08-24

Similar Documents

Publication Publication Date Title
CN102053645B (en) Wide-input voltage high-power supply rejection ratio reference voltage source
US20060202721A1 (en) Differential comparator with extended common mode voltage range
JP2015061294A (en) Cascode amplifier
TWI546644B (en) Fixed voltage generating circuit
CN206671935U (en) A kind of bipolar transistor amplifier with input current compensation circuit
CN107565928B (en) Capacitance multiplier with high multiplication coefficient
GB2477572A (en) A class AB wideband high-power current output push-pull amplifier
US8742845B2 (en) Amplifier circuits with reduced power consumption
KR102278562B1 (en) Method and apparatus for a floating current source
US10141897B2 (en) Source follower
CN101834575B (en) Operational amplifier
CN108693912B (en) Bandgap reference circuit with inverted bandgap pairs
US9088252B2 (en) Fixed voltage generating circuit
KR101618971B1 (en) Power amplifier of the inverter form
CN107395146B (en) Constant transconductance amplifier circuit
TWI644195B (en) Buffer stage and a control circuit
US20130181771A1 (en) Light receiving circuit and photo-coupling type insulated circuit
JP6969884B2 (en) Current detection amplifier
JP2008172538A (en) Bias circuit and power amplifier
CN108170195B (en) Source follower
US7230476B1 (en) Bipolar high impedance element
KR20050030610A (en) Current mirror circuit
JP6020238B2 (en) Amplifier circuit
CN103580622A (en) Signal amplifier
JP2022009496A (en) Current detection amplifier