CN114995576A - Bidirectional self-bias bipolar current mirror circuit adaptive to low-voltage operation - Google Patents
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Abstract
The invention provides a bidirectional self-bias bipolar current mirror circuit adapting to low-voltage work, which comprises: a current source current mirror circuit and a current sink current mirror circuit; the current source current mirror circuit and the current sink current mirror circuit both use a public power supply positive end and a public power supply negative end as power supply connection ends; the current source current mirror circuit comprises a current source input side PNP tube P1, a first base electrode current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2; the current sink current mirror circuit comprises a current sink input side NPN transistor N1, a second base current compensation circuit, a second beta-helper circuit, a current sink output side NPN transistor and a bias current source I1. The invention utilizes the emitter current of the first emitter follower as the current source supply of the second base current compensation circuit, and the emitter current of the second emitter follower as the current source supply of the first base current compensation circuit, so that bias currents are mutually provided, no additional bias circuit is relied on, and low-voltage operation is simultaneously satisfied.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a bidirectional self-bias bipolar current mirror circuit suitable for low-voltage work.
Background
1. The existing current mirror has the precision problem when being used as a current source or a current sink, and the reason is that the base electrode flow direction current of the current mirror is overlarge; in addition, the triode device is arranged at different positions of a chip layout, so that the lengths of the emitter wires of the triode device are different, the resistance values of parasitic resistors of the triode device are different, and the collector current of the BJT device is very sensitive to the BE junction voltage of the BJT device, so that the parasitic resistors of the emitter wires have great influence on the image accuracy.
2. The existing precision optimization scheme usually adopts a mode of reducing the base flowing current of a current mirror structure and setting an emitter feedback resistor to improve the precision, for example, a beta-helper structure (the electric connection between a collector and a base of a triode at the input side of the current mirror is replaced by triode gain connection, and the current at the input side of the current mirror is more accurately matched with the current at the output side of the current mirror by reducing the shunt of the collector to the base of the triode at the input side of the current mirror) or a base current compensation scheme is adopted for reducing the base flowing current, but the precision of the scheme has a further optimization space, for example, as shown in fig. 1 to 5 (formula), more bias circuits are needed to realize stable voltage or current supply, and higher working voltage is required by bias voltage when a current mirror current source and a current mirror sink are adopted.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a bidirectional self-bias bipolar current mirror circuit adaptive to low-voltage work, so as to solve the technical problem that the mirror accuracy of the current mirror circuit needs more bias circuits to stabilize voltage or current supply.
The invention provides a bidirectional self-bias bipolar current mirror circuit adapting to low-voltage work, which comprises: a current source current mirror circuit and a current sink current mirror circuit; the current source current mirror circuit and the current sink current mirror circuit both use a public power supply positive end and a public power supply negative end as power supply connection ends;
the current source current mirror circuit comprises a current source input side PNP tube P1, a first base electrode current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2;
the bias current source I2 supplies current to the collector current of a PNP tube P1 at the input side of the current source;
the first base current compensation circuit is used for reducing the current shunt of the bias current source I2 at the collector of the PNP tube P1 at the current source input side; wherein the first base current compensation circuit comprises a first emitter follower, an emitter current of the first emitter follower is used for providing a bias current for the second base current compensation circuit;
the current sink current mirror circuit comprises a current sink input side NPN tube N1, a second base current compensation circuit, a second beta-helper circuit, a current sink output side NPN tube and a bias current source I1;
the bias current source I1 supplies collector current of a current sink input side NPN tube N1;
the second base current compensation circuit is used for reducing the current shunt of the bias current source I1 at the collector electrode of the current sink input side NPN tube N1; the second base current compensation circuit comprises a second emitter follower, and the emitter current of the second emitter follower is used for providing bias current for the first base current compensation circuit.
Optionally, the number of transistors included in each of the first β -helper circuit and the second β -helper circuit is at least two.
Optionally, the first β -helper circuit and the first base current compensation circuit comprise a common NPN transistor;
the second beta-helper circuit and the second base current compensation circuit comprise a common PNP transistor.
Optionally, the working transistor of the first emitter follower in the first base current compensation circuit is a PNP transistor P2, the first emitter follower serves as a bias current source I3, and a collector of the PNP transistor P2 provides a bias current for the emitter of the common PNP triode;
the working tube of the second emitter follower in the second base current compensation circuit is an NPN tube N2, the second emitter follower is used as a bias current source I4, and bias current is provided for the emitter of the common NPN triode through the collector of the NPN tube N2.
Optionally, the emitter of the PNP transistor P2 is connected to the positive terminal of the common power supply through the resistor R4, and the collector of the PNP transistor P2 is connected to the emitter of the common PNP triode; the collector of the shared PNP triode is connected with the negative end of the common power supply; the base electrode of the PNP tube P2 and the base electrode of the common NPN triode are connected with the collector electrode of the PNP tube P1 at the current source input side so as to commonly reduce the current shunt of the bias current source I2 at the collector electrode of the PNP tube P1 at the current source input side;
an emitter of the NPN tube N2 is connected with the negative end of a public power supply through a resistor R3, and a collector of the NPN tube N2 is connected with an emitter of the common NPN triode; the collector of the shared NPN triode is connected with the positive end of the common power supply; the base of the NPN transistor N2 and the base of the common PNP transistor are both connected to the collector of the current sink input-side NPN transistor N1 to collectively reduce current shunting of the bias current source I1 at the collector of the current sink input-side NPN transistor N1.
Optionally, the first β -helper circuit further includes an NPN transistor N5 and a PNP transistor P4, an emitter of the NPN transistor N5 is connected to an emitter of the PNP transistor P4, a base of the PNP transistor P1 on the current source input side, and a base of the PNP transistor on the current source output side, a collector of the NPN transistor N5 is connected to the positive terminal of the common power supply, and a base of the NPN transistor N2 is connected to an emitter of the PNP transistor P4; the base electrode of the PNP pipe P4 is connected with the emitter electrode of the common NPN triode, and the collector electrode of the PNP pipe P4 is connected with the negative end of a common power supply;
the second beta-helper circuit further comprises a PNP tube P5 and an NPN tube N4, wherein an emitter of the PNP tube P5 is connected with an emitter of the NPN tube N4, a base of the current sink input side NPN tube N1 and a base of the current sink output side NPN tube, a collector of the PNP tube P5 is connected with a negative end of a public power supply, and a base of the PNP tube P5 is connected with an emitter of the NPN tube N2; the base electrode of the NPN pipe N4 is connected with the emitting electrode of the common PNP triode, and the collector electrode of the NPN pipe N4 is connected with the positive end of the common power supply.
Optionally, the bias current sources I1 and I2 include current mirror structures, and are supplied with currents by the current mirror structures.
Alternatively, the output of the current mirror structure of the bias current source I2 acts as a mirror current source of the current mirror structure of the bias current source I1.
Optionally, the current mirror structure of the bias current source I1 comprises a wilson current mirror structure.
Optionally, the number of the current source output side PNP transistors and the current sink output side NPN transistors is plural.
Compared with the prior art, the invention has the following beneficial effects:
the invention is based on a base compensation technology and a beta-helper technology, combines technical innovations of bidirectional self-bias, cascade complementary emitter following, device function multiplexing and the like, and organically integrates precision improvement and low-voltage work matching. The first base current compensation circuit is used for reducing the current shunt of the current source I2 at the collector of a PNP tube P1 on the current source input side, the second base current compensation circuit is used for reducing the current shunt of the current source I1 at the collector of an NPN tube N1 on the current sink input side, the precision of a current mirror is improved, meanwhile, the emitter current of a first emitter follower in the first base current compensation circuit is used as the current source of the second base current compensation circuit, the emitter current of the second emitter follower in the second base current compensation circuit is used as the current source of the first base current compensation circuit, so that bias currents are mutually provided, no additional bias circuit is needed, and the requirement of multiple external bias matching precisions is avoided; the requirement of the working voltage of the circuit is reduced by the cascade complementary following of the shared PNP triode and the NPN tube N4 and the shared NPN triode and the PNP tube P4.
Drawings
FIG. 1 is a diagram of a basic current mirror circuit in the prior art;
FIG. 2 is a prior art current mirror structure with a beta-helper;
FIG. 3 is a prior art current mirror circuit with two stages of beta-helper;
FIG. 4 is a diagram of a prior art current mirror circuit with base current compensation;
FIG. 5 is a diagram of a prior art current mirror circuit with base current compensation and two stages of β -helper;
FIG. 6 is a diagram of a current mirror circuit for simultaneous base current compensation and two-stage β -helper, cascaded complementary emitter follower and bi-directional self-bias improvement in accordance with the present invention;
FIG. 7 is a schematic illustration of the structure of FIG. 6 according to the present invention;
FIG. 8 is a diagram of a current mirror circuit according to another embodiment of the present invention shown in FIG. 6;
FIG. 9 is a schematic diagram of the structure of FIG. 8 of the present invention.
The reference numbers illustrate:
100. a PNP pipe P1 at the current source input side; 110. a first base current compensation circuit; 120. a first beta-helper circuit; 130. PNP tube at output side of current source; 200. a current sink input side NPN tube N1; 210. a second base current compensation circuit; 220. a second beta-helper circuit; 230. an NPN tube at the output side of the current sink; 300. a current mirror; 310. a wilson current mirror.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the objects, technical solutions and beneficial effects of the present invention more clearly understood, the technical solutions of the present invention are further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The symbols designed in all formulas of the invention are illustrated as follows:
I X the dc current sources are indicated, the numbers following them indicating the serial numbers of the dc current sources. I is PXX The current at a port of a PNP device is shown, where I represents the current symbol, P in the subscript PXX represents the PNP bipolar transistor symbol, the first X represents the device number, numbered 1, 2, 3, etc. arabic numerals, and the second X represents the port of the device, C (collector), B (base), and E (emitter), respectively. I is NXX Indicating the current of a certain port of a certain NPN device, wherein I represents the current symbol, and N in subscript NXX is shown inThe NPN bipolar transistor symbol is shown, the first X representing the device number, numbered 1, 2, 3, etc., arabic numerals, and the second X representing the device ports, C (collector), B (base), and E (emitter), respectively. V BEPX The BE junction voltage of a PNP device is shown, wherein V represents the current sign, BE in subscript BEPXX represents the BE junction, P represents the PNP bipolar transistor sign, and X represents the device number, and the numbers are Arabic numerals 1, 2, 3, etc. V BENX The BE junction voltage of a PNP device is shown, wherein V represents a current symbol, BE in subscript BENXX represents a BE junction, N represents an NPN bipolar transistor symbol, and X represents a device number, and the numbers are Arabic numerals 1, 2, 3, and the like. K XXXX Representing the ratio of the emitter areas of two bipolar transistor devices, wherein the first and third X represent the device type, P or N respectively; the second and the fourth X represent the device numbers and are Arabic numerals 1, 2, 3, etc. V RX The voltage across a certain resistance element is shown, wherein V represents a voltage symbol, R represents a resistance symbol, and X represents an element number, which is an Arabic number 1, 2, 3, etc.
Referring to fig. 1, when the current source I1 and the current source I2 have the same size, that is, I1 is equal to I2, the current source I1 is mirrored to a current sink output side NPN transistor NS (hereinafter abbreviated as NS) by an NPN transistor N1, and the current source I2 is mirrored to a current source output side PNP transistor PS (hereinafter abbreviated as PS) by a PNP transistor P1. If PS and NS are precisely matched, their mirror proportions are the same, the collector currents of the NS and PS devices are correspondingly equal, the sum of the collector currents of NS is equal to the sum of the collector currents of PS, and when the devices of the same type are highly matched, the error of the mirror mainly comes from two aspects: emitter trace parasitic resistance and base current.
In practice, because the NPN devices N1 and NS are placed at different positions of a chip layout, the lengths of the traces from the emitter of each NPN device to the VEE pin are different, and the resistance values of the parasitic resistors are also different. Since the collector current of the BJT device is very sensitive to the BE junction voltage, the parasitic resistance of the emitter trace has a great influence on the image accuracy. The same applies to the PNP devices P1 and PS;
setting N1 toThe mirror ratio of the NS group is 1 to K, and the common emitter current gain of NPN is beta N When errors caused by parasitic resistance of emitter wiring are ignored, there are
I 1 ＝I N1C +I N1B +I NSB
I N1C ＝β N I N1B
I NSC ＝β N I NSB
I NSC ＝KI N1C
Wherein, I N1C Collector current, I, of N1 N1B Is the base current, I, of N1 NSC Is the sum of the collector currents of the NS group, I NSB Is the sum of the base currents of the NS sets. Can be obtained from the above formulas
Since NS and PS are exactly matched, the mirror ratio of P1 to PS is also 1 to K. Common emitter current gain of PNP is set as beta P In the same way, have
I 2 ＝I P1C +I P1B +I PSB
I P1C ＝β P I P1B
I PSC ＝β P I PSB
I PSC ＝KI P1C
Wherein, I P1C Is the collector current, I, of P1 P1B Is the base current, I, of P1 PSC Is the sum of the collector currents of the PS group, I PSB Is the sum of the base currents of the NP group.
Since I1 ═ I2, can be obtained
And because the current amplification factor is usually far larger than the mirror image multiple K, the current amplification factor can be obtained according to the Meglan formula
Then the relative error based on the reference is (I) PSC ≠0)
The current amplification factors of the NPN and the PNP cannot be perfectly matched in the process, and the relative error of the current amplification factor of the NPN with respect to the current amplification factor of the PNP is δ, that is, δ
β N ＝(1+δ)β P
Then
It can be seen that if δ is small, the relative error of the NS and PS output currents is proportional to δ, and the larger the mirror factor K or the smaller the current amplification factor, the larger ERR.
Referring to fig. 2, in order to increase the mirror image precision, in the conventional scheme, R1 is matched with the resistors in the NS by a mirror image multiple, R2 is matched with the resistors in the PS by a mirror image multiple, and these resistors are collectively referred to as emitter degeneration resistors, and the organization of setting the emitter degeneration resistors can effectively reduce the mirror image error caused by the parasitic resistance of the emitter trace.
The NPN transistor N2 and the PNP transistor P2 are used for reducing the influence of base current on image error, the structure is called beta-helper, and I is enabled to be I due to the current gains of the NPN transistor N2 and the PNP transistor P2 1 And I 2 The current shunted through the base is reduced, thereby increasing accuracy.
The current relationships in this structure are updated as follows:
I 1 ＝I N1C +I N2B
I N1C ＝β N I N1B
I NSC ＝β N I NSB
I NSB +I N1B ＝(β N +1)I N2B
I NSC ＝KI N1C
I 2 ＝I P1C +I P2B
I P1C ＝β P I P1B
I PSC ＝β P I PSB
I PSB +I P1B ＝(β P +1)I P2B
I PSC ＝KI P1C
can obtain
Then with I PSC The relative error of the reference is (I) PSC ≠0)
Because the current amplification factor of the BJT is much greater than 1, the BJT has a current amplification factor of 1
It can be seen that ERR is greatly reduced, but still a perfect match cannot be achieved, and the relationship of ERR being larger for larger K, larger for smaller BJT current gain, larger for larger δ when δ is small still exists, e.g. 1+ δ ≈ 1, 2+ δ ≈ 2 when δ is small, so ERR is proportional to δ.
Since the emitter current of N2 is equal to the sum of the base currents of NPN transistor N1 and NS, and the emitter current of PNP transistor P2 is equal to the sum of the base currents of P1 and PS, the bias currents of NPN transistor N2 and PNP transistor P2 are low, and the current amplification coefficients of NPN transistor N2 and PNP transistor P2 are attenuated due to the low currents, thereby introducing additional errors.
Referring to fig. 3, in order to further optimize the mirror image accuracy based on fig. 2, two stages of β -helper are used to further reduce the current value of I1 and I2 shunted through the base, so as to improve the amplification effect of the two stages of BJT current gains, at this time, the base currents of NPN transistor N20 and PNP transistor P20 are already very small, but two problems still exist, the first is that the bias currents of NPN transistor N20 and PNP transistor P20 are further reduced, so that the current gain is further attenuated, and the base currents are still difficult to be reduced to the expected values, which causes the problem of final mirror image matching; secondly, the structure is difficult to work under extremely low voltage;
for example, I1 adopts a structure with minimum consumption voltage margin, i.e. a current mirror in a cascode configuration without emitter degeneration resistor, and if it works in the amplification region, it is required that the CE junction voltage is not less than the BE junction voltage V BEI1 . Let the BE junction voltages of N1, N2, and N20 BE V respectively BEN1 、V BEN2 、V BEN20 When the voltage drop across the resistor R1 is VR1, the minimum power supply voltage is V BEI1 +V BEN1 +V BEN2 +V BEN20 +V R1 . Since the BE junction voltage of BJT is usually greater than 0.7V under normal operation, the minimum operating voltage must BE greater than 2.8V, making it difficult to operate the chip at lower voltage.
Referring to fig. 4, in order to further solve the problem of current accuracy between bases based on fig. 3, the base currents in opposite directions are used to compensate each other, and further solve the problem of mirror image matching, I1, I2, I3, and I4 are current sources, where I1 and I2 are matching current signals that need to be mirrored, and I1 is I2. I3, I4 are bias currents of P3, N3;
when the base currents of the NPN transistor N2 and the PNP transistor P3 are equal, and the base currents of the NPN transistor N3 and the PNP transistor P2 are equal, then
I 1 ＝I N1C
I NSC ＝KI N1C
I 2 ＝I P1C
I PSC ＝KI P1C
Calculating derivable I NSC ＝KI N1C ＝KI 1 ＝KI 2 ＝KI P1C ＝I PSC 。
Referring to fig. 5, the two-stage β -helper scheme is to use a two-stage cascade emitter follower to further reduce the input base current, and on the basis of the base current compensation circuit, the two-stage β -helper scheme can make the bias currents of NPN and PNP compensated for the base current more matched, and the current gain of the NPN transistor N21 makes I more suitable N21B Relative to I 5 Neglectable, the output current of NS does not affect the matching of the base currents of NPN transistor N2 and PNP transistor P3, therefore the base currents of NPN transistor N2 and PNP transistor P3 can be adjusted by I 3 And I 5 To achieve matching. Due to I 3 And I 5 The current is not extremely small, so that the NPN transistor N2 and the PNP transistor P3 can operate at an optimum operating point. Can obtain at higher precision
I NSC ＝KI 1
Similarly, can obtain under higher precision
I PSC ＝KI 2
It can be seen that the two-stage β -helper scheme further solves the problem of image matching in conjunction with base current compensation.
Referring to fig. 6 and 7, in order to meet the requirements of low voltage operation, while avoiding the need for more bias circuits to achieve stable voltage or current supply;
the invention provides a bidirectional self-bias bipolar current mirror circuit adapting to low-voltage work, which comprises: a current source current mirror circuit and a current sink current mirror circuit; the current source current mirror circuit and the current sink current mirror circuit both use a public power supply positive end and a public power supply negative end as power supply connection ends;
the current source current mirror circuit comprises a current source input side PNP tube P1(100), a first base current compensation circuit (110), a first beta-helper circuit (120), a current source output side PNP tube (130) and a bias current source I2;
the bias current source I2 supplies collector current of a PNP tube P1(100) at the input side of the current source;
the first base current compensation circuit (110) is used for reducing the current shunt of a collector (100) of a PNP tube P1 on the input side of a bias current source I2; wherein the first base current compensation circuit (110) comprises a first emitter follower whose emitter current is used to provide a bias current for the second base current compensation circuit (210);
the current sink current mirror circuit comprises a current sink input side NPN transistor N1(200), a second base current compensation circuit (210), a second beta-helper circuit (220), a current sink output side NPN transistor (230) and a bias current source I1;
the bias current source I1 supplies collector current of a current sink input side NPN tube N1 (200);
the second base current compensation circuit (210) is used for reducing the current shunt of the collector of the bias current source I1 on the current sink input side NPN tube N1 (200); wherein the second base current compensation circuit (210) comprises a second emitter follower, the emitter current of the second emitter follower being used to provide a bias current for the first base current compensation circuit (110).
In one embodiment of the invention, on the basis of adopting a two-stage beta-helper and basic current compensation scheme in the prior art, a bidirectional self-biasing structure is further adopted to avoid an additional biasing circuit;
the bases of an NPN tube N3 and a PNP tube P2 in the first base current compensation circuit (110) are connected with the collector of a current source input side PNP tube P1(100) for jointly reducing the current shunt of the current source I2 at the collector of the current source input side PNP tube P1(100), and the bases of an NPN tube N2 and a PNP tube P3 in the second base current compensation circuit (210) are connected with the collector of a current sink input side NPN tube N1(200) for jointly reducing the current shunt of the current source I1 at the collector of a current sink input side NPN tube N1(200), and the effect is shown in FIG. 4;
the NPN transistor N3 is used as a shared NPN triode in the first beta-helper circuit (120) and the first base current compensation circuit (110);
the PNP pipe P3 is used as a shared PNP triode in the second beta-helper circuit (220) and the second base current compensation circuit (210).
The bidirectional self-bias adopts the collector current of the PNP tube P2 of the first emitter follower to provide bias current for the common PNP tube P3; the collector of the second emitter follower NPN transistor N2 provides bias current for the common NPN transistor N3, and the magnitude of the bias current is provided by an internal feedback circuit, and the PNP transistor P2 and the PNP transistor P3, the NPN transistor N2 and the NPN crown N3 provide up and down current for each other, instead of the current source I3, the current source I4, the current source I5 and the current source I6 in fig. 5, so that the circuit structure is simplified, and the fact that no additional bias circuit is required is realized.
The NPN tube N3, the PNP tube P4, and the NPN tube N5 form a first β -helper circuit (120), the PNP tube P3, the NPN tube N4, and the PNP tube P5 form a second β -helper circuit (220), the NPN tube N3 and the PNP tube P4, and the PNP tube P3 and the NPN tube N4 respectively adopt two-stage β -helper technologies to respectively form complementary cascades, so that collector currents of the NPN tube N2 and the NPN tube N3, and collector currents of the PNP tube P2 and the PNP tube P3 are precisely equal (as shown in fig. 5). Meanwhile, compared with the common cascade of the NPN tube N2 and the NPN tube N21, and the PNP tube P2 and the PNP tube P21 in fig. 5, the NPN tube N3 and the PNP tube P4, and the PNP tube P3 and the NPN tube N4 adopt complementary cascade, and the base of the NPN tube N4 is connected to the emitter of the PNP tube P3, so that VBEs of the NPN tube N4 and the PNP tube P3 are mutually offset, no voltage margin is consumed, and cascade complementary emission is formed, and the NPN tube N3 and the PNP tube P4 are similar. All devices are arranged to work in an amplification region, and the lowest working voltage is as follows:
V BEN1 +V BEN4 +V BEP2 +V R1 +V R4
if collector currents of the NPN tube N2 and the PNP tube P2 are set to be 50 muA, and resistance values of R3 and R4 are set to be 1k omega, the lowest working voltage is calculated to be 2.2V from 0.7V +0.7V +0.7V +0.05+0.05, and the requirement of low-voltage working is met;
further, NPN tube N2, NPN tube N4, PNP tube P3, and PNP tube P5 form a class ab output stage structure (PNP tube P5 objectively forms a class ab output stage structure with NPN tube N4, but does not function as a class ab output stage), PNP tube P5 is mainly used to provide bias current to NPN tube N4, and PNP tube P5 can ensure that when the base current thereof is likely to be small, NPN tube N4 is prevented from being at an optimal operating point, and at the same time, has a negative feedback function, and if there is no PNP tube P5, if the base of NPN tube N2 is higher, and the emitter of PNP tube P3 is not changed, the current of NPN tube N2 increases, and the current of PNP tube P3 decreases, but the whole is still stable, so that the currents of NPN tube N2 and PNP tube P3 are not ensured to be equal; by arranging the PNP tube P5, the increase of the current of the NPN tube N2 can cause the base electrode of the PNP tube P5 to rise, so that the base electrode of the NPN tube N1 can rise, the base electrode of the NPN tube N2 is pulled down, negative feedback is formed, and the current of the N2 is equal to that of the P3.
NPN tube N3, NPN tube N5, PNP tube P2, and PNP tube P4 form a structure of class ab output stage (the effect of NPN tube N5 and PNP tube P4 are as described above, and they do not function as class ab output stage as well), and the structure of class ab output stage makes BE junction voltages of related devices balanced with each other, that is, satisfies the relational expressions VBEN2+ VBEP3 ═ VBEN4+ VBEP5 and VBEN3+ VBEP2 ═ VBEN5+ VBEP 4. Further, the currents of the NPN transistor N2, the NPN transistor N4, the PNP transistor P3, and the PNP transistor P5 can be matched, and the currents of the NPN transistor N3, the NPN transistor N5, the PNP transistor P2, and the PNP transistor P4 can be matched.
Setting the resistance ratio of R1 and R3 to K N1N2 Then, then
I N2C ＝K N1N2 I N1C
Setting the resistance ratio of R2 and R4 to K P1P2 Then, then
I P2C ＝K P1P2 I P1C
It can be seen that collector currents of the NPN transistor N2, the NPN transistor N3, the PNP transistor P3, and the PNP transistor P2 are matched.
Setting device parameters to K N4N2 ＝K P5P3 ，K N5N3 ＝K P4P2 Then, then
I N4C ＝I P5C ＝I N5C ＝I P4C ＝K N4N2 I N2C ＝K P1P2 I P1C
The bases of the NS and the PS are both driven by an emitter follower (respectively driven by the complementary output stages of the NPN transistor N4 and the PNP transistor P5, and the complementary output stages of the PNP transistor P4 and the NPN transistor N5), so that the starting time is fast, and the driving capability is not generated;
the collector voltage of the NPN transistor N1 is only VBEN2+ VR3, so that I1 can be preferably implemented by using a cascode structure, and the applicability of the circuit at low voltage is not affected. Similarly, I2 can be preferably implemented by using a cascode structure, and does not affect the applicability of the circuit at low voltage. The working voltage of the front-stage current source can be as low as VCC-0.75V, and the working voltage of the front-stage current sink can be as high as VEE + 0.75V.
Referring to fig. 8 and 9, another embodiment of the present invention uses a current source IREF and a wilson current mirror (310) with higher output resistance to output a precise mirror current; the NPN transistor N6, the NPN transistor N7, the NPN transistor N8, the resistor R5, the resistor R6, and the resistor R7 form a current mirror (300), and since the circuit includes only one reference current source IREF, and the current source is outputted as a one-to-one mirror image through the NPN transistor N7 and the NPN transistor N8, although IREF and I are outputted as a one-to-one mirror image N7C 、I N8C There is a difference, however, that N7C 、I N8C Are closely matched with each other; the PNP transistor P6, the PNP transistor P7, and the PNP transistor P8 form a wilson current mirror (310), the collector current of the PNP transistor P8 corresponds to the current source I1 in fig. 6, the collector current of the NPN transistor N8 corresponds to the current source I2 in fig. 6, and since the collector current of the NPN transistor N8 and the current of the PNP transistor P8 are strictly matched, the current of the PS collector and the current of the NS collector are also strictly matched, and the rest of the structure is the same as that in fig. 6, and the technical effects produced by the structure are also the same, and thus are not repeated.
The number of the PNP tubes (130) on the current source output side and the NPN tubes (230) on the current sink output side can be set to be multiple according to the load, and the mirror image error caused by the parasitic resistance of the emitter wiring is solved by arranging the emitter negative feedback resistor in the manner shown in FIG. 2.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (10)
1. A bi-directional self-biased bipolar current mirror circuit adapted for low voltage operation, comprising: a current source current mirror circuit and a current sink current mirror circuit; the current source current mirror circuit and the current sink current mirror circuit both use a public power supply positive end and a public power supply negative end as power supply connection ends;
the current source current mirror circuit comprises a current source input side PNP tube P1, a first base electrode current compensation circuit, a first beta-helper circuit, a current source output side PNP tube and a bias current source I2;
the bias current source I2 supplies collector current of a PNP tube P1 at the input side of the current source;
the first base current compensation circuit is used for reducing the current shunt of the collector of a PNP tube P1 on the input side of the bias current source I2; wherein the first base current compensation circuit comprises a first emitter follower, an emitter current of the first emitter follower is used for providing a bias current for the second base current compensation circuit;
the current sink current mirror circuit comprises a current sink input side NPN tube N1, a second base current compensation circuit, a second beta-helper circuit, a current sink output side NPN tube and a bias current source I1;
the bias current source I1 supplies collector current of a current sink input side NPN tube N1;
the second base current compensation circuit is used for reducing the current shunt of the bias current source I1 at the collector electrode of the current sink input side NPN tube N1; the second base current compensation circuit comprises a second emitter follower, and the emitter current of the second emitter follower is used for providing bias current for the first base current compensation circuit.
2. The bi-directional self-biased bipolar current mirror circuit that accommodates low voltage operation of claim 1,
the first beta-helper circuit and the second beta-helper circuit respectively comprise at least two triodes.
3. The bi-directional self-biased bipolar current mirror circuit of claim 2, wherein the first β -helper circuit and the first base current compensation circuit comprise a common NPN transistor;
the second beta-helper circuit and the second base current compensation circuit comprise a common PNP transistor.
4. The bi-directional self-biased bipolar current mirror circuit for accommodating low voltage operation of claim 3,
the working tube of the first emitter follower in the first base current compensation circuit is a PNP tube P2, the first emitter follower is used as a bias current source I3, and the emitter of the common PNP triode is provided with bias current through the collector of the PNP tube P2;
the working tube of the second emitter follower in the second base current compensation circuit is an NPN tube N2, the second emitter follower is used as a bias current source I4, and bias current is provided for the emitter of the common NPN triode through the collector of the NPN tube N2.
5. The bi-directional self-biased bipolar current mirror circuit according to claim 4, wherein said PNP transistor P2 has its emitter connected to the positive terminal of the common power supply via a resistor R4, and the PNP transistor P2 has its collector connected to the emitter of the common PNP transistor; the collector of the shared PNP triode is connected with the negative end of the common power supply; the base electrode of the PNP tube P2 and the base electrode of the common NPN triode are connected with the collector electrode of the PNP tube P1 at the current source input side so as to commonly reduce the current shunt of the bias current source I2 at the collector electrode of the PNP tube P1 at the current source input side;
an emitter of the NPN tube N2 is connected with the negative end of a public power supply through a resistor R3, and a collector of the NPN tube N2 is connected with an emitter of the common NPN triode; the collector of the shared NPN triode is connected with the positive end of the common power supply; the base of the NPN transistor N2 and the base of the common PNP transistor are both connected to the collector of the current sink input-side NPN transistor N1 to collectively reduce current shunting of the bias current source I1 at the collector of the current sink input-side NPN transistor N1.
6. The bi-directional self-biased bipolar current mirror circuit that accommodates low voltage operation of claim 5,
the first beta-helper circuit further comprises an NPN tube N5 and a PNP tube P4, wherein an emitter of the NPN tube N5 is connected with an emitter of the PNP tube P4, a base of the PNP tube P1 on the current source input side and a base of the PNP tube on the current source output side, a collector of the NPN tube N5 is connected with the positive end of a public power supply, and a base of the PNP tube P2 is connected with an emitter of the PNP tube; the base electrode of the PNP pipe P4 is connected with the emitter electrode of the common NPN triode, and the collector electrode of the PNP pipe P4 is connected with the negative end of a common power supply;
the second beta-helper circuit further comprises a PNP tube P5 and an NPN tube N4, wherein an emitter of the PNP tube P5 is connected with an emitter of the NPN tube N4, a base of the current sink input side NPN tube N1 and a base of the current sink output side NPN tube, a collector of the PNP tube P5 is connected with a negative end of a public power supply, and a base of the PNP tube P5 is connected with an emitter of the NPN tube N2; the base electrode of the NPN pipe N4 is connected with the emitting electrode of the common PNP triode, and the collector electrode of the NPN pipe N4 is connected with the positive end of the common power supply.
7. The bi-directional self-biased bipolar current mirror circuit that accommodates low voltage operation of claim 6,
the bias current source I1 and the bias current source I2 comprise current mirror structures, and the current is supplied by the current mirror structures.
8. The bi-directional self-biased bipolar current mirror circuit according to claim 7, wherein the output of the current mirror structure of the bias current source I2 is used as a mirror current source of the current mirror structure of the bias current source I1.
9. The bi-directional self-biased bipolar current mirror circuit according to claim 7 or 8, wherein the current mirror structure of the bias current source I1 comprises a wilson current mirror structure.
10. The bi-directional self-biased bipolar current mirror circuit according to any one of claims 1 to 8, wherein the number of PNP transistors on the current source output side and NPN transistors on the current sink output side is plural.
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| CN114995576B (en) | 2023-09-15 |
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