CN113745310A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN113745310A
CN113745310A CN202011601435.3A CN202011601435A CN113745310A CN 113745310 A CN113745310 A CN 113745310A CN 202011601435 A CN202011601435 A CN 202011601435A CN 113745310 A CN113745310 A CN 113745310A
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semiconductor region
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semiconductor device
metal layers
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CN113745310B (zh
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谷平圭
堀阳一
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式的半导体装置具备第一电极、连接于所述第一电极的第一导电型的第一半导体区域、设于所述第一半导体区域上并与所述第一半导体区域接触的第二导电型的第二半导体区域、设于所述第二半导体区域上并与所述第二半导体区域接触的多个第一金属层以及多个第二金属层、第三半导体区域、以及第二电极。所述第三半导体区域设于所述第一半导体区域与所述第一金属层之间，与所述第一半导体区域以及所述第二半导体区域接触，为所述第一导电型，杂质浓度比所述第一半导体区域的杂质浓度高。所述第二电极与所述第一半导体区域、所述第二半导体区域、所述第一金属层以及所述第二金属层接触。

Description

半导体装置
相关申请
本申请享受以日本专利申请2020－94936号(申请日：2020年5月29日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的所有内容。
技术领域
实施方式涉及半导体装置。
背景技术
已知有将金属与半导体接合而成的肖特基势垒二极管(Schottky BarrierDiode：SBD)。SBD具有正向的压降少、开关速度高的优点。另一方面，一般构造的SBD在半导体侧耗尽层扩散，电荷(例如电子)产生的电场在金属与半导体的边界面变得最高。因此，开发出混合存在有SBD与pn结二极管的JBS(Junction Barrier Schottky)二极管。JBS二极管将pn二极管包覆于内，从而耗尽层扩散到与半导体表面相比埋入于n－层的一部分的p层与n－层之间。若反向偏置的电压变高，则p层的耗尽层彼此击穿，最大电场移动到p层的正下方。由此，缺陷等较多的表面的电场下降，能够抑制泄漏电流。另外，在构成SBD的n－层的一部分中埋入有p+层的构造中，将由p+层与原始的SBD的n－层形成的pn结二极管包覆于内，在需要高电流(高浪涌电流)的定时导通。由此，电流输送能力提高，抑制大电流时的正向电压的上升且实现高浪涌耐受量。
发明内容
实施方式提供能够提高浪涌耐受量的半导体装置。
实施方式的半导体装置具备第一电极、连接于所述第一电极的第一导电型的第一半导体区域、设于所述第一半导体区域上并与所述第一半导体区域接触的第二导电型的第二半导体区域、设于所述第二半导体区域上并与所述第二半导体区域接触的多个第一金属层以及多个第二金属层、第三半导体区域、以及第二电极。所述第三半导体区域设于所述第一半导体区域与所述第一金属层之间，与所述第一半导体区域以及所述第二半导体区域接触，为所述第一导电型，杂质浓度比所述第一半导体区域的杂质浓度高。所述第二电极与所述第一半导体区域、所述第二半导体区域、所述第一金属层以及所述第二金属层接触。
附图说明
图1是表示第一实施方式的半导体装置的俯视图。
图2是图1所示的A－A'线的剖面图。
图3是表示第二实施方式的半导体装置的俯视图。
图4是图3所示的B－B'线的剖面图。
图5是表示第一比较例的半导体装置的剖面图。
图6是表示第二比较例的半导体装置的剖面图。
图7的(a)是在横轴取正向电压并且在纵轴取正向电流而示出半导体装置的特性的曲线图，(b)是在横轴取逆向电压并且在纵轴取逆向电流而示出半导体装置的特性的曲线图。
具体实施方式
＜第一实施方式＞
首先，对第一实施方式进行说明。
图1是表示本实施方式的半导体装置的俯视图。
图2是图1所示的A－A'线的剖面图。
另外，各图是示意性的，构成要素被适当地强调、简化或者省略。另外，在图之间，构成要素的数量以及尺寸比并不一定一致。对于后述的其他图也相同。
如图1以及图2所示，在本实施方式的半导体装置1中，设有阴极电极10。阴极电极10例如由镍(Ni)等金属构成，配置于半导体装置1的下表面整体。
在阴极电极10上设有半导体部分20。半导体部分20由半导体材料构成，例如由碳化硅(SiC)构成，例如由单晶的SiC构成。如以下所说明，半导体部分20的各部中注入有例如氮(N)等成为施主的杂质、或者例如铝(Al)或硼(B)等成为受主的杂质，形成了若干半导体区域。
在半导体部分20上设有阳极电极30、多个金属层31、多个金属层32、绝缘膜40。
以下，在本说明书中，为了方便说明，采用XYZ正交坐标系。将从阴极电极10朝向阳极电极30的方向设为“Z方向”，将与Z方向正交的两个方向、并且是相互正交的两个方向设为“X方向”以及“Y方向”。另外，也将Z方向中的从阴极电极10朝向阳极电极30的方向称作“上”，将其相反方向称作“下”，但该表述也是为了方便，与重力的方向无关。而且，在以下的说明中，也使用与Z方向正交且与X方向以及Y方向交叉的“W方向”。
如图2所示，在半导体部分20中设有n+型半导体区域21、n－型半导体区域22、多个n型半导体区域23、p型半导体区域26、多个p+型半导体区域27、p－型半导体区域28。之后叙述各半导体区域的平面配置。
n+型半导体区域21例如是导电型为n型的SiC基板。n+型半导体区域21与阴极电极10接触。n－型半导体区域22配置于n+型半导体区域21上。n－型半导体区域22的导电型为n型。n－型半导体区域22的杂质浓度比n+型半导体区域21的杂质浓度低，例如为2×1016(cm－3)左右。n－型半导体区域22经由n+型半导体区域21电连接于阴极电极10。多个n型半导体区域23设于n－型半导体区域22上的一部分。n型半导体区域23的导电型为n型，其杂质浓度比n－型半导体区域22的杂质浓度高。n型半导体区域23的杂质浓度例如为3×1017(cm－3)左右。
p型半导体区域26设于n－型半导体区域22上以及n型半导体区域23上，与n－型半导体区域22以及n型半导体区域23接触。p+型半导体区域27设于p型半导体区域26上，与p型半导体区域26接触。p+型半导体区域27的杂质浓度比p型半导体区域26的杂质浓度高。一部分的p+型半导体区域27设于n型半导体区域23的正上方区域，其他p+型半导体区域27设于离开n型半导体区域23的正上方区域的位置。即，在Z方向上，在一部分的p+型半导体区域27与n－型半导体区域22之间设有n型半导体区域23，在其他p+型半导体区域27与n－型半导体区域22之间未设有n型半导体区域23。p－型半导体区域28设于p型半导体区域26的周围，与p型半导体区域26接触。p－型半导体区域28的杂质浓度比p型半导体区域26的杂质浓度低。p－型半导体区域28与p+型半导体区域27分离。
金属层31设于p+型半导体区域27上并且设于n型半导体区域23的正上方区域，与p+型半导体区域27接触。金属层32设于p+型半导体区域27上并且设于除了n型半导体区域23的正上方区域之外的区域的一部分，与p+型半导体区域27接触。即，在Z方向上，在金属层31与n型层23之间设置一部分的p+型层27，在金属层32与n型层23之间未设有其他p+型层27。金属层31以及32例如由镍(Ni)构成。
绝缘膜40设于半导体部分20上并且设于半导体装置1的终端部。绝缘膜40例如由氧化硅(SiO2)构成。绝缘膜40与n－型半导体区域22、p型半导体区域26、p－型半导体区域28、以及阳极电极30接触。
阳极电极30设于半导体部分20上并且设于除了半导体装置1的终端部之外的部分(以下，称作“单元部”)。半导体装置1的终端部将单元部包围。阳极电极30的周边部攀上绝缘膜40的内侧部上。阳极电极30例如由钛(Ti)构成。阳极电极30与n－型半导体区域22、p型半导体区域26、金属层31、金属层32、以及绝缘膜40接触。另外，上述的p－型层28设于终端部，将设于单元部的各半导体区域的一部分包围。
接下来，对各半导体区域的平面配置进行说明。
图1示出半导体部分20以及金属层32，省略了金属层31、阳极电极30、绝缘膜40。另外，为了易于观看附图，仅对金属层32标注了阴影线。
如图1以及图2所示，从Z方向观察时，n+型半导体区域21以及n－型半导体区域22配置于半导体装置1的整体。如上所述，阳极电极30配置于半导体装置1的单元部，绝缘膜40配置于半导体装置1的终端部，从Z方向观察时，一部分彼此重叠。
金属层31以及金属层32配置于半导体装置1的单元部。从Z方向观察时，各金属层31以及32的形状例如是角部倒圆的正方形或者圆形。但是，金属层31以及32的形状并不限定于此。从Z方向观察时，各金属层31的面积与各金属层32的面积相等。金属层31以及32在XY平面上周期性地排列，例如排列为密排六方状。
具体而言，多个金属层31构成了多个沿X方向周期性地排列的第一列，多个金属层32构成了多个沿X方向周期性地排列的第二列。而且，由金属层31构成的第一列和由金属层32构成的第二列沿Y方向交替地且周期性地排列。
另外，多个金属层31构成了多个也沿Y方向周期性地排列的列，多个金属层32也构成了多个沿Y方向周期性地排列的列。而且，由金属层31构成的沿Y方向延伸的列和由金属层32构成的沿Y方向延伸的列，沿X方向交替地且周期性地排列。
而且，金属层31以及金属层32沿W方向交替地排列。W方向相对于X方向例如倾斜60°，相对于Y方向例如倾斜30°。由此，从Z方向观察时，将多个金属层31以及多个金属层32中的相互最近的三个中心间连结的三角形成为正三角形。
换言之，在沿Y方向延伸的第一列C1与第二列C2上，仅金属层31周期性地配置，未配置有金属层32。沿Y方向延伸且在X方向上位于第一列C1与第二列C2之间的第三列C3上，仅金属层32周期性地配置，未配置有金属层31。而且，在X方向上邻接的第一列C1的金属层31和第二列C2的金属层31之间未配置有金属层32。
p+型半导体区域27配置于金属层31以及32的正下方区域，与金属层31或者32接触。p+型半导体区域27与金属层31以及32欧姆连接。p+型半导体区域27的形状以及大小与金属层31或者32的形状以及大小大致相同。
p型半导体区域26大致配置于半导体装置1的单元部。在p型半导体区域26设有框状部分26a、多个线状部分26b、和多个圆状部分26c。从Z方向观察时，框状部分26a的形状为框状，例如是角部倒圆的长方形或者正方形。框状部分26a沿单元部的外缘配置。
多个线状部分26b配置于框状部分26a内。各线状部分26b的形状是沿Y方向延伸的直线状，其两端部与框状部分26a相连。多个线状部分26b沿X方向周期性地排列。
多个圆状部分26c配置于框状部分26a内。圆状部分26c与多个线状部分26b相连。圆状部分26c配置于p+型半导体区域27的正下方区域，因而，配置于金属层31以及32的正下方区域。圆状部分26c与p+型半导体区域27接触。从Z方向观察时，圆状部分26c的形状以及大小与p+型半导体区域27大致相等。
n型半导体区域23仅设于p型半导体区域26的圆状部分26c的正下方区域并且是金属层31的正下方区域。n型半导体区域23未设于金属层32的正下方区域。因此，多个n型半导体区域23沿X方向以及Y方向周期性地排列。即，多个n型半导体区域23以矩阵状排列。但是，在X方向上相邻的n型半导体区域23间的距离比在Y方向上相邻的n型半导体区域23间的距离短。n型半导体区域23与圆状部分26c接触。
p－型半导体区域28配置于p型半导体区域26的框状部分26a的外侧。p－型半导体区域28的上表面与绝缘膜40接触。但是，p－型半导体区域28未到达半导体装置1的终端边缘。
接下来，对本实施方式的半导体装置1的动作以及效果进行说明。
在半导体装置1中，利用n－型半导体区域22与阳极电极30形成肖特基势垒二极管(SBD)。肖特基势垒二极管的开关速度高，正向的压降少。
由于在阳极电极30连接有p型半导体区域26的线状部分26b，因此在被施加了反向电压时，以n－型半导体区域22与线状部分26b的界面为起点形成耗尽半导体区域。因此，与未设有线状部分26b的情况比较，能够使电场集中的位置转移到比n－型半导体区域22与阳极电极30的界面靠下方的位置。其结果，能够抑制泄漏电流。
阳极电极30经由金属层31以及32、和p+型半导体区域27而欧姆连接于p型半导体区域26。由此，在p型半导体区域26与n－型半导体区域22的接合部分、以及p型半导体区域26与n型半导体区域23的接合部分形成pn二极管。利用pn二极管，能够向正向流过较大的电流，提高电流浪涌耐受量。
由于n型半导体区域23的杂质浓度比n－型半导体区域22的杂质浓度高，因此形成于n型半导体区域23与p型半导体区域26的接合部分的pn二极管相比于形成于n－型半导体区域22与p型半导体区域26的接合部分的pn二极管，耐压更低。因此，在施加了较高的反向电压时，形成于n型半导体区域23与p型半导体区域26的接合部分的pn二极管先击穿而流过电流。由此，能够避免终端部击穿，并能够避免因终端部的击穿而损伤半导体装置1。
而且，在半导体装置1中，n型半导体区域23仅设于金属层31的正下方区域，未设于金属层32的正下方区域。因此，电场集中在形成于金属层31的正下方区域的pn二极管，该pn二极管容易先击穿。由此，能够更可靠地避免终端部的击穿。因而，半导体装置1的电压浪涌耐受量高。
如此，根据本实施方式，能够提高被施加了正向的浪涌电压时的电流浪涌耐受量、以及被施加了反向的浪涌电压时的电压浪涌耐受量这两方。其结果，能够实现浪涌耐受量高的半导体装置1。
＜第二实施方式＞
接下来，对第二实施方式进行说明。
图3是表示本实施方式的半导体装置的俯视图。
图4是图3所示的B－B'线的剖面图。
如图3以及图4所示，本实施方式的半导体装置2与第一实施方式的半导体装置1(参照图1以及图2)比较，金属层31较小，金属层32较大。即，在半导体装置2中，从Z方向观察时，金属层31的面积比金属层32的面积小。在一个例子中，在第一实施方式中，从Z方向观察时，金属层31以及32的直径都为13μm。另一方面，在本实施方式中，金属层31的直径为7μm，金属层32的直径为19μm。
另外，p+型半导体区域27、p型半导体区域26的圆状部分26c以及n型半导体区域23设于金属层31的正下方区域，从Z方向观察时，p+型半导体区域27、圆状部分26c以及n型半导体区域23的形状以及大小与金属层31大致相等。因此，本实施方式的半导体装置2与半导体装置1比较，p+型半导体区域27、圆状部分26c以及n型半导体区域23也较小。
根据本实施方式，通过减小n型半导体区域23，在施加了正向电压时，由n型半导体区域23与p型半导体区域26形成的pn二极管变得更容易导通。推断这是因为pn二极管小型化，使得电场更加集中。其结果，电流浪涌耐受量增加。另外，通过减小n型半导体区域23，在被施加了反向电压时，由n型半导体区域23与p型半导体区域26形成的pn二极管变得更容易击穿。由此，能够在单元部中顺利地进行击穿，能够更可靠地避免终端部的击穿。其结果，电压浪涌耐受量增加。本实施方式中的上述以外的构成、动作以及效果与第一实施方式相同。
＜第一比较例＞
接下来，对第一比较例进行说明。
图5是表示本比较例的半导体装置的剖面图。
如图5所示，本比较例的半导体装置101与第一实施方式的半导体装置1(参照图1以及图2)比较，未设有n型半导体区域23这一点不同。
在半导体装置101中，由于未设有n型半导体区域23，因此pn二极管仅形成于n－型半导体区域22与p型半导体区域26的接合部分。因此，在被施加了反向电压时，pn二极管难以击穿。其结果，在被施加了相反方向的浪涌电压时，单元部中不会顺利地发生击穿，有终端部击穿的可能性。若终端部击穿，则有半导体装置101受到损伤的可能性。
＜第二比较例＞
接下来，对第二比较例进行说明。
图6是表示本比较例的半导体装置的剖面图。
如图6所示，本比较例的半导体装置102与第一实施方式的半导体装置1(参照图1以及图2)比较，不同点是n型半导体区域23设于金属层31的正下方区域与金属层32的正下方区域这两方。
在半导体装置102中，n型半导体区域23设于金属层31的正下方区域与金属层32的正下方区域这两方，因此在被施加了正向的浪涌电压时，电场难以集中，pn二极管难以导通。因此，存在浪涌电流流过终端部而终端部受到损伤的可能性。
＜试验例＞
接下来，对表示上述的实施方式的效果的试验例进行说明。
图7的(a)是在横轴取正向电压并在纵轴取正向电流而示出半导体装置的特性的曲线图，图7的(b)是在横轴取逆向电压并在纵轴取逆向电流而示出半导体装置的特性的曲线图。
如图7的(a)所示，若使向上述的半导体装置施加的正向电压逐渐增加，则首先肖特基势垒二极管导通。若进一步使正向电压增加，则pn二极管导通，传导率产生调制。
在第一实施方式的半导体装置1中产生传导率调制的传导率调制电压vf1比在第二比较例的半导体装置102中产生传导率调制的传导率调制电压vf102低。因而，可以说半导体装置1与半导体装置102相比电流浪涌耐受量更高。另外，在第二实施方式的半导体装置2中产生传导率调制的传导率调制电压vf2比传导率调制电压vf1低。因而，可以说半导体装置2与半导体装置1相比电流浪涌耐受量更高。
如图7的(b)所示，若使向上述的半导体装置施加的逆向电压逐渐增加，则在到达规定的电压时，产生击穿而流过电流。第一实施方式的半导体装置1的击穿电压vb1比第一比较例的半导体装置101的击穿电压vb101低。因而，可以说半导体装置1与半导体装置101相比电流浪涌耐受量更高。另外，第二实施方式的半导体装置2的击穿电压vb2比第一实施方式的半导体装置1的击穿电压vb1低。因而，可以说半导体装置2与半导体装置1相比电压浪涌耐受量更高。
另外，在第一以及第二实施方式中，示出了金属层31以及32排列成密排六方状的例子，但本发明并不限定于此。金属层31以及32也可以按照其他图案排列。另外，金属层31以及32也可以随机地排列。
根据以上说明的实施方式，能够实现浪涌耐受量高的半导体装置。
以上，虽然说明了本发明的几个实施方式，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围、主旨中，并且包含在权利要求书所记载的发明及其等价物的范围内。

Claims (9)

1.一种半导体装置，具备：
第一电极；
第一导电型的第一半导体区域，连接于所述第一电极；
作为第二导电型的第二半导体区域，设于所述第一半导体区域上，与所述第一半导体区域接触；
多个第一金属层以及多个第二金属层，设于所述第二半导体区域上，与所述第二半导体区域接触；
第三半导体区域，设于所述第一半导体区域与所述第一金属层之间，与所述第一半导体区域以及所述第二半导体区域接触，为所述第一导电型，且杂质浓度比所述第一半导体区域的杂质浓度高；以及
第二电极，与所述第一半导体区域、所述第二半导体区域、所述第一金属层以及所述第二金属层接触。
2.根据权利要求1所述的半导体装置，
所述第三半导体区域未设于所述第一半导体区域与所述第二金属层之间。
3.根据权利要求1所述的半导体装置，
从上方观察时，所述第一金属层的面积与所述第二金属层的面积相等。
4.根据权利要求1所述的半导体装置，
从上方观察时，所述第一金属层的面积比所述第二金属层的面积小。
5.根据权利要求1所述的半导体装置，
多个所述第一金属层构成了多个沿第一方向排列的第一列，
多个所述第二金属层构成了多个沿所述第一方向排列的第二列，
所述第一列与所述第二列沿与所述第一方向正交的第二方向交替地排列。
6.根据权利要求5所述的半导体装置，
多个所述第一金属层沿所述第二方向周期性地排列，
多个所述第二金属层沿所述第二方向周期性地排列。
7.根据权利要求5所述的半导体装置，
所述第一金属层以及所述第二金属层沿与所述第一方向以及所述第二方向交叉的第三方向交替地排列。
8.根据权利要求5所述的半导体装置，
所述第二半导体区域具有沿所述第二方向延伸的多个线状部分。
9.根据权利要求1所述的半导体装置，
从上方观察时，将所述多个第一金属层以及所述多个第二金属层中的相互最近的三个金属层的中心间连结的三角形为正三角形。
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