CN114930525A - 一种光电合封集成器件 - Google Patents
一种光电合封集成器件 Download PDFInfo
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- CN114930525A CN114930525A CN202080091874.6A CN202080091874A CN114930525A CN 114930525 A CN114930525 A CN 114930525A CN 202080091874 A CN202080091874 A CN 202080091874A CN 114930525 A CN114930525 A CN 114930525A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
一种光电合封集成器件，PIC(7)和EIC(5)正向贴装在封装基板(2)上，ASIC(3)倒装在封装基板(2)上，PIC通过引线键合与EIC耦合，EIC通过引线键合与封装基板耦合，并通过封装基板与ASIC耦合，从而实现了PIC、EIC与ASIC之间的高频连接。PIC没有采用倒装，不需要开发TSV工艺，通过引线键合方式与EIC实现耦合，解决了目前包含PIC的光电合封集成器件成品率较低的技术问题。
Description
PCT国内申请，说明书已公开。
Claims (12)
- PCT国内申请，权利要求书已公开。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/082366 WO2021195942A1 (zh) | 2020-03-31 | 2020-03-31 | 一种光电合封集成器件 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114930525A true CN114930525A (zh) | 2022-08-19 |
| CN114930525B CN114930525B (zh) | 2024-05-03 |
Family
ID=77927335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080091874.6A Active CN114930525B (zh) | 2020-03-31 | 2020-03-31 | 一种光电合封集成器件 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114930525B (zh) |
| WO (1) | WO2021195942A1 (zh) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116264223A (zh) * | 2021-12-14 | 2023-06-16 | 中兴通讯股份有限公司 | 芯片封装结构及其光电设备 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130308898A1 (en) * | 2012-04-26 | 2013-11-21 | Acacia Communications Inc. | Co-packaging photonic integrated circuits and application specific integrated circuits |
| US20160124164A1 (en) * | 2014-10-29 | 2016-05-05 | Acacia Communications, Inc. | Optoelectronic ball grid array package with fiber |
| CN208256644U (zh) * | 2017-04-14 | 2018-12-18 | 谷歌有限责任公司 | 用于高数据速率的硅光子ic的集成 |
| CN110235039A (zh) * | 2017-01-06 | 2019-09-13 | 洛克利光子有限公司 | Asic与硅光子器件的共同封装 |
| CN110718593A (zh) * | 2018-06-27 | 2020-01-21 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7081667B2 (en) * | 2004-09-24 | 2006-07-25 | Gelcore, Llc | Power LED package |
| US10037982B2 (en) * | 2016-01-04 | 2018-07-31 | Infinera Corporation | Photonic integrated circuit package |
| US11043478B2 (en) * | 2018-04-24 | 2021-06-22 | Cisco Technology, Inc. | Integrated circuit bridge for photonics and electrical chip integration |
-
2020
- 2020-03-31 CN CN202080091874.6A patent/CN114930525B/zh active Active
- 2020-03-31 WO PCT/CN2020/082366 patent/WO2021195942A1/zh active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130308898A1 (en) * | 2012-04-26 | 2013-11-21 | Acacia Communications Inc. | Co-packaging photonic integrated circuits and application specific integrated circuits |
| US20160124164A1 (en) * | 2014-10-29 | 2016-05-05 | Acacia Communications, Inc. | Optoelectronic ball grid array package with fiber |
| CN110235039A (zh) * | 2017-01-06 | 2019-09-13 | 洛克利光子有限公司 | Asic与硅光子器件的共同封装 |
| CN208256644U (zh) * | 2017-04-14 | 2018-12-18 | 谷歌有限责任公司 | 用于高数据速率的硅光子ic的集成 |
| CN110718593A (zh) * | 2018-06-27 | 2020-01-21 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114930525B (zh) | 2024-05-03 |
| WO2021195942A1 (zh) | 2021-10-07 |
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