CN114899196A - Phase inverter based on IGZO thin film transistor and preparation method thereof - Google Patents
Phase inverter based on IGZO thin film transistor and preparation method thereof Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
The invention provides an IGZO thin film transistor-based inverter and a preparation method thereof, wherein the method comprises the following steps: obtaining a substrate; forming a gate electrode layer over a substrate; forming a gate dielectric layer on the gate electrode layer; forming an IGZO active layer on the gate dielectric layer; forming a source electrode and a drain electrode on the IGZO active layer; and carrying out local hydrogen plasma treatment on the IGZO active layer. Hydrogen doping is achieved through a hydrogen plasma processing technology, so that an n-type enhancement type IGZO thin film transistor in a pull-up network of the phase inverter is converted into an n-type depletion type IGZO thin film transistor, and compared with the phase inverter with the n-type enhancement type IGZO thin film transistor with a short-circuited gate and drain as a pull-up device, the phase inverter provided by the invention has higher gain and larger swing amplitude; meanwhile, the process is simple and quick, is convenient to operate, and the gas source used for reaction is easy to obtain, so that the demand of large-scale industrial production is met.
Description
Technical Field
The invention relates to the technical field of electronic devices and preparation thereof, in particular to an IGZO thin film transistor-based inverter and a preparation method thereof.
Background
Flexible electronics is a new electronic technology for manufacturing electronic devices such as metal oxides, organic materials, carbon nanotubes and the like on flexible and ductile substrates, and has attracted extensive attention in academia and industry. Since conventional silicon-based devices are not "flexible," metal oxide thin film transistors are the most promising alternative. Besides good flexibility, the metal oxide thin film transistor also has the advantages of higher mobility, lower preparation temperature and the like. Indium Gallium Zinc Oxide (IGZO) is a mainstream active layer material in the current metal oxide thin film transistor, has the advantages of high mobility, low off-state current, wide band gap (about 3.5eV), and the like, and is an ideal semiconductor material for preparing flexible electronic products.
The stable and reliable inverter is the basis for realizing a high-performance digital circuit and an analog circuit, so that the inverter prepared by using the IGZO thin film transistor is a crucial step in the process of realizing a flexible circuit and a product. The traditional silicon-based inverter adopts a CMOS structure with an n-tube as a pull-down network and a p-tube as a pull-up network, however, most IGZO thin film transistors are n-type reinforced tubes, and the p-type IGZO thin film transistors with good performance are difficult to manufacture by the current process and preparation flow, so that the CMOS structure is not suitable any more.
At present, an n-type enhancement type IGZO thin film transistor with a short-circuited gate and drain is usually used as a pull-up device to prepare an inverter, but the inverter with the structure has the defects of low voltage gain, small output swing and the like. In order to improve the performance of an IGZO thin film transistor-based inverter, a method widely adopted at present is to use an n-type depletion IGZO thin film transistor with a short-circuited gate source as a pull-up device and an n-type enhancement IGZO thin film transistor as a pull-down device. At present, the main methods for realizing the n-type depletion type IGZO thin film transistor include: the threshold of the transistor is dynamically controlled by adopting a double-gate structure, and the type of the transistor is changed by processes of laser annealing or depositing a plurality of active layers and the like. However, the dual-gate structure needs an additional top gate control circuit, which increases the complexity of circuit design and is not easy to implement; the laser annealing and the multiple active layers can make the process too complicated and cumbersome.
Therefore, it is necessary to provide an IGZO thin film transistor-based inverter and a method for manufacturing the same, so as to implement a high-gain and full-swing inverter and simplify circuit design and process flow.
Disclosure of Invention
In order to solve the above problems, the present invention provides an inverter and a method for manufacturing the same: forming a normally-open channel through a hydrogen plasma treatment process, so that an n-type enhancement type IGZO thin film transistor in a pull-up network is converted into an n-type depletion type IGZO thin film transistor, and compared with a phase inverter which takes the n-type enhancement type IGZO thin film transistor with a short-circuited gate drain as a pull-up device, the n-type depletion type IGZO thin film transistor with a short-circuited gate source as the phase inverter of the pull-up device has higher gain and larger swing amplitude; meanwhile, the process is simple and quick, is convenient to operate, and the gas source used for reaction is easy to obtain, so that the demand of large-scale industrial production is met.
In order to achieve the purpose, the invention adopts the following technical scheme:
the IGZO thin film transistor-based inverter comprises an n-type enhancement type IGZO thin film transistor T1 and an n-type depletion type IGZO thin film transistor T2, wherein the n-type depletion type IGZO thin film transistor T2 serves as a pull-up device;
the n-type enhancement IGZO thin film transistor T1 comprises a substrate, a first gate electrode layer, a first gate dielectric layer and a first IGZO active layer which are sequentially arranged, wherein a first source electrode and a first drain electrode are arranged on the surface of the first IGZO active layer;
the n-type depletion type IGZO thin film transistor T2 comprises a substrate, a second gate electrode layer, a second gate dielectric layer and a second IGZO active layer which are sequentially arranged; a second source electrode and a second drain electrode are arranged on the surface of the second IGZO active layer; the n-type depletion IGZO thin film transistor T2 further comprises an open type channel, the distance between the second source electrode and the second drain electrode is the channel length, and the open type channel is obtained by performing hydrogen plasma treatment on an IGZO active layer corresponding to the region between the second source electrode and the second drain electrode.
The first drain electrode of the n-type enhancement IGZO thin film transistor T1, the second source electrode and the second gate electrode of the n-type depletion IGZO thin film transistor T2 are shorted to V OUT A signal.
Further, the n-type enhancement IGZO thin film transistor T1 and the n-type depletion IGZO thin film transistor T2 share a substrate, which is a rigid substrate or a flexible substrate.
Furthermore, the first gate electrode layer and the second gate electrode layer are arranged on the surface of the substrate and are made of molybdenum.
Further, the first gate dielectric layer completely covers the first gate electrode layer of the transistor T1, the second gate dielectric layer completely covers the second gate electrode layer of the transistor T2, and the first gate dielectric layer and the second gate dielectric layer are made of silicon dioxide. Further, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all molybdenum or aluminum.
The invention discloses a preparation method of an IGZO thin film transistor-based inverter, which comprises the following steps:
step 1, cleaning a substrate, and preparing a patterned gate electrode layer on the substrate; the patterned gate electrode layer includes a first gate electrode layer and a second gate electrode layer.
step 3, forming an IGZO active layer on the grid dielectric layer through a radio frequency magnetron sputtering process, etching the IGZO active layer and a second grid dielectric layer positioned on the surface of a second grid to obtain a patterned IGZO active layer, and forming a window on the second grid dielectric layer to expose part of the second grid; the patterned IGZO active layer comprises a first IGZO active layer and a second IGZO active layer, the first IGZO active layer is positioned on the surface of the first grid dielectric layer, the second IGZO active layer is positioned on the surface of the second grid dielectric layer, and a space exists between the first IGZO active layer and the second IGZO active layer.
And 5, performing hydrogen plasma treatment on the second IGZO active layer positioned between the second source electrode and the second drain electrode to form a normally-open channel, and preparing to obtain the n-type depletion type IGZO thin film transistor T2.
Further, in step 5, the hydrogen plasma treatment process environment is as follows: the reaction power is 100W, the pressure of the chamber is 1200mTorr, the hydrogen flow is 170sccm, the reaction temperature is 30 ℃, and the reaction time is 200 s.
Has the advantages that: the conventional n-type enhancement IGZO thin film transistor adopting the gate-drain short circuit still has the defects of low gain, low swing amplitude and the like when being used as an inverter of a pull-up device. In order to prepare a high-performance phase inverter based on an IGZO thin film transistor, hydrogen doping is realized through a hydrogen plasma treatment process, so that an n-type enhancement type IGZO thin film transistor in a pull-up network is converted into an n-type depletion type IGZO thin film transistor, and compared with a phase inverter which takes the n-type enhancement type IGZO thin film transistor with a short-circuited gate drain as a pull-up device, the phase inverter which takes the n-type depletion tube with a short-circuited gate source as the pull-up device has higher gain and larger swing amplitude; meanwhile, the process is simple and quick, is convenient to operate, and the gas source used for reaction is easy to obtain, so that the demand of large-scale industrial production is met.
Drawings
In order to more clearly and concisely illustrate embodiments of the present invention, a number of figures are provided. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIG. 1 is a circuit diagram of a TFT-based inverter according to an embodiment of the present invention
FIG. 2 is a schematic diagram of an embodiment of a TFT-based inverter;
FIG. 3 is a flow chart of a method for fabricating a thin film transistor based inverter according to one embodiment;
fig. 4 is a graph of voltage transfer characteristics for an embodiment of the present invention.
110, a substrate; 120. a first gate electrode layer; 130 a first gate dielectric layer; 140. a first IGZO active layer; 150. a first source electrode; 152. a first drain electrode;
121. a second gate electrode layer; 131, a second gate dielectric layer; 141. a second IGZO active layer; 151. a second source electrode; 153. a second drain electrode; 142. an open channel.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings.
An embodiment of the invention is given in figure 2. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these examples are provided so that the reader will understand the disclosure more fully. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The currently common method for preparing the inverter based on the IGZO thin film transistor is to use an n-type enhancement type IGZO thin film transistor with a short-circuited gate and drain as a pull-up device and an n-type enhancement type IGZO thin film transistor as a pull-down device to form the inverter. In order to prepare the high-performance inverter based on the IGZO thin film transistor, hydrogen doping is realized through a hydrogen plasma treatment process, so that the n-type enhancement type IGZO thin film transistor in the pull-up network is converted into an n-type depletion type IGZO thin film transistor. Compared with an inverter taking an n-type enhancement type IGZO thin film transistor with a short-circuited gate drain as a pull-up device, the inverter taking the n-type depletion type IGZO thin film transistor with a short-circuited gate source as the pull-up device has higher gain and larger swing amplitude; meanwhile, the process is simple and quick, is convenient to operate, and the gas source used for reaction is easy to obtain, so that the demand of large-scale industrial production is met.
An IGZO thin film transistor based inverter includes an n-type enhancement IGZO thin film transistor T1 and an n-type depletion IGZO thin film transistor T2, wherein the n-type depletion IGZO thin film transistor T2 is used as a pull-up device;
as shown in fig. 2, the n-type enhancement IGZO thin film transistor T1 includes a substrate 110, a first gate electrode layer 120, a first gate dielectric layer 130, and a first IGZO active layer 140 in this order, and a first source electrode 150 and a first drain electrode 152 are disposed on a surface of the first IGZO active layer 140;
the n-type depletion type IGZO thin film transistor T2 includes a substrate 110, a second gate electrode layer 121, a second gate dielectric layer 131, and a second IGZO active layer 141 in this order; a second source electrode 151 and a second drain electrode 153 are arranged on the surface of the second IGZO active layer 141; the n-type enhancement-type IGZO thin film transistor T1 and the n-type depletion-type IGZO thin film transistor T2 share the substrate 110, and the first gate electrode layer 120 and the second gate electrode layer 121 are both arranged on the surface of the substrate 110 and are made of molybdenum. The n-type depletion IGZO thin film transistor T2 further includes an open channel 142, and the open channel 142 is obtained by performing a hydrogen plasma treatment on an IGZO active layer corresponding to a region between the second source electrode 151 and the second drain electrode 153.
Referring to fig. 1, which is a circuit diagram of an embodiment of the present invention, a first gate electrode layer 120 of an n-type enhancement IGZO thin film transistor T1 is used as an input electrode and connected to V IN A signal; the first source 150 of the n-type enhancement IGZO thin film transistor T1 is used as a ground electrode, and is grounded, i.e. connected to 0V; the first drain 152 of the n-type enhancement IGZO TFT T1, the second source 151 of the n-type depletion IGZO TFT T2 and the second gate electrode layer 121 are shorted to serve as output electrodes, and connected to V OUT A signal; the second drain electrode 153 of the n-type depletion IGZO TFT T2 is used as an external power supply electrode and connected to V DD A signal.
The substrate 110 may be a rigid base (e.g., glass) or a flexible base as is known in the art. In the present embodiment, the substrate 110 is a semiconductor substrate, such as a silicon substrate. It should be noted that the dimensions of the individual film layers in fig. 1 are only schematic and do not represent the actual dimensions.
The first gate dielectric layer 130 and the second gate dielectric layer 131 completely cover the gate electrode layer of the transistor T1 and the gate electrode layer of the transistor T2, respectively, and are made of silicon dioxide.
The first source 150, the first drain 152, the second source 151 and the second drain 153 are molybdenum sources, and in other embodiments, other source/drain materials known in the art may be used as the source/drain materials.
In the embodiment shown in fig. 2, the thickness of the gate electrode layer is 100nm, the thickness of the gate dielectric layer is 100nm, the thickness of the source electrode and the drain electrode are both 100nm, and the thickness of the IGZO active layer is 20 nm.
Fig. 3 is a flowchart of a method for manufacturing an IGZO thin film transistor-based inverter according to an embodiment of the present invention, which may be used to manufacture the inverter shown in fig. 2, and includes the following steps:
step 1, cleaning a substrate 110, and preparing a patterned gate electrode layer on the substrate 110;
the substrate 110 may be a rigid base (e.g., glass) or a flexible base as is known in the art. In one embodiment of the present invention, substrate 110 is a semiconductor substrate, such as a silicon/silicon oxide substrate. The substrates 110 were then ultrasonically cleaned for five minutes in the order of deionized water, acetone, absolute ethanol, and deionized water at a power of 100W to obtain substrates 110 for subsequent operations.
The method comprises the steps of carrying out photoresist homogenizing, photoetching, drying, exposing and developing treatment on the surface of a substrate 110 to obtain patterned photoresist, adopting a photoresist remover to treat residual photoresist possibly existing in a pattern area, forming a molybdenum metal layer on the substrate 110 (at the moment, the patterned photoresist exists on the surface of the substrate) by utilizing a magnetron sputtering process, further adopting a lift-off process to obtain a patterned gate electrode layer, and forming a first gate electrode layer 120 and a second gate electrode layer 121. Other materials/structures known in the art may also be used for the gate electrode layer. In this example, a gate electrode layer was prepared to a thickness of 100 nm.
In this embodiment, a gate dielectric layer is covered on the gate electrode layer by a PECVD process, the first gate dielectric layer 130 is located on the surface of the first gate electrode layer 120, the second gate dielectric layer 131 is located on the surface of the second gate electrode layer 121, and the gate dielectric layer is made of silicon dioxide. The PECVD process parameters used in this example are as follows: working pressure 1000mTorr, let in N 2 O and SiH at 5% concentration 4 The ratio of (A) to (B) is 710:170, the power is 100W, and the reaction temperature is 300 ℃. In this example, a gate dielectric layer was prepared with a thickness of 100 nm.
And 3, forming an IGZO active layer on the grid dielectric layer.
In this embodiment, an IGZO active layer is formed on the gate dielectric layer by a rf magnetron sputtering process, and the reaction conditions adopted in this embodiment are as follows: sputtering pressure 0.5Pa, introducing Ar and O 2 The ratio of (1) to (5) is 45:5, the sputtering power is 80W, and the sputtering time duration is 1000 s.
Performing photoresist homogenizing, photoetching, drying, exposing and developing treatment on the surface of the IGZO active layer to obtain patterned photoresist, etching the IGZO active layer and the second grid dielectric layer 131 positioned on the surface of the second grid electrode by adopting diluted hydrofluoric acid (1%), obtaining the patterned IGZO active layer through photoresist removing treatment, and forming a window on the second grid dielectric layer 131 to expose the second grid electrode for short circuit between the second grid electrode and the first drain electrode 152 and the second source electrode 151 in the following step; the patterned IGZO active layer includes a first IGZO active layer 140 and a second IGZO active layer 141, the first IGZO active layer 140 is located on the surface of the first gate dielectric layer 130, the second IGZO active layer 141 is located on the surface of the second gate dielectric layer 131, and an interval exists between the first IGZO active layer 140 and the second IGZO active layer 141, and then an annealing process is performed, wherein the annealing conditions in this embodiment are as follows: the temperature is 350 ℃, the annealing atmosphere is Ar, and the annealing time is 1 h. In this example, the thickness of the IGZO active layer prepared was 20 nm.
And 4, forming a source electrode and a drain electrode on the IGZO active layer.
In this embodiment, an aluminum Al metal layer is covered on the IGZO active layer by an electron beam evaporation process on the surface of the IGZO active layer, a patterned photoresist is obtained on the surface of the Al metal layer through photoresist uniformizing, photolithography, drying, exposure and development, the Al metal layer is etched by using an aluminum Al etching solution (the patterned photoresist exists on the surface of the Al metal layer at this time), and a first source 150 and a first drain 152 are formed on the surface of the first IGZO active layer 140 through photoresist removal, so as to obtain an n-type enhanced IGZO thin film transistor T1; a second source 151 and a second drain 153 are formed on the surface of the second IGZO active layer 141, and the first drain 152, the second source 151, and the second gate electrode are shorted. In other embodiments, other materials known in the art may be used as the source/drain electrode layer. In this embodiment, the thickness of the source and drain electrode layers is 100 nm.
And step 5, performing hydrogen plasma treatment on the second IGZO active layer 141 positioned between the second source electrode 151 and the second drain electrode 153 to form a normally-open channel 142, and thus preparing the n-type depletion IGZO thin film transistor T2.
In this embodiment, a window for doping hydrogen may be obtained on the upper surface of the second IGZO active layer 141 between the second source electrode 151 and the second drain electrode 153 by spin coating, photolithography, exposure, and development, and the normally-open channel 142 is formed by performing hydrogen plasma treatment on the window to obtain the n-type depletion IGZO thin film transistor, where the hydrogen plasma treatment process environment is: the reaction power is 100W, the pressure of the chamber is 1200mTorr, the hydrogen flow is 170sccm, the reaction temperature is 30 ℃, and the reaction time is 200 s.
FIG. 4 is a graph of transfer characteristics of an embodiment of the present invention with the input signal V on the abscissa IN Is the output signal V on the ordinate OUT Of (c) is used. It can be seen that at the supply voltage V DD The inverter gain and swing at 5V are 17.93 and 4.95V, respectively; at a supply voltage V DD The inverter gain and swing at 10V are 49.361 and 9.93V, respectively. The swing of the two supply voltages are connectedNear full amplitude of oscillation, at V DD Compared with an inverter which adopts an n-type enhancement type IGZO thin film transistor with a short circuit of a grid and a drain as a pull-up device, the gain of the inverter reaches 49.361 even when the voltage is 10V, the embodiment provided by the invention has higher gain and larger swing, and the performance is obviously improved.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. An IGZO thin film transistor based inverter comprises an n-type enhancement type IGZO thin film transistor T1 and an n-type depletion type IGZO thin film transistor T2, wherein the n-type depletion type IGZO thin film transistor T2 is used as a pull-up device;
the n-type enhancement IGZO thin film transistor T1 comprises a substrate, a first gate electrode layer, a first gate dielectric layer and a first IGZO active layer which are sequentially arranged, wherein a first source electrode and a first drain electrode are arranged on the surface of the first IGZO active layer;
the n-type depletion type IGZO thin film transistor T2 comprises a substrate, a second gate electrode layer, a second gate dielectric layer and a second IGZO active layer which are sequentially arranged; a second source electrode and a second drain electrode are arranged on the surface of the second IGZO active layer; the n-type depletion IGZO thin film transistor T2 further comprises an open-type channel, wherein the open-type channel is obtained by performing hydrogen plasma treatment on an IGZO active layer corresponding to a region between the second source electrode and the second drain electrode;
the first drain electrode of the n-type enhancement-type IGZO thin film transistor T1 is shorted with the second source electrode and the second gate electrode layer of the n-type depletion-type IGZO thin film transistor T2.
2. The IGZO thin film transistor based inverter as claimed in claim 1, wherein the n-type enhancement IGZO thin film transistor T1 and the n-type depletion IGZO thin film transistor T2 share a substrate, and the substrate is a rigid substrate or a flexible substrate.
3. The IGZO thin film transistor based inverter as claimed in claim 1, wherein the first gate electrode layer and the second gate electrode layer are both disposed on a surface of the substrate and are made of molybdenum.
4. The IGZO thin film transistor based inverter as claimed in claim 1, wherein the first gate dielectric layer completely covers the first gate electrode layer of the transistor T1, the second gate dielectric layer completely covers the second gate electrode layer of the transistor T2, and the first gate dielectric layer and the second gate dielectric layer are made of silicon dioxide.
5. The IGZO thin film transistor based inverter as claimed in claim 1, wherein the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all molybdenum or aluminum.
6. A preparation method of an IGZO thin film transistor-based inverter is characterized by comprising the following steps:
step 1, cleaning a substrate, and preparing a patterned gate electrode layer on the substrate; the patterned gate electrode layer includes a first gate electrode layer and a second gate electrode layer;
step 2, depositing a gate dielectric layer on the substrate with the gate electrode layer through a PECVD process, wherein the first gate dielectric layer is positioned on the surface of the first gate electrode layer, and the second gate dielectric layer is positioned on the surface of the second gate electrode layer;
step 3, forming an IGZO active layer on the grid dielectric layer through a radio frequency magnetron sputtering process, etching the IGZO active layer and a second grid dielectric layer positioned on the surface of a second grid to obtain a patterned IGZO active layer, and forming a window on the second grid dielectric layer to expose part of the second grid; the patterned IGZO active layer comprises a first IGZO active layer and a second IGZO active layer, the first IGZO active layer is positioned on the surface of the first grid dielectric layer, the second IGZO active layer is positioned on the surface of the second grid dielectric layer, and a space exists between the first IGZO active layer and the second IGZO active layer;
step 4, forming a first source electrode and a first drain electrode on the first IGZO active layer through an electron beam evaporation process to obtain an n-type enhanced IGZO thin film transistor T1; forming a second source and a second drain on the surface of the second IGZO active layer, and short-circuiting the first drain, the second source and the second gate electrode;
and 5, performing hydrogen plasma treatment on the second IGZO active layer positioned between the second source electrode and the second drain electrode to form a normally-open channel, and preparing to obtain the n-type depletion type IGZO thin film transistor T2.
7. The method for manufacturing an IGZO thin film transistor based inverter as claimed in claim 6, wherein in step 5, the hydrogen plasma processing environment is: the reaction power is 100W, the pressure of the chamber is 1200mTorr, the hydrogen flow is 170sccm, the reaction temperature is 30 ℃, and the reaction time is 200 s.
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| PCT/CN2022/143244 WO2023241006A1 (en) | 2022-06-14 | 2022-12-29 | Phase inverter based on igzo thin-film transistor, and preparation method therefor |
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| WO2023241006A1 (en) * | 2022-06-14 | 2023-12-21 | 东南大学 | Phase inverter based on igzo thin-film transistor, and preparation method therefor |
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| CN106783624A (en) * | 2016-12-31 | 2017-05-31 | 杭州潮盛科技有限公司 | Transistor threshold voltage adjusting method and phase inverter preparation method |
| US20210074702A1 (en) * | 2017-09-28 | 2021-03-11 | Intel Corporation | Monolithic integration of a thin film transistor over a complimentary transistor |
| CN113078112A (en) * | 2021-03-29 | 2021-07-06 | 电子科技大学 | Preparation method of oxide-based depletion type load inverter |
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| CN102290440A (en) * | 2010-06-21 | 2011-12-21 | 财团法人工业技术研究院 | Transistor and manufacturing method thereof |
| CN103346093B (en) * | 2013-06-13 | 2015-12-23 | 北京大学深圳研究生院 | Top grid self-aligned thin film transistor that source/drain region is raised and preparation method thereof |
| JP6246518B2 (en) * | 2013-07-29 | 2017-12-13 | 株式会社半導体エネルギー研究所 | Transistor |
| CN214588853U (en) * | 2021-02-19 | 2021-11-02 | 深圳市柔宇科技股份有限公司 | CMOS inverter, array substrate and display device |
| CN114899196A (en) * | 2022-06-14 | 2022-08-12 | 东南大学 | Phase inverter based on IGZO thin film transistor and preparation method thereof |
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| CN106783624A (en) * | 2016-12-31 | 2017-05-31 | 杭州潮盛科技有限公司 | Transistor threshold voltage adjusting method and phase inverter preparation method |
| US20210074702A1 (en) * | 2017-09-28 | 2021-03-11 | Intel Corporation | Monolithic integration of a thin film transistor over a complimentary transistor |
| CN113078112A (en) * | 2021-03-29 | 2021-07-06 | 电子科技大学 | Preparation method of oxide-based depletion type load inverter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023241006A1 (en) * | 2022-06-14 | 2023-12-21 | 东南大学 | Phase inverter based on igzo thin-film transistor, and preparation method therefor |
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