WO2023241006A1 - Phase inverter based on igzo thin-film transistor, and preparation method therefor - Google Patents

Phase inverter based on igzo thin-film transistor, and preparation method therefor Download PDF

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WO2023241006A1
WO2023241006A1 PCT/CN2022/143244 CN2022143244W WO2023241006A1 WO 2023241006 A1 WO2023241006 A1 WO 2023241006A1 CN 2022143244 W CN2022143244 W CN 2022143244W WO 2023241006 A1 WO2023241006 A1 WO 2023241006A1
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igzo
film transistor
layer
thin film
type
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Chinese (zh)
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吴汪然
黄庭瑞
俞祚旭
杨光安
孙伟锋
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of electronic devices and their preparation, in particular to an inverter based on an IGZO thin film transistor and its preparation method.
  • Flexible electronics is an emerging electronic technology that manufactures electronic devices such as metal oxides, organic materials, and carbon nanotubes on flexible and ductile substrates. It has attracted widespread attention from academia and industry. Since traditional silicon-based devices cannot be “flexible", metal oxide thin film transistors have become their most promising substitutes. In addition to good flexibility, metal oxide thin film transistors also have the advantages of higher mobility and lower preparation temperature. Indium gallium zinc oxide (IGZO) is currently a mainstream active layer material in metal oxide thin film transistors. It has the advantages of high mobility, low off-state current, and wide bandgap ( ⁇ 3.5eV). It is an ideal semiconductor material for preparing flexible electronic products.
  • IGZO Indium gallium zinc oxide
  • Stable and reliable inverters are the basis for realizing high-performance digital circuits and analog circuits. Therefore, using IGZO thin film transistors to prepare inverters is a crucial step in the process of realizing flexible circuits and products.
  • Traditional silicon-based inverters use a CMOS structure with n-tubes as the pull-down network and p-tubes as the pull-up network.
  • IGZO thin film transistors are n-type enhancement transistors, and it is difficult to manufacture them with good performance using the current technology and preparation process.
  • p-type IGZO thin film transistor so this CMOS structure is no longer applicable.
  • n-type enhancement-type IGZO thin film transistors with gate-to-drain short circuits are usually used as pull-up devices to prepare inverters.
  • inverters with this structure have shortcomings such as low voltage gain and small output swing.
  • the currently widely used method is to use n-type depletion mode IGZO thin film transistors with gate-source short circuits as pull-up devices and n-type enhancement mode IGZO thin film transistors as pull-down devices.
  • the main methods to realize n-type depletion IGZO thin film transistors include: dynamically controlling the threshold of the transistor using a dual-gate structure, changing the type of transistor through processes such as laser annealing or depositing multi-layer active layers.
  • the double-gate structure requires additional top-gate control circuits, which increases the complexity of circuit design and is difficult to implement; methods such as laser annealing and multi-layer active layers will make the process too complex and cumbersome.
  • the present invention provides an inverter and a preparation method thereof: a normally open channel is formed through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is converted into an n-type depletion Type IGZO thin film transistor, compared with the n-type enhancement type IGZO thin film transistor with the gate and drain shorted as the inverter of the pull-up device, the n-type depletion type IGZO thin film transistor with the gate source shorted as the inverter of the pull-up device
  • the phase device has higher gain and larger swing; at the same time, the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
  • An inverter based on IGZO thin film transistors of the present invention includes an n-type enhancement IGZO thin film transistor T1 and an n-type depletion IGZO thin film transistor T2, in which the n-type depletion IGZO thin film transistor T2 serves as a pull-up device;
  • the n-type enhancement mode IGZO thin film transistor T1 includes a substrate, a first gate electrode layer, a first gate dielectric layer and a first IGZO active layer arranged in sequence, and a first source electrode is arranged on the surface of the first IGZO active layer. and first drain;
  • the n-type depletion IGZO thin film transistor T2 includes a substrate, a second gate electrode layer, a second gate dielectric layer and a second IGZO active layer arranged in sequence; a second source is arranged on the surface of the second IGZO active layer. electrode and a second drain; the n-type depletion mode IGZO thin film transistor T2 also includes a normally open channel, the distance between the second source and the second drain is the channel length, and the normally open channel It is obtained by subjecting the IGZO active layer corresponding to the region between the second source electrode and the second drain electrode to hydrogen plasma treatment.
  • the first drain of the n-type enhancement type IGZO thin film transistor T1 and the second source and second gate electrode layer of the n-type depletion type IGZO thin film transistor T2 are short-circuited and connected to the V OUT signal.
  • the n-type enhancement mode IGZO thin film transistor T1 and the n-type depletion mode IGZO thin film transistor T2 share a substrate, and the substrate is a rigid substrate or a flexible substrate.
  • first gate electrode layer and the second gate electrode layer are both disposed on the surface of the substrate and are made of molybdenum.
  • first gate dielectric layer completely covers the first gate electrode layer of the transistor T1
  • second gate dielectric layer completely covers the second gate electrode layer of the transistor T2.
  • the first gate dielectric layer and the second gate dielectric layer completely cover the first gate electrode layer of the transistor T1.
  • the material of the extremely dielectric layer is silicon dioxide.
  • first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all made of molybdenum or aluminum.
  • the preparation method of an inverter based on IGZO thin film transistors of the present invention includes the following steps:
  • Step 1 Clean the substrate, and prepare a patterned gate electrode layer on the substrate; the patterned gate electrode layer includes a first gate electrode layer and a second gate electrode layer.
  • Step 2 Deposit a gate dielectric layer on the substrate with a gate electrode layer through a PECVD process.
  • the first gate dielectric layer is located on the surface of the first gate electrode layer, and the second gate dielectric layer is located on the surface of the second gate electrode layer.
  • Step 4 Form a first source electrode and a first drain electrode on the first IGZO active layer through an electron beam evaporation process to obtain an n-type enhancement mode IGZO thin film transistor T1; form a second source electrode on the surface of the second IGZO active layer and the second drain electrode, and short-circuit the first drain electrode, the second source electrode, and the second gate electrode.
  • step 5 the hydrogen plasma treatment process environment is: reaction power is 100W, chamber pressure is 1200mTorr, hydrogen flow rate is 170sccm, reaction temperature is 30°C, and reaction time is 200s.
  • the conventional n-type enhancement-type IGZO thin film transistor with gate-to-drain short circuit is used as the inverter of the pull-up device, but still has shortcomings such as low gain and low swing.
  • hydrogen doping is achieved through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is transformed into an n-type depletion mode IGZO thin film transistor.
  • n-type enhancement type IGZO thin film transistor with the gate-drain shorted is used as an inverter of the pull-up device
  • the n-type lossy transistor with the gate-source shorted is used as the inverter of the pull-up device with higher gain and larger swing.
  • the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
  • Figure 1 is a schematic circuit diagram of a thin film transistor-based inverter in an embodiment of the present invention.
  • Figure 3 is a flow chart of a method for preparing a thin film transistor-based inverter in an embodiment
  • Figure 4 is a voltage transfer characteristic curve diagram of the embodiment of the present invention.
  • 110 Substrate; 120. First gate electrode layer; 130. First gate dielectric layer; 140. First IGZO active layer; 150. First source electrode; 152. First drain electrode;
  • the second gate electrode layer 131.
  • the second gate dielectric layer 141.
  • the second IGZO active layer 151.
  • the second source electrode 153.
  • the currently commonly used method of preparing an inverter based on an IGZO thin film transistor is to use an n-type enhancement-type IGZO thin-film transistor with a gate-drain short circuit as a pull-up device and an n-type enhancement-type IGZO as a pull-down device to form an inverter.
  • phase inverters still have shortcomings such as low gain and low swing.
  • hydrogen doping is achieved through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is transformed into an n-type depletion mode IGZO thin film transistor.
  • the n-type depletion mode IGZO thin film transistor with the gate source shorted as the inverter of the pull-up device has higher gain and larger swing; at the same time, the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
  • An inverter based on IGZO thin film transistors including an n-type enhancement IGZO thin film transistor T1 and an n-type depletion IGZO thin film transistor T2, in which the n-type depletion IGZO thin film transistor T2 serves as a pull-up device;
  • the n-type enhancement mode IGZO thin film transistor T1 sequentially includes a substrate 110, a first gate electrode layer 120, a first gate dielectric layer 130 and a first IGZO active layer 140.
  • a first source electrode 150 and a first drain electrode 152 are provided on the surface of layer 140;
  • the first gate electrode layer 120 of the n-type enhancement mode IGZO thin film transistor T1 serves as an input electrode and is connected to the V IN signal; the first gate electrode layer 120 of the n-type enhancement mode IGZO thin film transistor T1
  • the source electrode 150 serves as a ground electrode, which is connected to 0V voltage; the first drain electrode 152 of the n-type enhancement mode IGZO thin film transistor T1 and the second source electrode 151 and the second gate electrode layer 121 of the n-type depletion mode IGZO thin film transistor T2
  • the three are short-circuited as output electrodes and connected to the V OUT signal; the second drain electrode 153 of the n-type depletion mode IGZO thin film transistor T2 is used as an external power supply electrode and connected to the V DD signal.
  • Substrate 110 may be a rigid substrate (eg, glass) or a flexible substrate as is known in the art.
  • the substrate 110 is a semiconductor substrate, such as a silicon substrate. It should be pointed out that the size of each film layer in Figure 1 is only a representation and does not represent its actual size.
  • the first gate dielectric layer 130 and the second gate dielectric layer 131 completely cover the gate electrode layer of the transistor T1 and the gate electrode layer of the transistor T2 respectively, and are made of silicon dioxide.
  • the thickness of the gate electrode layer is 100 nm
  • the thickness of the gate dielectric layer is 100 nm
  • the thickness of the source electrode and the drain electrode is both 100 nm
  • the thickness of the IGZO active layer is 20 nm.
  • Figure 3 is a flow chart of a method for manufacturing an inverter based on an IGZO thin film transistor in an embodiment of the present invention. This method can be used to manufacture the inverter shown in Figure 2, including the following steps:
  • Step 1 Clean the substrate 110 and prepare a patterned gate electrode layer on the substrate 110;
  • Substrate 110 may be a rigid substrate (eg, glass) or a flexible substrate as is known in the art.
  • the substrate 110 is a semiconductor substrate, such as a silicon/silicon oxide substrate.
  • the substrate 110 is ultrasonically cleaned for five minutes at a power of 100 W to obtain the substrate 110 for subsequent operations.
  • a patterned photoresist is obtained, a glue remover is used to process the residual glue that may exist in the pattern area, and a magnetron sputtering process is used.
  • a molybdenum metal layer is formed on the substrate 110 (at this time, there is patterned photoresist on the surface of the substrate), and a lift-off process is further used to obtain a patterned gate electrode layer to form the first gate electrode layer 120 and the second gate electrode layer. 121.
  • Other materials/structures commonly known in the art may also be used as the gate electrode layer.
  • the thickness of the prepared gate electrode layer is 100 nm.
  • a gate dielectric layer is covered on the gate electrode layer through a PECVD process.
  • the first gate dielectric layer 130 is located on the surface of the first gate electrode layer 120
  • the first gate dielectric layer 130 is located on the surface of the second gate electrode layer 121 .
  • the material of the gate dielectric layer is silicon dioxide.
  • the PECVD process parameters used in this embodiment are as follows: working pressure 1000mTorr, the ratio of N 2 O and SiH 4 with a concentration of 5% is 710:170, the power is 100W, and the reaction temperature is 300°C.
  • the thickness of the prepared gate dielectric layer is 100 nm.
  • Step 3 Form an IGZO active layer on the gate dielectric layer.
  • an IGZO active layer is formed on the gate dielectric layer through a radio frequency magnetron sputtering process.
  • the reaction conditions used in this embodiment are as follows: the sputtering pressure is 0.5 Pa, and Ar and O 2 are introduced The ratio is 45:5, the sputtering power is 80W, and the sputtering time is 1000s.
  • the first The IGZO active layer 140 is located on the surface of the first gate dielectric layer 130
  • the second IGZO active layer 141 is located on the surface of the second gate dielectric layer 131 , between the first IGZO active layer 140 and the second IGZO active layer 141 There is a gap between them, and then the annealing process is performed.
  • the annealing conditions in this embodiment are as follows: the temperature is 350°C, the annealing atmosphere is Ar, and the annealing time is 1 hour. In this embodiment, the thickness of the prepared IGZO active layer is 20 nm.
  • Step 4 Form source and drain electrodes on the IGZO active layer.
  • an aluminum Al metal layer is covered on the IGZO active layer using an electron beam evaporation process on the surface of the IGZO active layer.
  • the Al metal layer is Patterned photoresist is obtained on the surface, and the Al metal layer is etched with an aluminum Al etching solution (the patterned photoresist exists on the surface of the Al metal layer at this time).
  • the first IGZO active layer 140 can be A first source electrode 150 and a first drain electrode 152 are formed on the surface to obtain an n-type enhancement type IGZO thin film transistor T1; a second source electrode 151 and a second drain electrode 153 are formed on the surface of the second IGZO active layer 141, and the first The drain electrode 152, the second source electrode 151, and the second gate electrode are short-circuited.
  • other materials commonly known in the art may also be used as the materials of the source electrode layer/drain electrode layer.
  • the prepared source region electrode layer and drain region electrode layer have a thickness of 100 nm.
  • Step 5 Perform hydrogen plasma treatment on the second IGZO active layer 141 located between the second source electrode 151 and the second drain electrode 153 to form a normally open channel 142, and prepare an n-type depletion IGZO thin film transistor. T2.
  • FIG. 4 is a transfer characteristic curve diagram of an embodiment of the present invention.
  • the abscissa is the size of the input signal V IN
  • the ordinate is the size of the output signal V OUT .
  • the embodiment provided by the present invention has higher gain and larger swing, and the performance improvement effect is significant.

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Abstract

Provided in the present invention are a phase inverter based on an IGZO thin-film transistor, and a preparation method therefor. The method comprises: acquiring a substrate; forming a gate electrode layer on the substrate; forming a gate dielectric layer on the gate electrode layer; forming an IGZO active layer on the gate dielectric layer; forming a source electrode and a drain electrode on the IGZO active layer; and performing local hydrogen plasma treatment on the IGZO active layer. Hydrogen doping is realized by means of a hydrogen plasma treatment process, such that an n-type enhancement-type IGZO thin-film transistor in a pull-up network of the phase inverter is converted into an n-type depletion-type IGZO thin-film transistor. Compared with a phase inverter in which a gate-drain short-circuited n-type enhancement-type IGZO thin-film transistor is used as a pull-up device, the phase inverter provided in the present invention has a higher gain and a larger swing. Moreover, the process is simple and efficient and can be conveniently operated, and a gas source used for a reaction can be easily acquired, thereby meeting the quantity demand of large-scale industrial production.

Description

一种基于IGZO薄膜晶体管的反相器及其制备方法An inverter based on IGZO thin film transistor and preparation method thereof 技术领域Technical field
本发明涉及电子器件及其制备技术领域，特别是一种基于IGZO薄膜晶体管的反相器及其制备方法。The invention relates to the technical field of electronic devices and their preparation, in particular to an inverter based on an IGZO thin film transistor and its preparation method.
背景技术Background technique
柔性电子，是将金属氧化物、有机材料、碳纳米管等电子器件制作在柔性、可延展基板上的新兴电子技术，获得了学术界和产业界的广泛关注。由于传统硅基器件无法做到“柔性”，金属氧化物薄膜晶体管成为了其最有希望的替代者。金属氧化物薄膜晶体管除了具有良好的柔性外，还具有更高的迁移率、更低的制备温度等优点。铟镓锌氧化物(indium gallium zinc oxide，IGZO)是目前金属氧化物薄膜晶体管中一种主流的有源层材料，具有高迁移率、低关态电流、宽带隙(～3.5eV)等优点，是制备柔性电子产品的理想半导体材料。Flexible electronics is an emerging electronic technology that manufactures electronic devices such as metal oxides, organic materials, and carbon nanotubes on flexible and ductile substrates. It has attracted widespread attention from academia and industry. Since traditional silicon-based devices cannot be "flexible", metal oxide thin film transistors have become their most promising substitutes. In addition to good flexibility, metal oxide thin film transistors also have the advantages of higher mobility and lower preparation temperature. Indium gallium zinc oxide (IGZO) is currently a mainstream active layer material in metal oxide thin film transistors. It has the advantages of high mobility, low off-state current, and wide bandgap (~3.5eV). It is an ideal semiconductor material for preparing flexible electronic products.
稳定可靠的反相器是实现高性能数字电路和模拟电路的基础，因此利用IGZO薄膜晶体管制备反相器是实现柔性电路及产品过程中至关重要的一步。传统的硅基反相器采用将n管作为下拉网络、p管作为上拉网络的CMOS结构，然而大部分IGZO薄膜晶体管都是n型增强管，并且当前的工艺和制备流程难以制造出性能良好的p型IGZO薄膜晶体管，因此这种CMOS结构不再适用。Stable and reliable inverters are the basis for realizing high-performance digital circuits and analog circuits. Therefore, using IGZO thin film transistors to prepare inverters is a crucial step in the process of realizing flexible circuits and products. Traditional silicon-based inverters use a CMOS structure with n-tubes as the pull-down network and p-tubes as the pull-up network. However, most IGZO thin film transistors are n-type enhancement transistors, and it is difficult to manufacture them with good performance using the current technology and preparation process. p-type IGZO thin film transistor, so this CMOS structure is no longer applicable.
目前通常将栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件制备反相器，但这种结构的反相器具有电压增益低、输出摆幅小等缺点。为了提升基于IGZO薄膜晶体管的反相器的性能，当前广泛采用的方法是将栅源短接的n型耗尽型IGZO薄膜晶体管作为上拉器件，将n型增强型IGZO薄膜晶体管作为下拉器件。目前实现n型耗尽型IGZO薄膜晶体管的主要方法有：采用双栅结构动态控制晶体管的阈值、通过激光退火或者沉积多层有源层等工艺来改变晶体管的类型。但双栅结构需要额外的顶栅控制电路，增加了电路设计的复杂性，不易实现；激光退火和多层有源层等办法又会使得工艺过于复杂、繁琐。At present, n-type enhancement-type IGZO thin film transistors with gate-to-drain short circuits are usually used as pull-up devices to prepare inverters. However, inverters with this structure have shortcomings such as low voltage gain and small output swing. In order to improve the performance of inverters based on IGZO thin film transistors, the currently widely used method is to use n-type depletion mode IGZO thin film transistors with gate-source short circuits as pull-up devices and n-type enhancement mode IGZO thin film transistors as pull-down devices. At present, the main methods to realize n-type depletion IGZO thin film transistors include: dynamically controlling the threshold of the transistor using a dual-gate structure, changing the type of transistor through processes such as laser annealing or depositing multi-layer active layers. However, the double-gate structure requires additional top-gate control circuits, which increases the complexity of circuit design and is difficult to implement; methods such as laser annealing and multi-layer active layers will make the process too complex and cumbersome.
因此有必要提出一种基于IGZO薄膜晶体管的反相器及其制备方法，实现高增益、全摆幅的反相器，并且使电路设计和工艺流程简单化。Therefore, it is necessary to propose an inverter based on IGZO thin film transistor and its preparation method to achieve a high-gain, full-swing inverter and simplify the circuit design and process flow.
发明内容Contents of the invention
针对上述问题，本发明提供了一种反相器及其制备方法：通过氢等离子体处 理工艺形成常开型沟道，使上拉网络中的n型增强型IGZO薄膜晶体管转变为n型耗尽型IGZO薄膜晶体管，相比于将栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件的反相器，将栅源短接的n型耗尽型IGZO薄膜晶体管作为上拉器件的反相器具有更高的增益和更大的摆幅；与此同时，该工艺简单快捷，便于操作，反应所用的气体源易获取，满足大规模工业生产的需求量。In response to the above problems, the present invention provides an inverter and a preparation method thereof: a normally open channel is formed through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is converted into an n-type depletion Type IGZO thin film transistor, compared with the n-type enhancement type IGZO thin film transistor with the gate and drain shorted as the inverter of the pull-up device, the n-type depletion type IGZO thin film transistor with the gate source shorted as the inverter of the pull-up device The phase device has higher gain and larger swing; at the same time, the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
为了实现上述目的，本发明采用如下的技术方案：In order to achieve the above objects, the present invention adopts the following technical solutions:
本发明的一种基于IGZO薄膜晶体管的反相器,包括n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2，其中n型耗尽型IGZO薄膜晶体管T2作为上拉器件；An inverter based on IGZO thin film transistors of the present invention includes an n-type enhancement IGZO thin film transistor T1 and an n-type depletion IGZO thin film transistor T2, in which the n-type depletion IGZO thin film transistor T2 serves as a pull-up device;
n型增强型IGZO薄膜晶体管T1包括依次设置的衬底、第一栅电极层、第一栅极介电层和第一IGZO有源层，在第一IGZO有源层表面设置有第一源极和第一漏极；The n-type enhancement mode IGZO thin film transistor T1 includes a substrate, a first gate electrode layer, a first gate dielectric layer and a first IGZO active layer arranged in sequence, and a first source electrode is arranged on the surface of the first IGZO active layer. and first drain;
n型耗尽型IGZO薄膜晶体管T2包括依次设置的衬底、第二栅电极层、第二栅极介电层和第二IGZO有源层；在第二IGZO有源层表面设置有第二源极和第二漏极；所述n型耗尽型IGZO薄膜晶体管T2还包括常开型沟道，第二源极与第二漏极之间间距为沟道长度，所述常开型沟道通过对位于第二源极与第二漏极之间区域对应的IGZO有源层进行氢等离子体处理获得。The n-type depletion IGZO thin film transistor T2 includes a substrate, a second gate electrode layer, a second gate dielectric layer and a second IGZO active layer arranged in sequence; a second source is arranged on the surface of the second IGZO active layer. electrode and a second drain; the n-type depletion mode IGZO thin film transistor T2 also includes a normally open channel, the distance between the second source and the second drain is the channel length, and the normally open channel It is obtained by subjecting the IGZO active layer corresponding to the region between the second source electrode and the second drain electrode to hydrogen plasma treatment.
n型增强型IGZO薄膜晶体管T1的第一漏极和n型耗尽型IGZO薄膜晶体管T2的第二源极、第二栅电极层三者短接，接V OUT信号。 The first drain of the n-type enhancement type IGZO thin film transistor T1 and the second source and second gate electrode layer of the n-type depletion type IGZO thin film transistor T2 are short-circuited and connected to the V OUT signal.
进一步的，n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2共用衬底，衬底是刚性基底或柔性基底。Further, the n-type enhancement mode IGZO thin film transistor T1 and the n-type depletion mode IGZO thin film transistor T2 share a substrate, and the substrate is a rigid substrate or a flexible substrate.
进一步的，第一栅电极层和第二栅电极层均设置在衬底表面，材质为钼。Further, the first gate electrode layer and the second gate electrode layer are both disposed on the surface of the substrate and are made of molybdenum.
进一步的，第一栅极介电层完全覆盖晶体管T1的第一栅电极层，第二栅极介电层完全覆盖晶体管T2的第二栅电极层，第一栅极介电层和第二栅极介电层材质为二氧化硅。Further, the first gate dielectric layer completely covers the first gate electrode layer of the transistor T1, and the second gate dielectric layer completely covers the second gate electrode layer of the transistor T2. The first gate dielectric layer and the second gate dielectric layer completely cover the first gate electrode layer of the transistor T1. The material of the extremely dielectric layer is silicon dioxide.
进一步的，第一源极、第一漏极、第二源极和第二漏极均为钼或铝。Further, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all made of molybdenum or aluminum.
本发明的一种基于IGZO薄膜晶体管的反相器的制备方法，包括如下步骤：The preparation method of an inverter based on IGZO thin film transistors of the present invention includes the following steps:
步骤1，清洗衬底，在衬底上制备图案化的栅电极层；图案化的栅电极层包括第一栅电极层和第二栅电极层。Step 1: Clean the substrate, and prepare a patterned gate electrode layer on the substrate; the patterned gate electrode layer includes a first gate electrode layer and a second gate electrode layer.
步骤2，通过PECVD工艺在具有栅电极层的衬底上沉积栅极介电层，位于第一栅电极层表面的为第一栅极介电层，位于第二栅电极层表面的为第二栅极介电层；Step 2: Deposit a gate dielectric layer on the substrate with a gate electrode layer through a PECVD process. The first gate dielectric layer is located on the surface of the first gate electrode layer, and the second gate dielectric layer is located on the surface of the second gate electrode layer. gate dielectric layer;
步骤3，通过射频磁控溅射工艺，在栅极介电层上形成IGZO有源层，刻蚀IGZO有源层和位于第二栅极表面的第二栅极介电层，得到图案化IGZO有源层，以及在第二栅极介电层上形成窗口，使第二栅极部分暴露；图案化IGZO有源层包括第一IGZO有源层和第二IGZO有源层，第一IGZO有源层位于第一栅极介电层表面，第二IGZO有源层位于第二栅极介电层表面，第一IGZO有源层和第二IGZO有源层之间存在间隔。Step 3: Form an IGZO active layer on the gate dielectric layer through a radio frequency magnetron sputtering process, and etch the IGZO active layer and the second gate dielectric layer located on the surface of the second gate to obtain patterned IGZO. active layer, and forming a window on the second gate dielectric layer to partially expose the second gate; the patterned IGZO active layer includes a first IGZO active layer and a second IGZO active layer, and the first IGZO has The source layer is located on the surface of the first gate dielectric layer, the second IGZO active layer is located on the surface of the second gate dielectric layer, and there is a gap between the first IGZO active layer and the second IGZO active layer.
步骤4，通过电子束蒸发工艺在第一IGZO有源层上形成第一源极和第一漏极，得到n型增强型IGZO薄膜晶体管T1；在第二IGZO有源层表面形成第二源极和第二漏极，并将第一漏极、第二源极、第二栅电极短接。Step 4: Form a first source electrode and a first drain electrode on the first IGZO active layer through an electron beam evaporation process to obtain an n-type enhancement mode IGZO thin film transistor T1; form a second source electrode on the surface of the second IGZO active layer and the second drain electrode, and short-circuit the first drain electrode, the second source electrode, and the second gate electrode.
步骤5，对位于第二源极和第二漏极之间的第二IGZO有源层进行氢等离子体处理，形成常开型沟道，制备得到n型耗尽型IGZO薄膜晶体管T2。Step 5: The second IGZO active layer located between the second source electrode and the second drain electrode is subjected to hydrogen plasma treatment to form a normally open channel, and an n-type depletion mode IGZO thin film transistor T2 is prepared.
进一步的，步骤5中，氢等离子处理工艺环境为：反应功率为100W，腔室压强为1200mTorr，氢流量为170sccm，反应温度为30℃，反应时间为200s。Further, in step 5, the hydrogen plasma treatment process environment is: reaction power is 100W, chamber pressure is 1200mTorr, hydrogen flow rate is 170sccm, reaction temperature is 30°C, and reaction time is 200s.
有益效果：常规的采用栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件的反相器，仍具有低增益、低摆幅等缺点。为了制备基于IGZO薄膜晶体管的高性能反相器，通过氢等离子体处理工艺实现氢掺杂，使上拉网络中n型增强型IGZO薄膜晶体管转变为n型耗尽型IGZO薄膜晶体管，相比于将栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件的反相器，将栅源短接的n型耗尽管作为上拉器件的反相器具有更高的增益和更大的摆幅；与此同时，该工艺简单快捷，便于操作，反应所用的气体源易获取，满足大规模工业生产的需求量。Beneficial effects: The conventional n-type enhancement-type IGZO thin film transistor with gate-to-drain short circuit is used as the inverter of the pull-up device, but still has shortcomings such as low gain and low swing. In order to prepare high-performance inverters based on IGZO thin film transistors, hydrogen doping is achieved through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is transformed into an n-type depletion mode IGZO thin film transistor. Compared with The n-type enhancement type IGZO thin film transistor with the gate-drain shorted is used as an inverter of the pull-up device, and the n-type lossy transistor with the gate-source shorted is used as the inverter of the pull-up device with higher gain and larger swing. At the same time, the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
附图说明Description of the drawings
为了更清晰、简洁地说明本发明的实施例，本发明提供了多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。In order to explain the embodiments of the present invention more clearly and concisely, the present invention provides multiple drawings. The additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed inventions, the embodiments and/or examples presently described, and the best modes currently understood of these inventions.
图1是本发明的一实施例中基于薄膜晶体管的反相器的电路示意图Figure 1 is a schematic circuit diagram of a thin film transistor-based inverter in an embodiment of the present invention.
图2是一实施例中基于薄膜晶体管的反相器的结构示意图；Figure 2 is a schematic structural diagram of an inverter based on a thin film transistor in an embodiment;
图3是一实施例中基于薄膜晶体管的反相器的制备方法流程图；Figure 3 is a flow chart of a method for preparing a thin film transistor-based inverter in an embodiment;
图4是本发明实施例的电压转移特性曲线图。Figure 4 is a voltage transfer characteristic curve diagram of the embodiment of the present invention.
其中，110、衬底；120、第一栅电极层；、130、第一栅极介电层；140、第一IGZO有源层；150、第一源极；152、第一漏极；Among them, 110. Substrate; 120. First gate electrode layer; 130. First gate dielectric layer; 140. First IGZO active layer; 150. First source electrode; 152. First drain electrode;
121、第二栅电极层；、131、第二栅极介电层；141、第二IGZO有源层；151、第二源极；153、第二漏极；142、常开型沟道。121. The second gate electrode layer; 131. The second gate dielectric layer; 141. The second IGZO active layer; 151. The second source electrode; 153. The second drain electrode; 142. Normally open channel.
具体实施方式Detailed ways
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings.
附图2中给出了本发明的实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使读者对本发明的公开内容理解得更加透彻全面。除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。An embodiment of the invention is shown in Figure 2 of the accompanying drawing. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide the reader with a thorough and comprehensive understanding of the disclosure of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs.
目前常用的制备基于IGZO薄膜晶体管的反相器的方法是将栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件、将n型增强型IGZO作为下拉器件形成的反相器，该反相器相比于传统CMOS反相器，仍具有低增益、低摆幅等缺点。为了制备基于IGZO薄膜晶体管的高性能反相器，通过氢等离子体处理工艺实现氢掺杂，使上拉网络中的n型增强型IGZO薄膜晶体管转变为n型耗尽型IGZO薄膜晶体管。相比于将栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件的反相器，将栅源短接的n型耗尽型IGZO薄膜晶体管作为上拉器件的反相器具有更高的增益和更大的摆幅；与此同时，该工艺简单快捷，便于操作，反应所用的气体源易获取，满足大规模工业生产的需求量。The currently commonly used method of preparing an inverter based on an IGZO thin film transistor is to use an n-type enhancement-type IGZO thin-film transistor with a gate-drain short circuit as a pull-up device and an n-type enhancement-type IGZO as a pull-down device to form an inverter. Compared with traditional CMOS inverters, phase inverters still have shortcomings such as low gain and low swing. In order to prepare high-performance inverters based on IGZO thin film transistors, hydrogen doping is achieved through a hydrogen plasma treatment process, so that the n-type enhancement mode IGZO thin film transistor in the pull-up network is transformed into an n-type depletion mode IGZO thin film transistor. Compared with the n-type enhancement mode IGZO thin film transistor with the gate and drain shorted as an inverter of the pull-up device, the n-type depletion mode IGZO thin film transistor with the gate source shorted as the inverter of the pull-up device has higher gain and larger swing; at the same time, the process is simple, fast, easy to operate, and the gas source used in the reaction is easy to obtain, meeting the demand for large-scale industrial production.
一种基于IGZO薄膜晶体管的反相器,包括n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2，其中n型耗尽型IGZO薄膜晶体管T2作为上拉器件；An inverter based on IGZO thin film transistors, including an n-type enhancement IGZO thin film transistor T1 and an n-type depletion IGZO thin film transistor T2, in which the n-type depletion IGZO thin film transistor T2 serves as a pull-up device;
如图2所示，n型增强型IGZO薄膜晶体管T1依次包括衬底110、第一栅电极层120、第一栅极介电层130和第一IGZO有源层140，在第一IGZO有源层140表面设置有第一源极150和第一漏极152；As shown in Figure 2, the n-type enhancement mode IGZO thin film transistor T1 sequentially includes a substrate 110, a first gate electrode layer 120, a first gate dielectric layer 130 and a first IGZO active layer 140. In the first IGZO active layer A first source electrode 150 and a first drain electrode 152 are provided on the surface of layer 140;
n型耗尽型IGZO薄膜晶体管T2依次包括衬底110、第二栅电极层121、第二栅极介电层131和第二IGZO有源层141；在第二IGZO有源层141表面设置有第二源极151和第二漏极153；n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2共用衬底110，第一栅电极层120和第二栅电极层121均设置在衬底110表面，材质为钼。所述n型耗尽型IGZO薄膜晶体管T2还包括常开型沟道142，所述常开型沟道142通过对位于第二源极151与第二漏极153之间区域对应的IGZO有源层进行氢等离子体处理获得。The n-type depletion IGZO thin film transistor T2 sequentially includes a substrate 110, a second gate electrode layer 121, a second gate dielectric layer 131 and a second IGZO active layer 141; on the surface of the second IGZO active layer 141, The second source electrode 151 and the second drain electrode 153; the n-type enhancement type IGZO thin film transistor T1 and the n-type depletion type IGZO thin film transistor T2 share the substrate 110, and the first gate electrode layer 120 and the second gate electrode layer 121 are both provided On the surface of the substrate 110, the material is molybdenum. The n-type depletion IGZO thin film transistor T2 also includes a normally open channel 142. The normally open channel 142 is configured by connecting the IGZO active channel corresponding to the region between the second source electrode 151 and the second drain electrode 153. The layer is obtained by hydrogen plasma treatment.
如图1所示，是本申请实施例的电路示意图，n型增强型IGZO薄膜晶体管T1的第一栅电极层120作为输入电极，接V IN信号；n型增强型IGZO薄膜晶体管T1的第一源极150作为接地电极，接地即接0V电压；n型增强型IGZO薄膜晶体管T1的第一漏极152和n型耗尽型IGZO薄膜晶体管T2的第二源极151、第二栅电极层121三者短接作为输出电极，接V OUT信号；n型耗尽型IGZO薄膜晶体管T2的第二漏极153作为外部供电电极，接V DD信号。 As shown in Figure 1, it is a schematic circuit diagram of an embodiment of the present application. The first gate electrode layer 120 of the n-type enhancement mode IGZO thin film transistor T1 serves as an input electrode and is connected to the V IN signal; the first gate electrode layer 120 of the n-type enhancement mode IGZO thin film transistor T1 The source electrode 150 serves as a ground electrode, which is connected to 0V voltage; the first drain electrode 152 of the n-type enhancement mode IGZO thin film transistor T1 and the second source electrode 151 and the second gate electrode layer 121 of the n-type depletion mode IGZO thin film transistor T2 The three are short-circuited as output electrodes and connected to the V OUT signal; the second drain electrode 153 of the n-type depletion mode IGZO thin film transistor T2 is used as an external power supply electrode and connected to the V DD signal.
衬底110可以是本领域习知的刚性基底(例如玻璃)或柔性基底。在本实施例中，衬底110为半导体衬底，例如硅衬底。需要指出的是，各膜层在图1中的尺寸只是一个示意，并不代表其实际尺寸。 Substrate 110 may be a rigid substrate (eg, glass) or a flexible substrate as is known in the art. In this embodiment, the substrate 110 is a semiconductor substrate, such as a silicon substrate. It should be pointed out that the size of each film layer in Figure 1 is only a representation and does not represent its actual size.
第一栅极介电层130和第二栅极介电层131分别完全覆盖晶体管T1的栅电极层和晶体管T2的栅电极层，材质为二氧化硅。The first gate dielectric layer 130 and the second gate dielectric layer 131 completely cover the gate electrode layer of the transistor T1 and the gate electrode layer of the transistor T2 respectively, and are made of silicon dioxide.
第一源极150、第一漏极152、第二源极151和第二漏极153均为钼源极，在其他实施例中，也可以采用本领域习知的其他源漏材质作为源极/漏极的材料。The first source electrode 150 , the first drain electrode 152 , the second source electrode 151 and the second drain electrode 153 are all molybdenum source electrodes. In other embodiments, other source and drain materials commonly known in the art can also be used as the source electrodes. /Drain material.
在图2所示的实施例中，栅电极层的厚度为100nm，栅极介电层厚度为100nm，源极和漏极的厚度皆为100nm，IGZO有源层的厚度为20nm。In the embodiment shown in FIG. 2 , the thickness of the gate electrode layer is 100 nm, the thickness of the gate dielectric layer is 100 nm, the thickness of the source electrode and the drain electrode is both 100 nm, and the thickness of the IGZO active layer is 20 nm.
图3是本发明实施例中基于IGZO薄膜晶体管的反相器的制备方法流程图，该方法可以用于制造图2所示的反相器，包括如下步骤：Figure 3 is a flow chart of a method for manufacturing an inverter based on an IGZO thin film transistor in an embodiment of the present invention. This method can be used to manufacture the inverter shown in Figure 2, including the following steps:
步骤1，清洗衬底110，在衬底110上制备图案化的栅电极层；Step 1: Clean the substrate 110 and prepare a patterned gate electrode layer on the substrate 110;
衬底110可以是本领域习知的刚性基底(例如玻璃)或柔性基底。在本发明的一个实施例中，衬底110为半导体衬底，例如硅/氧化硅衬底。以去离子水、丙酮、无水乙醇、去离子水的顺序，在100W的功率下各对衬底110超声清洗五分钟，可获得供后续操作的衬底110。 Substrate 110 may be a rigid substrate (eg, glass) or a flexible substrate as is known in the art. In one embodiment of the invention, the substrate 110 is a semiconductor substrate, such as a silicon/silicon oxide substrate. Using deionized water, acetone, absolute ethanol, and deionized water in this order, the substrate 110 is ultrasonically cleaned for five minutes at a power of 100 W to obtain the substrate 110 for subsequent operations.
通过在所述衬底110表面进行匀胶、光刻、烘干、曝光和显影处理，获得图案化的光刻胶，采用去胶机处理图形区域可能存在的残胶，利用磁控溅射工艺在衬底110(此时衬底表面存在图案化光刻胶)上形成钼金属层，进一步采用lift-off工艺得到图案化的栅电极层，形成第一栅电极层120和第二栅电极层121。也可以采用本领域习知的其他材质/结构作为栅电极层。在本实施例中，制备的栅电极层厚度为100nm。By performing glue leveling, photolithography, drying, exposure and development on the surface of the substrate 110, a patterned photoresist is obtained, a glue remover is used to process the residual glue that may exist in the pattern area, and a magnetron sputtering process is used. A molybdenum metal layer is formed on the substrate 110 (at this time, there is patterned photoresist on the surface of the substrate), and a lift-off process is further used to obtain a patterned gate electrode layer to form the first gate electrode layer 120 and the second gate electrode layer. 121. Other materials/structures commonly known in the art may also be used as the gate electrode layer. In this embodiment, the thickness of the prepared gate electrode layer is 100 nm.
步骤2，在具有栅电极层的衬底110上沉积栅极介电层 Step 2, deposit a gate dielectric layer on the substrate 110 having the gate electrode layer
在本实施例中，通过PECVD工艺在所述栅电极层上覆盖栅极介电层，位于第 一栅电极层120表面的为第一栅极介电层130，位于第二栅电极层121表面的为第二栅极介电层131，栅极介电层材质为二氧化硅。本实施例中采用的PECVD工艺参数如下：工作压强1000mTorr，通入N 2O和5％浓度的SiH 4的比例为710:170，功率为100W，反应温度300℃。在本实施例中，制备的栅介电层厚度为100nm。 In this embodiment, a gate dielectric layer is covered on the gate electrode layer through a PECVD process. The first gate dielectric layer 130 is located on the surface of the first gate electrode layer 120 , and the first gate dielectric layer 130 is located on the surface of the second gate electrode layer 121 . is the second gate dielectric layer 131, and the material of the gate dielectric layer is silicon dioxide. The PECVD process parameters used in this embodiment are as follows: working pressure 1000mTorr, the ratio of N 2 O and SiH 4 with a concentration of 5% is 710:170, the power is 100W, and the reaction temperature is 300°C. In this embodiment, the thickness of the prepared gate dielectric layer is 100 nm.
步骤3，在栅极介电层上形成IGZO有源层。Step 3: Form an IGZO active layer on the gate dielectric layer.
在本实施例中，通过射频磁控溅射工艺在所述栅极介电层上形成IGZO有源层，本实施例中采用的反应条件如下：溅射压力0.5Pa，通入Ar和O 2的比例为45:5，溅射功率为80W，溅射时长为1000s。 In this embodiment, an IGZO active layer is formed on the gate dielectric layer through a radio frequency magnetron sputtering process. The reaction conditions used in this embodiment are as follows: the sputtering pressure is 0.5 Pa, and Ar and O 2 are introduced The ratio is 45:5, the sputtering power is 80W, and the sputtering time is 1000s.
通过在IGZO有源层表面进行匀胶、光刻、烘干、曝光和显影处理，获得图案化的光刻胶，采用稀释的氢氟酸(～1％)刻蚀IGZO有源层和位于第二栅极表面的第二栅极介电层131，经过去胶处理可得到图案化IGZO有源层，以及第二栅极介电层131上形成窗口，使第二栅极部分暴露，用于后面步骤中将第二栅极与第一漏极152、第二源极151短接时使用；图案化IGZO有源层包括第一IGZO有源层140和第二IGZO有源层141，第一IGZO有源层140位于第一栅极介电层130表面，第二IGZO有源层141位于第二栅极介电层131表面，第一IGZO有源层140和第二IGZO有源层141之间存在间隔，随即进行退火处理，本实施例中的退火条件如下：温度为350℃，退火氛围为Ar，退火时间为1h。在本实施例中，制备的IGZO有源层厚度为20nm。By performing glue leveling, photolithography, drying, exposure and development on the surface of the IGZO active layer, a patterned photoresist is obtained, and dilute hydrofluoric acid (~1%) is used to etch the IGZO active layer and the The second gate dielectric layer 131 on the surface of the second gate electrode can be removed to obtain a patterned IGZO active layer, and a window is formed on the second gate dielectric layer 131 to partially expose the second gate electrode. It is used when the second gate electrode is short-circuited with the first drain electrode 152 and the second source electrode 151 in the following steps; the patterned IGZO active layer includes the first IGZO active layer 140 and the second IGZO active layer 141. The first The IGZO active layer 140 is located on the surface of the first gate dielectric layer 130 , the second IGZO active layer 141 is located on the surface of the second gate dielectric layer 131 , between the first IGZO active layer 140 and the second IGZO active layer 141 There is a gap between them, and then the annealing process is performed. The annealing conditions in this embodiment are as follows: the temperature is 350°C, the annealing atmosphere is Ar, and the annealing time is 1 hour. In this embodiment, the thickness of the prepared IGZO active layer is 20 nm.
步骤4，在IGZO有源层上形成源极、漏极。Step 4: Form source and drain electrodes on the IGZO active layer.
在本实施例中，在所述IGZO有源层表面利用电子束蒸发工艺在IGZO有源层上覆盖铝Al金属层，通过匀胶、光刻、烘干、曝光和显影处理，在Al金属层表面获得图案化的光刻胶，采用铝Al刻蚀液刻蚀Al金属层(此时的Al金属层表面存在图案化光刻胶)，经过去胶处理即可在第一IGZO有源层140表面形成第一源极150和第一漏极152，得到n型增强型IGZO薄膜晶体管T1；在第二IGZO有源层141表面形成第二源极151和第二漏极153，并将第一漏极152、第二源极151、第二栅电极短接。在其他实施例中，也可以采用其他本领域习知的材质作为源区电极层/漏区电极层的材料。在本实施例中，制备的源区电极层、漏区电极层厚度为100nm。In this embodiment, an aluminum Al metal layer is covered on the IGZO active layer using an electron beam evaporation process on the surface of the IGZO active layer. Through glue dispersion, photolithography, drying, exposure and development, the Al metal layer is Patterned photoresist is obtained on the surface, and the Al metal layer is etched with an aluminum Al etching solution (the patterned photoresist exists on the surface of the Al metal layer at this time). After the gel removal process, the first IGZO active layer 140 can be A first source electrode 150 and a first drain electrode 152 are formed on the surface to obtain an n-type enhancement type IGZO thin film transistor T1; a second source electrode 151 and a second drain electrode 153 are formed on the surface of the second IGZO active layer 141, and the first The drain electrode 152, the second source electrode 151, and the second gate electrode are short-circuited. In other embodiments, other materials commonly known in the art may also be used as the materials of the source electrode layer/drain electrode layer. In this embodiment, the prepared source region electrode layer and drain region electrode layer have a thickness of 100 nm.
步骤5，对位于第二源极151和第二漏极153之间的第二IGZO有源层141进行氢等离子体处理，形成常开型沟道142，制备得到n型耗尽型IGZO薄膜晶 体管T2。Step 5: Perform hydrogen plasma treatment on the second IGZO active layer 141 located between the second source electrode 151 and the second drain electrode 153 to form a normally open channel 142, and prepare an n-type depletion IGZO thin film transistor. T2.
在本实施例中，通过匀胶、光刻、曝光和显影处理可在位于第二源极151和第二漏极153之间的第二IGZO有源层141上表面获得以供氢掺杂的窗口，通过对其进行氢等离子体处理，形成常开型沟道142，获得n型耗尽型IGZO薄膜晶体管，所述氢等离子处理工艺环境为：反应功率为100W，腔室压强为1200mTorr，氢流量为170sccm，反应温度为30℃，反应时间为200s。In this embodiment, a layer for hydrogen doping can be obtained on the upper surface of the second IGZO active layer 141 between the second source electrode 151 and the second drain electrode 153 through smearing, photolithography, exposure and development processes. The window is subjected to hydrogen plasma treatment to form a normally open channel 142, and an n-type depletion mode IGZO thin film transistor is obtained. The hydrogen plasma treatment process environment is: reaction power is 100W, chamber pressure is 1200mTorr, hydrogen The flow rate is 170 sccm, the reaction temperature is 30°C, and the reaction time is 200 s.
图4是本发明实施例的转移特性曲线图，横坐标是输入信号V IN的大小，纵坐标是输出信号V OUT的大小。可以看出，在供电电压V DD＝5V时的反相器增益和摆幅分别是17.93和4.95V；在供电电压V DD＝10V时的反相器增益和摆幅分别是49.361和9.93V。两种供电电压情况下的摆幅都接近全摆幅，在V DD＝10V时的反相器增益甚至达到了49.361，与采用栅漏短接的n型增强型IGZO薄膜晶体管作为上拉器件的反相器相比，本发明所提供的实施例具有更高的增益和更大的摆幅，性能提升的成效显著。 Figure 4 is a transfer characteristic curve diagram of an embodiment of the present invention. The abscissa is the size of the input signal V IN , and the ordinate is the size of the output signal V OUT . It can be seen that the inverter gain and swing when the supply voltage V DD =5V are 17.93 and 4.95V respectively; when the supply voltage V DD =10V, the inverter gain and swing are 49.361 and 9.93V respectively. The swing amplitude under both supply voltages is close to the full swing, and the inverter gain even reaches 49.361 when V DD =10V, which is similar to the use of an n-type enhancement-type IGZO thin film transistor with gate-to-drain short circuit as a pull-up device. Compared with the inverter, the embodiment provided by the present invention has higher gain and larger swing, and the performance improvement effect is significant.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (7)

  1. 一种基于IGZO薄膜晶体管的反相器,其特征在于，包括n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2，其中n型耗尽型IGZO薄膜晶体管T2作为上拉器件；An inverter based on IGZO thin film transistors, characterized by including an n-type enhancement type IGZO thin film transistor T1 and an n-type depletion type IGZO thin film transistor T2, wherein the n-type depletion type IGZO thin film transistor T2 serves as a pull-up device;
    n型增强型IGZO薄膜晶体管T1包括依次设置的衬底、第一栅电极层、第一栅极介电层和第一IGZO有源层，在第一IGZO有源层表面设置有第一源极和第一漏极；The n-type enhancement mode IGZO thin film transistor T1 includes a substrate, a first gate electrode layer, a first gate dielectric layer and a first IGZO active layer arranged in sequence, and a first source electrode is arranged on the surface of the first IGZO active layer. and first drain;
    n型耗尽型IGZO薄膜晶体管T2包括依次设置的衬底、第二栅电极层、第二栅极介电层和第二IGZO有源层；在第二IGZO有源层表面设置有第二源极和第二漏极；所述n型耗尽型IGZO薄膜晶体管T2还包括常开型沟道，所述常开型沟道通过对位于第二源极与第二漏极之间区域对应的IGZO有源层进行氢等离子体处理获得；The n-type depletion IGZO thin film transistor T2 includes a substrate, a second gate electrode layer, a second gate dielectric layer and a second IGZO active layer arranged in sequence; a second source is arranged on the surface of the second IGZO active layer. electrode and the second drain; the n-type depletion IGZO thin film transistor T2 also includes a normally open channel, the normally open channel is formed by aligning the corresponding region between the second source and the second drain. The IGZO active layer is obtained by hydrogen plasma treatment;
    n型增强型IGZO薄膜晶体管T1的第一漏极和n型耗尽型IGZO薄膜晶体管T2的第二源极、第二栅电极层三者短接。The first drain electrode of the n-type enhancement type IGZO thin film transistor T1, the second source electrode and the second gate electrode layer of the n-type depletion type IGZO thin film transistor T2 are short-circuited.
  2. 根据权利要求1所述一种基于IGZO薄膜晶体管的反相器,其特征在于，n型增强型IGZO薄膜晶体管T1和n型耗尽型IGZO薄膜晶体管T2共用衬底，衬底是刚性基底或柔性基底。An inverter based on an IGZO thin film transistor according to claim 1, characterized in that the n-type enhancement type IGZO thin film transistor T1 and the n-type depletion type IGZO thin film transistor T2 share a substrate, and the substrate is a rigid substrate or a flexible substrate. base.
  3. 根据权利要求1所述一种基于IGZO薄膜晶体管的反相器,其特征在于，第一栅电极层和第二栅电极层均设置在衬底表面，材质为钼。An inverter based on an IGZO thin film transistor according to claim 1, characterized in that the first gate electrode layer and the second gate electrode layer are both arranged on the surface of the substrate and are made of molybdenum.
  4. 根据权利要求1所述一种基于IGZO薄膜晶体管的反相器,其特征在于，第一栅极介电层完全覆盖晶体管T1的第一栅电极层，第二栅极介电层完全覆盖晶体管T2的第二栅电极层，第一栅极介电层和第二栅极介电层材质为二氧化硅。An inverter based on an IGZO thin film transistor according to claim 1, characterized in that the first gate dielectric layer completely covers the first gate electrode layer of the transistor T1, and the second gate dielectric layer completely covers the transistor T2. The material of the second gate electrode layer, the first gate dielectric layer and the second gate dielectric layer is silicon dioxide.
  5. 根据权利要求1所述一种基于IGZO薄膜晶体管的反相器,其特征在于，第一源极、第一漏极、第二源极和第二漏极均为钼或铝。An inverter based on an IGZO thin film transistor according to claim 1, characterized in that the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all molybdenum or aluminum.
  6. 一种基于IGZO薄膜晶体管的反相器的制备方法，其特征在于，包括如下步骤：A method for preparing an inverter based on an IGZO thin film transistor, which is characterized by including the following steps:
    步骤1，清洗衬底，在衬底上制备图案化的栅电极层；图案化的栅电极层包括第一栅电极层和第二栅电极层；Step 1: Clean the substrate and prepare a patterned gate electrode layer on the substrate; the patterned gate electrode layer includes a first gate electrode layer and a second gate electrode layer;
    步骤2，通过PECVD工艺在具有栅电极层的衬底上沉积栅极介电层，位于第一栅电极层表面的为第一栅极介电层，位于第二栅电极层表面的为第二栅极介电层；Step 2: Deposit a gate dielectric layer on the substrate with a gate electrode layer through a PECVD process. The first gate dielectric layer is located on the surface of the first gate electrode layer, and the second gate dielectric layer is located on the surface of the second gate electrode layer. gate dielectric layer;
    步骤3，通过射频磁控溅射工艺，在栅极介电层上形成IGZO有源层，刻蚀IGZO有源层和位于第二栅极表面的第二栅极介电层，得到图案化IGZO有源层，以及在第二栅极介电层上形成窗口，使第二栅极部分暴露；图案化IGZO有源层 包括第一IGZO有源层和第二IGZO有源层，第一IGZO有源层位于第一栅极介电层表面，第二IGZO有源层位于第二栅极介电层表面，第一IGZO有源层和第二IGZO有源层之间存在间隔；Step 3: Form an IGZO active layer on the gate dielectric layer through a radio frequency magnetron sputtering process, and etch the IGZO active layer and the second gate dielectric layer located on the surface of the second gate to obtain patterned IGZO. active layer, and forming a window on the second gate dielectric layer to partially expose the second gate; the patterned IGZO active layer includes a first IGZO active layer and a second IGZO active layer, and the first IGZO has The source layer is located on the surface of the first gate dielectric layer, the second IGZO active layer is located on the surface of the second gate dielectric layer, and there is a gap between the first IGZO active layer and the second IGZO active layer;
    步骤4，通过电子束蒸发工艺在第一IGZO有源层上形成第一源极和第一漏极，得到n型增强型IGZO薄膜晶体管T1；在第二IGZO有源层表面形成第二源极和第二漏极，并将第一漏极、第二源极、第二栅电极短接；Step 4: Form a first source electrode and a first drain electrode on the first IGZO active layer through an electron beam evaporation process to obtain an n-type enhancement mode IGZO thin film transistor T1; form a second source electrode on the surface of the second IGZO active layer and a second drain electrode, and short-circuit the first drain electrode, the second source electrode, and the second gate electrode;
    步骤5，对位于第二源极和第二漏极之间的第二IGZO有源层进行氢等离子体处理，形成常开型沟道，制备得到n型耗尽型IGZO薄膜晶体管T2。Step 5: The second IGZO active layer located between the second source electrode and the second drain electrode is subjected to hydrogen plasma treatment to form a normally open channel, and an n-type depletion mode IGZO thin film transistor T2 is prepared.
  7. 根据权利要求6所述一种基于IGZO薄膜晶体管的反相器的制备方法，其特征在于，步骤5中，氢等离子处理工艺环境为：反应功率为100W，腔室压强为1200mTorr，氢流量为170sccm，反应温度为30℃，反应时间为200s。A method for preparing an inverter based on an IGZO thin film transistor according to claim 6, characterized in that in step 5, the hydrogen plasma treatment process environment is: reaction power is 100W, chamber pressure is 1200mTorr, and hydrogen flow rate is 170sccm , the reaction temperature is 30°C, and the reaction time is 200s.
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