CN114865908B - I-type three-level circuit - Google Patents
I-type three-level circuit Download PDFInfo
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- CN114865908B CN114865908B CN202210551710.8A CN202210551710A CN114865908B CN 114865908 B CN114865908 B CN 114865908B CN 202210551710 A CN202210551710 A CN 202210551710A CN 114865908 B CN114865908 B CN 114865908B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/072—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate an output voltage whose value is lower than the input voltage
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Abstract
The invention discloses an I-type three-level circuit, which is provided with a controller, a charge-discharge module and a logic judgment module consisting of an AND gate, wherein the controller outputs high level through a first output module when in work, and the charge-discharge module starts charging and inputs high level to a second input end of a second AND gate and a second input end of a third AND gate. Meanwhile, the first input ends of the first AND gate and the fourth AND gate are connected with the first output module, so that the first outer pipe, the first inner pipe, the second inner pipe and the second outer pipe are in a working state when the controller works; when the controller is turned off, the first output module outputs low level, the first outer tube and the second outer tube are turned off, and meanwhile, the charging and discharging module starts discharging, and when the discharging is performed until the time delay, the second end outputs low level, so that the first inner tube and the second inner tube are turned off after the time delay. The invention can realize three-level turn-off sequential logic only through a simple circuit, and reduces the complexity and cost of circuit design.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to an I-type three-level circuit.
Background
The traditional circuit utilizes a complex programmable logic device (Complex Programming logic device, CPLD) to realize the turn-off sequential logic of the I type three level, and the CPLD needs to be programmed, so that the circuit design process is complex, and the cost is increased.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the invention provides an I-type three-level circuit.
The technical scheme adopted by the embodiment of the invention comprises the following steps:
a type I three level circuit comprising:
the switching tube circuit comprises a first outer tube, a second outer tube, a first inner tube and a second inner tube;
the controller comprises a first output module and a second output module, wherein the first output module is used for outputting a high level when the controller works and outputting a low level when the controller is turned off;
The charging and discharging module is used for charging when the high level is input into the first end and discharging when the low level is input into the first end; the high-voltage power supply is used for outputting a high level from the second end after charging and outputting a low level from the second end after discharging to a delay time;
The logic judging module comprises a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, wherein a first input end of the first AND gate is connected with the first output module, a second input end of the first AND gate is connected with the second output module, and an output end of the first AND gate is used for turning off the first outer tube when outputting low level; the first input end of the second AND gate is connected with the second output module, the second input end of the second AND gate is connected with the second end of the charge-discharge module, and the output end of the second AND gate is used for turning off the first inner tube when outputting low level; the first input end of the third AND gate is connected with the second output module, the second input end of the third AND gate is connected with the second end of the charge-discharge module, and the output end of the third AND gate is used for turning off the second inner tube when outputting low level; the first input end of the fourth AND gate is connected with the first output module, the second input end of the fourth AND gate is connected with the second output module, and the output end of the fourth AND gate is used for cutting off the second outer tube when outputting low level.
As an alternative embodiment, the controller is a digital signal processor, and the second output module is a PWM module.
As an alternative embodiment, the second output module includes a first PWM port, a second PWM port, a third PWM port, and a fourth PWM port;
The first PWM port is connected with the second input end of the first AND gate, the second PWM port is connected with the first input end of the second AND gate, the third PWM port is connected with the first input end of the third AND gate, and the fourth PWM port is connected with the second input end of the fourth AND gate.
As an optional implementation manner, the charge-discharge module includes a power supply, a first resistor, a second resistor, a first capacitor and a triode, wherein a base electrode of the triode is a first end of the charge-discharge module, and an emitter electrode of the triode is a second end of the charge-discharge module;
The power supply is connected with the first end of the first resistor, the second end of the first resistor is connected with the emitting electrode of the triode, the collecting electrode of the triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the first capacitor, the first end of the first capacitor is grounded, and the second end of the first capacitor is connected with the second end of the first resistor.
As an optional implementation manner, the I-type three-level circuit further comprises a driver module, wherein the driver module is used for performing driving control on the switching tube circuit, and comprises a first driver, a second driver, a third driver and a fourth driver;
The input end of the first driver is connected with the output end of the first AND gate, and the output end of the first driver is connected with the base electrode of the first outer tube; the input end of the second driver is connected with the output end of the second AND gate, and the output end of the second driver is connected with the base electrode of the first inner tube; the input end of the third driver is connected with the output end of the third AND gate, and the output end of the third driver is connected with the base electrode of the second inner tube; the input end of the fourth driver is connected with the output end of the fourth AND gate, and the output end of the fourth driver is connected with the base electrode of the second outer tube.
As an alternative embodiment, the switching tube circuit includes a second capacitor, a third capacitor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode;
The collector of the first outer tube is connected with the first end of the first diode, the second end of the first diode is connected with the emitter of the first outer tube, the emitter of the first outer tube is connected with the collector of the first inner tube, the collector of the first inner tube is connected with the first end of the second diode, the second end of the second diode is connected with the emitter of the first inner tube, the emitter of the first inner tube is connected with the collector of the second inner tube, the collector of the second inner tube is connected with the first end of the third diode, the second end of the third diode is connected with the emitter of the second inner tube, the emitter of the second inner tube is connected with the collector of the second outer tube, the collector of the second outer tube is connected with the first end of the fourth diode, the second end of the fourth diode is connected with the emitter of the second outer tube, the second end of the second outer tube is connected with the second end of the third capacitor, the second end of the third capacitor is connected with the second end of the second outer tube, the second end of the second outer tube is connected with the second end of the fourth capacitor.
The advantages and benefits of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
The I-type three-level circuit provided by the embodiment of the invention is provided with the controller, the charge-discharge module and the logic judgment module consisting of the AND gates, wherein the controller outputs high level through the first output module when in a working state, so that the charge-discharge module starts charging, and inputs high level to the second input end of the second AND gate and the second input end of the third AND gate after charging. Meanwhile, the first input ends of the first AND gate and the fourth AND gate are connected with the first output module, so that a first outer tube controlled by the first AND gate, a first inner tube controlled by the second AND gate, a second inner tube controlled by the third AND gate and a second outer tube controlled by the fourth AND gate are in a working state when the controller works; when the controller is turned off, the first output module outputs low level, the first AND gate and the fourth AND gate output low level, and the first outer pipe and the second outer pipe are turned off. Meanwhile, the low level output by the first output module enables the charge-discharge module to start discharging, when the charge-discharge module discharges to delay time, the low level is output from the second end, and the second AND gate and the third AND gate output the low level, so that the first inner pipe and the second inner pipe are turned off, namely, the invention can realize three-level turn-off sequential logic only through a simple circuit without adopting CPLD programming, and the complexity and the cost of circuit design are reduced.
Drawings
Fig. 1 is a schematic circuit connection diagram of a type I three-level circuit according to an embodiment of the invention.
Reference numerals: 101. a switching tube circuit; 102. a charge-discharge module; 103. a logic judgment module; 104. a driver module; t1, a first outer tube; t2, a first inner tube; t3, a second inner tube; t4, a second outer tube; u1, a controller; GPIO and a first output module; a PWM and second output module; U2A, a first AND gate; U2B, a second AND gate; U2C, third AND gate; U2D, a fourth AND gate; PWM1A, the first PWM port; PWM2B, second PWM port; PWM1B, third PWM port; PWM2A, fourth PWM port; VCC, power supply; r1, a first resistor; r2, a second resistor; c1, a first capacitor; q1, triode; DRV1, a first driver; DRV2, second driver; DRV3, third driver; DRV4, fourth driver; c2, a second capacitor; c3, a third capacitor; d1, a first diode; d2, a second diode; d3, a third diode; d4, a fourth diode; d5, a fifth diode; d6, a sixth diode.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The type I three-level turn-off sequential logic is as follows: for four switching tubes in one bridge arm, when the switching tubes are turned off, the outer tube needs to be turned off before the inner tube.
The traditional circuit utilizes CPLD to realize the turn-off sequential logic of I type three level, and programming is needed to be carried out on the CPLD, so that the circuit design process is complex, and the cost is increased. Therefore, the embodiment of the invention provides an I-type three-level circuit, which is provided with a controller, a charge-discharge module and a logic judgment module consisting of an AND gate, wherein the controller outputs a high level through a first output module when in a working state, so that the charge-discharge module starts charging, and inputs the high level to a second input end of a second AND gate and a second input end of a third AND gate after charging. Meanwhile, the first input ends of the first AND gate and the fourth AND gate are connected with the first output module, so that a first outer tube controlled by the first AND gate, a first inner tube controlled by the second AND gate, a second inner tube controlled by the third AND gate and a second outer tube controlled by the fourth AND gate are in a working state when the controller works; when the controller is turned off, the first output module outputs low level, the first AND gate and the fourth AND gate output low level, and the first outer pipe and the second outer pipe are turned off. Meanwhile, the low level output by the first output module enables the charge-discharge module to start discharging, when the charge-discharge module discharges to delay time, the low level is output from the second end, and the second AND gate and the third AND gate output the low level, so that the first inner pipe and the second inner pipe are turned off, namely, the invention can realize three-level turn-off sequential logic only through a simple circuit without adopting CPLD programming, and the complexity and the cost of circuit design are reduced.
As shown in fig. 1, an embodiment of the present invention provides an I-type three-level circuit, including:
a switching tube circuit 101 including a first outer tube T1, a second outer tube T4, a first inner tube T2, and a second inner tube T3;
The controller U1 comprises a first output module GPIO and a second output module PWM, wherein the first output module GPIO is used for outputting a high level when the controller U1 works and outputting a low level when the controller U1 is turned off;
The charging and discharging module 102, wherein a first end of the charging and discharging module 102 is connected with the first output module GPIO, and the charging and discharging module 102 is used for charging when a high level is input into the first end and discharging when a low level is input into the first end; the high-voltage power supply is used for outputting a high level from the second end after charging and outputting a low level from the second end after discharging to a delay time;
The logic judging module 103 comprises a first and gate U2A, a second and gate U2B, a third and gate U2C and a fourth and gate U2D, wherein a first input end of the first and gate U2A is connected with the first output module GPIO, a second input end of the first and gate U2A is connected with the second output module PWM, and an output end of the first and gate U2A is used for turning off the first outer tube T1 when outputting a low level; the first input end of the second and gate U2B is connected to the second output module PWM, the second input end of the second and gate is connected to the second end of the charge-discharge module 102, and the output end of the second and gate U2B is used to turn off the first inner tube T2 when outputting a low level; the first input end of the third and gate U2C is connected to the second output module PWM, the second input end of the third and gate U2C is connected to the second end of the charge-discharge module 102, and the output end of the third and gate U2C is configured to turn off the second inner tube T3 when outputting a low level; the first input end of the fourth and gate U2D is connected to the first output module GPIO, the second input end of the fourth and gate U2D is connected to the second output module PWM, and the output end of the fourth and gate U2D is configured to turn off the second outer tube T4 when outputting a low level.
Specifically, when the controller U1 is in normal operation, a high level is output through the first output module GPIO, that is, the first input end of the first and gate U2A and the first input end of the fourth and gate U2D are in a high level, at this time, the first and gate U2A and the fourth and gate U2D control the output signals of the output ends by the output signals of the second output module PWM, that is, the controller U1 controls the output signals of the second output module PWM to realize the on/off control of the first outer tube T1 and the second outer tube T4; meanwhile, as the charge-discharge module 102 charges at the high level output by the first output module GPIO, the charge-discharge module 102 outputs the high level at the second end, so that the second input end of the second and gate U2B and the second input end of the third and gate U2C are at the high level, and at this time, the second and gate U2B and the third and gate U2C control the output signals of the output ends by the output signals of the second output module PWM, that is, the controller U1 controls the output signals of the second output module PWM to realize the on/off control of the first inner tube T2 and the second inner tube T3. It can be understood that when the controller U1 controls the second output module PWM to output a high level, the first outer tube T1, the second outer tube T4, the first inner tube T2 and the second inner tube T3 are turned on.
When the controller U1 is turned off, a low level is output through the first output module GPIO, namely the first input end of the first AND gate U2A and the first input end of the fourth AND gate U2D are low levels, at the moment, the output ends of the first AND gate U2A and the fourth AND gate U2D output low levels, and the first outer pipe T1 and the second outer pipe T4 are turned off; meanwhile, as the charge-discharge module 102 discharges under the low level output by the first output module GPIO, the charge-discharge module 102 discharges to the delay time and then outputs the low level at the second end, so that the second input end of the second and gate U2B and the second input end of the third and gate U2C are low, at this time, the output ends of the second and gate U2B and the third and gate U2C output the low level, that is, the first inner tube T2 and the second inner tube T3 are turned off again after the first outer tube T1 and the second outer tube T4 are turned off after the delay time, thereby realizing the three-level turn-off sequential logic.
As an alternative embodiment, the controller U1 is a digital signal Processor (DIGITAL SIGNAL Processor, DSP), and the second output module PWM is a PWM module.
Optionally, the controller U1 selects a DSP with a model TMS320F28374S, and outputs a Fault signal by using a general purpose input output interface (General Purpose Input Output, GPIO) of the controller U1 (the first output module GPIO outputs a high level when the controller U1 works and outputs a low level when the controller U1 is turned off).
As an alternative embodiment, the second output module PWM includes a first PWM port PWM1A, a second PWM port PWM2B, a third PWM port PWM1B, and a fourth PWM port PWM2A;
The first PWM port PWM1A is connected to the second input end of the first and gate U2A, the second PWM port PWM2B is connected to the first input end of the second and gate U2B, the third PWM port PWM1B is connected to the first input end of the third and gate U2C, and the fourth PWM port PWM2A is connected to the second input end of the fourth and gate U2D.
As can be seen, when the controller U1 is operated, the first outer tube T1, the second outer tube T4, the first inner tube T2 and the second inner tube T3 can be respectively turned on/off by controlling the output signals of the first PWM port PWM1A, the second PWM port PWM2B, the third PWM port PWM1B and the fourth PWM port PWM 2A.
As an alternative embodiment, the charge-discharge module 102 includes a power source VCC, a first resistor R1, a second resistor R2, a first capacitor C1, and a transistor Q1, where a base electrode of the transistor Q1 is a first end of the charge-discharge module 102, and an emitter electrode of the transistor Q1 is a second end of the charge-discharge module 102;
The power VCC is connected with a first end of a first resistor R1, a second end of the first resistor R1 is connected with an emitter of a triode Q1, a collector of the triode Q1 is connected with a first end of a second resistor R2, a second end of the second resistor R2 is connected with a first end of a first capacitor C1, a first end of the first capacitor C1 is grounded, and a second end of the first capacitor C1 is connected with a second end of the first resistor R1.
Specifically, when the first output module GPIO outputs a high level, the transistor Q1 is turned off, and the power VCC charges the first capacitor C1 through the first resistor R1, that is, the charge-discharge circuit 101 is in a charged state; when the first output module GPIO outputs a low level, the transistor Q1 is turned on, the first capacitor C1 begins to discharge, and the discharge current flows through the second resistor R2 to the ground, that is, the charge-discharge current 102 is in a discharge state. When the first capacitor C1 is discharged to the delay time, a low level is output from the emitter (the second terminal of the charge-discharge circuit 102) of the transistor Q1.
Delay time:
Wherein V 1L is the low level threshold of the first and gate U2A, the second and gate U2B, the third and gate U2C and the fourth and gate U2D, and V CEsat is the saturation voltage drop of the triode Q1.
In combination with the foregoing, when the controller U1 is turned off, the first inner tube T2 and the second inner tube T3 are turned off after the first outer tube T1 and the second outer tube T4 are turned off, and then are turned off after the delay time T.
As an alternative embodiment, the type I three-level circuit further includes a driver module 104, where the driver module 104 is configured to perform driving control on the switching tube circuit 101, and the driver module 104 includes a first driver DRV1, a second driver DRV2, a third driver DRV3, and a fourth driver DRV4;
the input end of the first driver DRV1 is connected with the output end of the first AND gate U2A, and the output end of the first driver DRV1 is connected with the base electrode of the first outer tube T1; the input end of the second driver DRV2 is connected with the output end of the second AND gate U2B, and the output end of the second driver DRV2 is connected with the base electrode of the first inner tube T2; the input end of the third driver DRV3 is connected with the output end of the third AND gate U2C, and the output end of the third driver DRV3 is connected with the base electrode of the second inner tube T3; the input end of the fourth driver DRV4 is connected to the output end of the fourth and gate U2D, and the output end of the fourth driver DRV4 is connected to the base of the second external tube T4.
Specifically, the first outer tube T1 is drive-controlled by the first driver DRV1, the first inner tube T2 is drive-controlled by the second driver DRV2, the second inner tube T3 is drive-controlled by the third driver DRV3, and the second outer tube T4 is drive-controlled by the fourth driver DRV 4.
As an alternative embodiment, the switching tube circuit 101 includes a second capacitor C2, a third capacitor C3, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6;
The collector of the first outer tube T1 is connected to the first end of the first diode D1, the second end of the first diode D1 is connected to the emitter of the first outer tube T1, the emitter of the first outer tube T1 is connected to the collector of the first inner tube T2, the collector of the first inner tube T2 is connected to the first end of the second diode D2, the second end of the second diode D2 is connected to the emitter of the first inner tube T2, the emitter of the first inner tube T2 is connected to the collector of the second inner tube T3, the collector of the second inner tube T3 is connected to the first end of the third diode D3, the second end of the third diode D3 is connected to the emitter of the second inner tube T3, the emitter of the second inner tube T3 is connected to the collector of the second outer tube T4, the second outer tube T4 is connected to the first end of the fourth diode D4, the second end of the second outer tube T4 is connected to the second end of the second outer tube T2, the second end of the third outer tube T4 is connected to the second end of the third outer tube T4, the second end of the third outer tube T4 is connected to the third end of the third outer tube T4, the third end of the third outer tube T4 is connected to the third end of the third capacitor D4.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the embodiments described above, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (5)
1. A type I three level circuit comprising:
the switching tube circuit comprises a first outer tube, a second outer tube, a first inner tube and a second inner tube;
the controller comprises a first output module and a second output module, wherein the first output module is used for outputting a high level when the controller works and outputting a low level when the controller is turned off;
The charging and discharging module is used for charging when the high level is input into the first end and discharging when the low level is input into the first end; the high-voltage power supply is used for outputting a high level from the second end after charging and outputting a low level from the second end after discharging to a delay time;
The logic judging module comprises a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, wherein a first input end of the first AND gate is connected with the first output module, a second input end of the first AND gate is connected with the second output module, and an output end of the first AND gate is used for turning off the first outer tube when outputting low level; the first input end of the second AND gate is connected with the second output module, the second input end of the second AND gate is connected with the second end of the charge-discharge module, and the output end of the second AND gate is used for turning off the first inner tube when outputting low level; the first input end of the third AND gate is connected with the second output module, the second input end of the third AND gate is connected with the second end of the charge-discharge module, and the output end of the third AND gate is used for turning off the second inner tube when outputting low level; the first input end of the fourth AND gate is connected with the first output module, the second input end of the fourth AND gate is connected with the second output module, and the output end of the fourth AND gate is used for turning off the second outer tube when outputting low level;
the charging and discharging module comprises a power supply, a first resistor, a second resistor, a first capacitor and a triode, wherein the base electrode of the triode is the first end of the charging and discharging module, and the emitting electrode of the triode is the second end of the charging and discharging module;
The power supply is connected with the first end of the first resistor, the second end of the first resistor is connected with the emitting electrode of the triode, the collecting electrode of the triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the first capacitor, the first end of the first capacitor is grounded, and the second end of the first capacitor is connected with the second end of the first resistor.
2. The type I three level circuit of claim 1, wherein the controller is a digital signal processor and the second output module is a PWM module.
3. A type I three level circuit according to claim 2, wherein said second output module comprises a first PWM port, a second PWM port, a third PWM port and a fourth PWM port;
The first PWM port is connected with the second input end of the first AND gate, the second PWM port is connected with the first input end of the second AND gate, the third PWM port is connected with the first input end of the third AND gate, and the fourth PWM port is connected with the second input end of the fourth AND gate.
4. The type I three level circuit of claim 1, further comprising a driver module for driving control of the switching tube circuit, the driver module comprising a first driver, a second driver, a third driver, and a fourth driver;
The input end of the first driver is connected with the output end of the first AND gate, and the output end of the first driver is connected with the base electrode of the first outer tube; the input end of the second driver is connected with the output end of the second AND gate, and the output end of the second driver is connected with the base electrode of the first inner tube; the input end of the third driver is connected with the output end of the third AND gate, and the output end of the third driver is connected with the base electrode of the second inner tube; the input end of the fourth driver is connected with the output end of the fourth AND gate, and the output end of the fourth driver is connected with the base electrode of the second outer tube.
5. The type I three level circuit of claim 4, wherein the switching tube circuit comprises a second capacitor, a third capacitor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode;
The collector of the first outer tube is connected with the first end of the first diode, the second end of the first diode is connected with the emitter of the first outer tube, the emitter of the first outer tube is connected with the collector of the first inner tube, the collector of the first inner tube is connected with the first end of the second diode, the second end of the second diode is connected with the emitter of the first inner tube, the emitter of the first inner tube is connected with the collector of the second inner tube, the collector of the second inner tube is connected with the first end of the third diode, the second end of the third diode is connected with the emitter of the second inner tube, the emitter of the second inner tube is connected with the collector of the second outer tube, the collector of the second outer tube is connected with the first end of the fourth diode, the second end of the fourth diode is connected with the emitter of the second outer tube, the second end of the second outer tube is connected with the second end of the third capacitor, the second end of the third capacitor is connected with the second end of the second outer tube, the second end of the second outer tube is connected with the second end of the fourth capacitor.
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| CN110299696B (en) * | 2019-06-21 | 2021-10-01 | 漳州科华技术有限责任公司 | T-shaped three-level converter and short-circuit protection circuit thereof |
| CN111049408B (en) * | 2020-01-06 | 2020-10-13 | 山东华天电气有限公司 | I-type three-level driving time sequence protection circuit |
| CN111478609B (en) * | 2020-05-19 | 2021-05-04 | 深圳科士达科技股份有限公司 | Active neutral point clamping type three-level converter and control method and control device thereof |
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