CN111585251A - Short-circuit protection device and method for I-type three-level APF - Google Patents

Abstract

The invention provides a short-circuit protection device and a short-circuit protection method for I-type three-level APF (active power filter), which can close an outer tube and then close an inner tube to realize short-circuit protection; the circuit comprises a topology circuit, wherein the topology circuit comprises IGBT tubes T1-T4, freewheeling diodes D1-D4, clamping diodes D5 and D6, the IGBT tubes T1 and T4 are used as outer tubes, the IGBT tubes T2 and T3 are used as inner tubes, the circuit further comprises a short-circuit fault detection circuit, a fault signal logic circuit and a driving signal logic circuit, the short-circuit fault detection circuit is connected between a collector and an emitter of the IGBT tubes, the output ends of the short-circuit fault detection circuit are connected with the input end of the fault signal logic circuit, and the output end of the fault signal logic circuit is connected with the input end of the driving signal logic circuit; the short-circuit fault detection circuit is used for generating a fault signal corresponding to the IGBT tube; the fault signal logic circuit is used for summarizing fault signals sent by the IGBT tubes T1-T4 to generate a total fault signal; and the driving signal logic circuit is used for realizing delayed turn-off of the IGBT tube T2 and the IGBT tube T3 serving as inner tubes.

Description

Short-circuit protection device and method for I-type three-level APF

Technical Field

The invention relates to the technical field of power electronics, in particular to a short-circuit protection device and a short-circuit protection method for an I-type three-level APF.

Background

With the continuous development of solar energy and UPS technology and the continuous expansion of the market, the requirement on the efficiency of the inverter is more and more emphasized by manufacturers, therefore, a three-level topological structure is produced at the same time, and as is well known, compared with the traditional two-level structure, the three-level structure has the advantages of small harmonic wave, low loss, high efficiency and the like besides halving the blocking voltage of a single IGBT (insulated gate bipolar transistor), so that the three-level APF is widely applied; in practical application, when short-circuit fault or overcurrent fault occurs, the outer tube needs to be turned off first, and then the inner tube needs to be turned off, so that the reason for the operation is as follows:

(1) the voltage of a single IGBT tube is not very high, the highest common voltage is 650V, and the voltage of the single IGBT tube can not reach 1200V or even 1700V of the two-level IGBT, and taking industrial three-phase 400V level voltage as an example, the rectified voltage on the direct current side of a three-level system reaches 653V, and in practical application, the bus voltage generally exceeds 750V;

(2) if the inner tube is turned off first, the IGBT of the inner tube bears the voltage of the whole bus, the inner tube is damaged due to overvoltage, the IGBT is usually broken due to overvoltage, and the condition of module explosion can be caused subsequently;

(3) if two outer tubes are turned off first, the voltage of the outer tube can be clamped on half of the bus voltage, the risk of overvoltage is avoided, and the inner tube can be turned off safely.

The traditional fault protection method of the I-type three-level APF is that a short-circuit protection detection module in a drive IC chip can immediately close a fault tube after detecting a fault signal, simultaneously transmit the fault signal to an MCU (microprogrammed control unit) to trigger interruption, the MCU closes the rest tubes, and the delay of signal transmission and the time of interruption response are generally dozens of microseconds or even longer; however, when a short circuit occurs in the inner tube, the inner tube is turned off by itself, and it is impossible to turn off the outer tube first and then turn off the inner tube.

Disclosure of Invention

In order to solve the problems, the invention provides a short-circuit protection device for an I-type three-level APF, which can close an outer tube and then close an inner tube to realize short-circuit protection.

The technical scheme is that the short-circuit protection device for the I-type three-level APF comprises a topological circuit, wherein the topological circuit comprises IGBT tubes T1, T2, T3 and T4, freewheeling diodes D1, D2, D3 and D4, clamping diodes D5 and D6, the IGBT tubes T1 and T4 are used as outer tubes, and the IGBT tubes T2 and T3 are used as inner tubes, and the short-circuit protection device is characterized in that: the IGBT power supply circuit further comprises a short-circuit fault detection circuit, a fault signal logic circuit and a driving signal logic circuit, wherein the short-circuit fault detection circuit is connected between a collector and an emitter of each IGBT tube, an output end of the short-circuit fault detection circuit is connected to an input end of the fault signal logic circuit, and an output end of the fault signal logic circuit is connected with an input end of the driving signal logic circuit;

the short-circuit fault detection circuit is used for generating a fault signal of the corresponding IGBT tube;

the fault signal logic circuit is used for summarizing fault signals sent by the IGBT tubes T1, T2, T3 and T4 to generate a total fault signal;

and the driving signal logic circuit is used for realizing delayed turn-off of the IGBT tube T2 and the IGBT tube T3 which are used as inner tubes.

It is further characterized in that:

the topology circuit further comprises capacitors C1, C2 and an inductor L1, wherein a collector of the IGBT tube T1 is connected with a positive electrode end of the capacitor C1 and a negative electrode of a freewheeling diode D1, a negative electrode end of the capacitor C1 is connected with a positive electrode end of the capacitor C2, a positive electrode of a clamping diode D5 and a negative electrode of a clamping diode D6, an anode of the clamping diode D5 and a negative electrode of the clamping diode D6 are connected, a negative electrode end of the capacitor C2 is connected with an emitter of the IGBT tube T4 and a negative electrode of the freewheeling diode D4, an emitter of the IGBT tube T1 is connected with an anode of the freewheeling diode D1, a cathode of the freewheeling diode D2, a negative electrode of the clamping diode D5 and a collector of an IGBT tube T2, an emitter of the IGBT tube T2 is connected with an anode of the freewheeling diode D2, a negative electrode of the freewheeling diode D3, a collector of the IGBT tube T3 and one end of the inductor L1, the emitter of the IGBT tube T3 is connected with the freewheeling diode D3, the anode of the clamping diode D6, the cathode of the freewheeling diode D4 and the collector of the IGBT tube T4, and the gates of the IGBT tubes T1, T2, T3 and T4 are used as pulse width modulation signal terminals and are divided into PWM1, PWM2, PWM3 and PWM 4;

each short-circuit fault detection circuit comprises a constant current source I1, a comparator U1, an inverter U2, U3, a capacitor C3, a voltage regulator tube VD1, a current-limiting resistor R1, a diode D7 and an MOS tube Q1, wherein the output end of the inverter U2 is used as the fault signal output end of the short-circuit fault detection circuit, one end of the constant current source I1 is connected with the positive input end of the comparator U1, one end of the capacitor C3, one end of a resistor R1, the negative electrode of the voltage regulator tube VD1 and the drain electrode of the MOS tube Q1, the other end of the constant current source I1 is grounded, the other end of the resistor R1 is connected with the collector electrode of the IGBT tube through the diode D7, the other end of the capacitor C3 is connected with the positive electrode of the voltage regulator tube VD1 and then connected with the emitter electrode of the IGBT tube, the input end of the inverter U2 is connected with the output end of the comparator U2, the source electrode of the MOS tube Q1 is grounded, and the negative input end of the comparator U1 is connected with a preset short-circuit protection voltage V0;

the fault signal logic circuit comprises AND gates U1A, U1B and U1C, fault signals generated by the short-circuit fault detection circuits corresponding to the IGBT tubes T1 and T2 are connected to the input end of the AND gate U1A, fault signals generated by the short-circuit fault detection circuits corresponding to the IGBT tubes T3 and T4 are connected to the input end of the AND gate U1B, output ends of the AND gates U1A and U1B are connected to the input end of the AND gate U1C, and the output end of the AND gate U1C is used as a total fault signal end;

the driving signal logic circuit comprises AND gates U2A, U2B, U2C, U2D and a Delay unit Delay1, wherein the Delay unit Delay1 is used for generating a Delay signal; the input end of the and gate U2A is respectively connected to the total fault signal generated by the fault signal logic circuit and the pulse width input signal PWM _1 corresponding to the IGBT tube T1, and the pulse width modulation signal PWM1 is generated after the sum fault signal and the pulse width input signal PWM _1 corresponding to the IGBT tube T1 are subjected to an and operation, the input end of the and gate U2B is respectively connected to the total fault signal generated by the fault signal logic circuit and the pulse width input signal PWM _4 corresponding to the IGBT tube T4, and the pulse width modulation signal PWM4 is generated after the sum fault signal and the pulse width input signal PWM _4 corresponding to the IGBT tube T4 are subjected to an and operation, the input end of the and gate U2C is respectively connected to the pulse width input signal PWM _2 corresponding to the IGBT tube T2 and the total fault signal delayed by the Delay unit Delay1, and the pulse width modulation signal PWM _2 and the total fault signal delayed by the Delay unit Delay1 are subjected to an and operation to generate the pulse width modulation signal PWM _2 and operation An input end of the and gate U2D is respectively connected to a pulse width input signal PWM _3 corresponding to the IGBT transistor T3 and the total fault signal delayed by the Delay unit Delay1, and the pulse width modulation signal PWM3 is generated after an and operation is performed on the pulse width input signal PWM _3 and the total fault signal delayed by the Delay unit Delay 1;

the Delay unit Delay1 delays the maximum short-circuit time not exceeding the maximum short-circuit time allowed by the IGBT tube.

A short-circuit protection method for I-type three-level APF is characterized in that: which comprises the following steps:

s1, detecting saturation voltage drops of the IGBT tubes after T1, T2, T3 and T4 are switched on correspondingly through the short-circuit fault detection circuit respectively, wherein if short-circuit occurs, the corresponding saturation voltage drops are increased, and after a set threshold value is reached, fault signals of the corresponding IGBT tubes are subjected to level inversion;

after the fault signals of the S2 and the IGBT tubes T1, T2, T3 and T4 are correspondingly connected to the fault signal logic circuit, as long as the IGBT tubes have faults, a total fault signal is finally generated, and the level of the total fault signal is reversed;

and S3, when the total fault signal level is reversed, the pulse width modulation signal PWM1 and the pulse width modulation signal PWM4 are pulled low to be turned off, and because the front-stage input ends of the AND gates U2C and U2D are both connected with the Delay unit Delay1, the pulse width modulation signal PWM2 and the pulse width modulation signal PWM3 corresponding to the IGBT tubes T2 and T3 are turned off in a delayed manner, so that the outer tube is turned off first, and the inner tube is turned off later.

The invention has the advantages that by arranging the short-circuit fault detection circuit, the fault signal logic circuit and the driving signal logic circuit, when short circuit occurs, the IGBT tube T2 and the IGBT tube T3 which are used as the inner tube can be turned off in a delayed way, so that the purposes of first turning off the outer tube, then turning off the inner tube and short-circuit protection are realized, and the invention has better economic use value.

Drawings

FIG. 1 is a circuit schematic of the topology circuit of the present invention;

fig. 2 is a schematic circuit diagram of a short-circuit fault detection circuit for detecting an IGBT transistor T1 according to the present invention;

FIG. 3 is a circuit schematic of the fault signaling logic circuit of the present invention;

fig. 4 is a circuit schematic of the drive signal logic circuit of the present invention.

Detailed Description

As shown in fig. 1 to 4, the short-circuit protection device for I-type three-level APF includes a topology circuit, the topology circuit includes IGBT transistors T1, T2, T3, T4, freewheeling diodes D1, D2, D3, D4, clamp diodes D5, D6 connected in series in sequence, the IGBT transistors T1, and IGBT transistors T4 are used as outer tubes, the IGBT transistors T2, and IGBT transistors T3 are used as inner tubes, the short-circuit protection device further includes a short-circuit fault detection circuit, a fault signal logic circuit, and a driving signal logic circuit, a short-circuit fault detection circuit is connected between a collector and an emitter of each IGBT transistor, output ends of the short-circuit fault detection circuit are connected to input ends of the fault signal logic circuit, and output ends of the fault signal logic circuit are connected to input ends of the driving signal logic circuit;

the short-circuit fault Detection circuits are used for generating fault signals of corresponding IGBT tubes, and four short-circuit fault Detection circuits are respectively marked as short-circuit fault Detection circuits SC Detection 1, SC Detection2, SC Detection3 and SC Detection 4; FAULT signals sent by the IGBT tubes T1, T2, T3 and T4 are respectively recorded as FAULT1, FAULT2, FAULT3 and FAULT 4;

the FAULT signal logic circuit is used for summarizing FAULT signals sent by the IGBT transistors T1, T2, T3 and T4 to generate a total FAULT signal FAULT, in this embodiment, the total FAULT signal FAULT is active low, that is, in normal operation, the total FAULT signal FAULT is at a high level (logic 1), and changes to a low level (logic 0) in the event of a FAULT;

and the driving signal logic circuit is used for realizing delayed turn-off of the IGBT tube T2 and the IGBT tube T3 serving as inner tubes.

The topology circuit further comprises capacitors C1, C2 and an inductor L1, wherein the collector of an IGBT tube T1 is connected with the positive terminal of a capacitor C1 and the negative terminal of a freewheeling diode D1, the negative terminal of a capacitor C1 is connected with the positive terminal of a capacitor C2, the positive terminal of a clamp diode D5 and the negative terminal of a clamp diode D6, the positive terminal of a clamp diode D5 and the negative terminal of a clamp diode D6, the negative terminal of a capacitor C2 is connected with the emitter of an IGBT tube T4 and the negative terminal of a freewheeling diode D4, the emitter of an IGBT tube T1 is connected with the positive terminal of a freewheeling diode D1, the negative terminal of a clamp diode D1 and the collector of an IGBT tube T1, the emitter of the IGBT tube T1 is connected with the positive terminal of a freewheeling diode D1 and the positive terminal of a freewheeling diode D1, the freewheeling diode D1 and the collector of a freewheeling diode D1 are connected with the emitter of the IGBT tube T1 and the clamp diode D1, and the anode of, The negative electrode of the freewheeling diode D4 and the collector of the IGBT transistor T4 are connected, and the gates of the IGBT transistors T1, T2, T3, and T4 are pulse width modulation signal terminals, which are divided into PWM1, PWM2, PWM3, and PWM 4.

Each short-circuit fault detection circuit comprises a constant current source I1, a comparator U1, an inverter U2, a U3, a capacitor C3, a voltage regulator VD1, a current-limiting resistor R1, a diode D7 and a MOS tube Q1, the output end of the inverter U2 is used as a fault signal output end of the short-circuit fault detection circuit, one end of a constant current source I1 is connected with the positive input end of a comparator U1, one end of a capacitor C3, one end of a resistor R1, the negative electrode of a voltage regulator tube VD1 and the drain electrode of an MOS tube Q1, the other end of the constant current source I1 is grounded, the other end of the resistor R1 is connected with the collector electrode of the IGBT tube through a diode D7, the other end of the capacitor C3 is connected with the positive electrode of the voltage regulator tube VD1 and then connected with the emitter electrode of the IGBT tube, the input end of the inverter U2 is connected with the output end of a comparator U1, the gate electrode of the IGBT tube is connected with the input end of the inverter U3, the output end of the inverter U3 is connected with the gate electrode of the MOS tube Q1, the source;

taking the IGBT transistor T1 for example, as shown in fig. 2, when the PWM signal PWM1 is at a low level, the MOS transistor Q1 is turned on, and the "+" input terminal of the comparator U1 is shorted to GND; when the pulse width modulation signal PWM1 is at a high level (i.e., the IGBT tube T1 is turned on), the MOS tube Q1 is turned off, the constant current source I1 charges the capacitor C3, if the IGBT tube T1 has no short-circuit fault, the voltage at the A, B point (i.e., the saturation voltage drop of the IGBT tube T1) is lower than the preset short-circuit protection voltage V0, and the voltage of the capacitor C3 is charged to a certain extent, and is clamped by the diode D7 (the final voltage of the capacitor C3 is the voltage at the a point plus the forward voltage drop of the diode D7, which should be lower than the saturation voltage drop of the IGBT tube T1), and cannot rise continuously; if the short circuit phenomenon occurs, the IGBT tube T1 is desaturated, the voltage between A, B rises rapidly, the diode D7 is cut off reversely, the voltage of the point C3 of the capacitor is charged by the constant current source I1 and rises rapidly until the voltage exceeds the preset short-circuit protection voltage V0, the comparator U1 outputs a high level, and the FAULT signal FAULT1 output by the inverter U2 is overturned and becomes a low level; the diode D7 may also use a plurality of fast recovery diodes connected in series according to actual needs, so as to achieve a reduction in protection time.

The FAULT signal logic circuit comprises AND gates U1A, U1B and U1C, FAULT signals FAULT1 and FAULT2 generated by short-circuit FAULT detection circuits corresponding to IGBT tubes T1 and T2 are connected to the input end of the AND gate U1A, FAULT signals FAULT3 and FAULT4 generated by short-circuit FAULT detection circuits corresponding to IGBT tubes T3 and T4 are connected to the input end of the AND gate U1B, the output ends of the AND gates U1A and U1B are connected to the input end of the AND gate U1C, and the output end of the AND gate U1C is used as a total FAULT signal end.

The driving signal logic circuit comprises an AND gate U2A, a U2B, a U2C, a U2D, a Delay unit Delay1 and a Delay unit Delay1, and is used for generating a Delay signal after a total fault signal generated by the fault signal logic circuit is accessed, so that the IGBT tubes T2 and T3 are turned off in a delayed mode, and the Delay unit Delay1 can realize signal Delay through an existing software program or an existing Delay module; the input end of the and gate U2A is respectively connected to the total FAULT signal FAULT generated by the FAULT signal logic circuit and the pulse width input signal PWM _1 corresponding to the IGBT tube T1, and the pulse width modulation signal PWM1 is generated after the phase inversion operation of the total FAULT signal FAULT and the pulse width input signal PWM _1 corresponding to the IGBT tube T1, if the total FAULT signal FAULT is a high level (i.e., logic 1), the pulse width input signal PWM _1 and the total FAULT signal FAULT are not changed after the phase inversion operation, otherwise, when the total FAULT signal FAULT is a low level (logic 0), the pulse width input signal PWM _1 and the total FAULT signal FAULT are changed into a low level after the phase inversion operation, and the IGBT tube T1 cannot be turned on; the input end of the and gate U2B is respectively connected to the total FAULT signal FAULT generated by the FAULT signal logic circuit and the pulse width input signal PWM _4 corresponding to the IGBT tube T4, and generates a pulse width modulation signal PWM4 after the AND operation of the total FAULT signal FAULT and the pulse width input signal PWM _4 corresponding to the IGBT tube T4, the input end of the and gate U2C is respectively connected to the pulse width input signal PWM _2 corresponding to the IGBT transistor T2 and the total FAULT signal FAULT delayed by the Delay unit Delay1, and generates a pulse width modulation signal PWM2 after performing an and operation on the pulse width input signal PWM _2 and the total FAULT signal FAULT delayed by the Delay unit Delay1, the input end of the and gate U2D is respectively connected to the pulse width input signal PWM _3 corresponding to the IGBT transistor T3 and the total FAULT signal FAULT delayed by the Delay unit Delay1, and generating a pulse width modulation signal PWM3 after performing AND operation on the pulse width input signal PWM _3 and the total FAULT signal FAULT delayed by the Delay unit Delay 1; the Delay unit Delay1 delays the maximum short-circuit time not exceeding the allowable maximum short-circuit time of the IGBT tube; the pulse width input signals PWM _1, PWM _2, PWM _3, and PWM _4 are all signals generated by the system.

Short-circuit protection method for type I three-level APF, comprising the steps of:

s1, detecting saturation voltage drops of the IGBT tubes T1, T2, T3 and T4 after being switched on respectively and correspondingly through short-circuit fault Detection circuits SC Detection 1, SC Detection2, SC Detection3 and SCdetection4, wherein if short-circuit occurs, the corresponding saturation voltage drops can be increased, and after a set threshold value is reached, fault signals of the corresponding IGBT tubes can be subjected to level inversion, namely, high levels are changed into low levels;

after the FAULT signals of the S2, the IGBT tubes T1, T2, T3 and T4 are correspondingly connected to the FAULT signal logic circuit, as long as the IGBT tubes are in FAULT, namely one or more FAULT signals are turned over and are changed from high level to low level, a total FAULT signal FAULT is finally generated, and the level of the total FAULT signal FAULT is turned over;

s3, when the total FAULT signal FAULT changes from high level to low level, the pulse width modulation signal PWM1 and the pulse width modulation signal PWM4 are pulled low to be turned off, and because the front-stage input ends of the AND gates U2C and U2D are both connected with the Delay unit Delay1, the pulse width modulation signals PWM2 and PWM3 corresponding to the IGBT tubes T2 and T3 are turned off in a delayed manner, so that the outer tube is turned off first, and the inner tube is turned off later; the logic gate device has the characteristic of low delay (ps level), so that the delay of the whole short-circuit protection process is only the delay of signal transmission plus the delay of the logic gate device.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (7)

1. Short-circuit protection device for I-type three-level APF, comprising a topological circuit, wherein the topological circuit comprises IGBT tubes T1, T2, T3, T4, freewheeling diodes D1, D2, D3, D4 and clamping diodes D5, D6, the IGBT tubes T1 and T4 are used as outer tubes, the IGBT tubes T2 and T3 are used as inner tubes, and the short-circuit protection device is characterized in that: the IGBT power supply circuit further comprises a short-circuit fault detection circuit, a fault signal logic circuit and a driving signal logic circuit, wherein the short-circuit fault detection circuit is connected between a collector and an emitter of each IGBT tube, an output end of the short-circuit fault detection circuit is connected to an input end of the fault signal logic circuit, and an output end of the fault signal logic circuit is connected with an input end of the driving signal logic circuit;

the short-circuit fault detection circuit is used for generating a fault signal of the corresponding IGBT tube;

the fault signal logic circuit is used for summarizing fault signals sent by the IGBT tubes T1, T2, T3 and T4 to generate a total fault signal;

and the driving signal logic circuit is used for realizing delayed turn-off of the IGBT tube T2 and the IGBT tube T3 which are used as inner tubes.

2. The short circuit protection device for type I three-level APF according to claim 1, wherein: the topology circuit further comprises capacitors C1, C2 and an inductor L1, wherein a collector of the IGBT tube T1 is connected with a positive electrode end of the capacitor C1 and a negative electrode of a freewheeling diode D1, a negative electrode end of the capacitor C1 is connected with a positive electrode end of the capacitor C2, a positive electrode of a clamping diode D5 and a negative electrode of a clamping diode D6, an anode of the clamping diode D5 and a negative electrode of the clamping diode D6 are connected, a negative electrode end of the capacitor C2 is connected with an emitter of the IGBT tube T4 and a negative electrode of the freewheeling diode D4, an emitter of the IGBT tube T1 is connected with an anode of the freewheeling diode D1, a cathode of the freewheeling diode D2, a negative electrode of the clamping diode D5 and a collector of an IGBT tube T2, an emitter of the IGBT tube T2 is connected with an anode of the freewheeling diode D2, a negative electrode of the freewheeling diode D3, a collector of the IGBT tube T3 and one end of the inductor L1, the emitter of the IGBT tube T3 is connected with the freewheeling diode D3, the anode of the clamping diode D6, the cathode of the freewheeling diode D4 and the collector of the IGBT tube T4, and the gates of the IGBT tubes T1, T2, T3 and T4 are used as pulse width modulation signal terminals and are divided into PWM1, PWM2, PWM3 and PWM 4.

3. The short-circuit protection device for type I three-level APF according to claim 2, characterized in that: each short-circuit fault detection circuit comprises a constant current source I1, a comparator U1, an inverter U2, U3, a capacitor C3, a voltage regulator tube VD1, a current-limiting resistor R1, a diode D7 and an MOS tube Q1, wherein the output end of the inverter U2 is used as the fault signal output end of the short-circuit fault detection circuit, one end of the constant current source I1 is connected with the positive input end of the comparator U1, one end of the capacitor C3, one end of a resistor R1, the negative electrode of the voltage regulator tube VD1 and the drain electrode of the MOS tube Q1, the other end of the constant current source I1 is grounded, the other end of the resistor R1 is connected with the collector electrode of the IGBT tube through the diode D7, the other end of the capacitor C3 is connected with the positive electrode of the voltage regulator tube VD1 and then connected with the emitter electrode of the IGBT tube, the input end of the inverter U2 is connected with the output end of the comparator U2, the source electrode of the MOS transistor Q1 is grounded, and the negative input end of the comparator U1 is connected with a preset short-circuit protection voltage V0.

4. The short circuit protection device for type I three-level APF according to claim 3, wherein: the fault signal logic circuit comprises AND gates U1A, U1B and U1C, fault signals generated by the short-circuit fault detection circuits corresponding to the IGBT tubes T1 and T2 are connected to the input end of the AND gate U1A, fault signals generated by the short-circuit fault detection circuits corresponding to the IGBT tubes T3 and T4 are connected to the input end of the AND gate U1B, output ends of the AND gates U1A and U1B are connected to the input end of the AND gate U1C, and the output end of the AND gate U1C serves as a total fault signal end.

5. The short-circuit protection device for type-I three-level APF according to claim 4, wherein: the driving signal logic circuit comprises AND gates U2A, U2B, U2C, U2D and a Delay unit Delay1, wherein the Delay unit Delay1 is used for generating a Delay signal; the input end of the and gate U2A is respectively connected to the total fault signal generated by the fault signal logic circuit and the pulse width input signal PWM _1 corresponding to the IGBT tube T1, and the pulse width modulation signal PWM1 is generated after the sum fault signal and the pulse width input signal PWM _1 corresponding to the IGBT tube T1 are subjected to an and operation, the input end of the and gate U2B is respectively connected to the total fault signal generated by the fault signal logic circuit and the pulse width input signal PWM _4 corresponding to the IGBT tube T4, and the pulse width modulation signal PWM4 is generated after the sum fault signal and the pulse width input signal PWM _4 corresponding to the IGBT tube T4 are subjected to an and operation, the input end of the and gate U2C is respectively connected to the pulse width input signal PWM _2 corresponding to the IGBT tube T2 and the total fault signal delayed by the Delay unit Delay1, and the pulse width modulation signal PWM _2 and the total fault signal delayed by the Delay unit Delay1 are subjected to an and operation to generate the pulse width modulation signal PWM _2 and operation An input end of the and gate U2D is respectively connected to a pulse width input signal PWM _3 corresponding to the IGBT transistor T3 and the total fault signal delayed by the Delay unit Delay1, and the pulse width modulation signal PWM3 is generated after an and operation is performed on the pulse width input signal PWM _3 and the total fault signal delayed by the Delay unit Delay 1.

6. The short-circuit protection device for type-I three-level APF according to claim 5, wherein: the Delay unit Delay1 delays the maximum short-circuit time not exceeding the maximum short-circuit time allowed by the IGBT tube.

7. The short-circuit protection method for the type-I three-level APF using the short-circuit protection device for the type-I three-level APF according to any one of claims 1 to 6, characterized in that: which comprises the following steps:

s1, detecting saturation voltage drops of the IGBT tubes after T1, T2, T3 and T4 are switched on correspondingly through the short-circuit fault detection circuit respectively, wherein if short-circuit occurs, the corresponding saturation voltage drops are increased, and after a set threshold value is reached, fault signals of the corresponding IGBT tubes are subjected to level inversion;

after the fault signals of the S2 and the IGBT tubes T1, T2, T3 and T4 are correspondingly connected to the fault signal logic circuit, as long as the IGBT tubes have faults, a total fault signal is finally generated, and the level of the total fault signal is reversed;

and S3, when the total fault signal level is reversed, the pulse width modulation signal PWM1 and the pulse width modulation signal PWM4 are pulled low to be turned off, and because the front-stage input ends of the AND gates U2C and U2D are both connected with the Delay unit Delay1, the pulse width modulation signal PWM2 and the pulse width modulation signal PWM3 corresponding to the IGBT tubes T2 and T3 are turned off in a delayed manner, so that the outer tube is turned off first, and the inner tube is turned off later.

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