CN114793471A

CN114793471A - Three-dimensional memory device and method of manufacturing the same

Info

Publication number: CN114793471A
Application number: CN202280001144.1A
Authority: CN
Inventors: 张恒; 刘峻; 雷威锋
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-07-26
Also published as: WO2023168696A1

Abstract

In certain aspects, a memory device includes a plurality of bottom Phase Change Memory (PCM) cells, a plurality of top PCM cells on the plurality of bottom PCM cells, a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in plan view, a plurality of top dummy cells on the plurality of bottom dummy cells, a first gap fill layer between adjacent bottom PCM cells, a second gap fill layer at least partially surrounding the plurality of bottom PCM cells in plan view, a third gap fill layer between adjacent top PCM cells, and a fourth gap fill layer at least partially surrounding the plurality of top PCM cells in plan view.

Description

Three-dimensional memory device and method of manufacturing the same

Background

The present disclosure relates to three-dimensional (3D) memory devices, layouts, and methods of manufacturing the same.

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, Phase Change Memories (PCMs) may utilize the difference between the resistivities of the amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material. The PCM array cells may be vertically stacked in a 3D manner to form a 3D PCM device.

The layout configuration of the peripheral devices in the storage device corresponds to the pattern and arrangement of a plurality of peripheral units or components therein.

Disclosure of Invention

According to one aspect, a memory device includes a plurality of bottom Phase Change Memory (PCM) cells, a plurality of top PCM cells on the plurality of bottom PCM cells, a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in plan view, a plurality of top dummy cells on the plurality of bottom dummy cells, a first gap fill layer between adjacent bottom PCM cells, a second gap fill layer at least partially surrounding the plurality of bottom PCM cells in plan view, a third gap fill layer between adjacent top PCM cells, and a fourth gap fill layer at least partially surrounding the plurality of top PCM cells in plan view.

In some embodiments, the first gap filling layer has a better gap filling capability than the second gap filling layer, and the third gap filling layer has a better gap filling capability than the fourth gap filling layer.

In some embodiments, the first gap fill layer has a thermal insulation capability that is better than the thermal insulation capability of the second gap fill layer, and the third gap fill layer has a thermal insulation capability that is better than the thermal insulation capability of the fourth gap fill layer.

In some embodiments, the first gap fill layer comprises the same material as the third gap fill layer and the second gap fill layer comprises the same material as the fourth gap fill layer.

In some embodiments, the first gap-filling layer comprises a ceramic, glass, air, polymer, other related insulating material, or combinations thereof.

In some embodiments, the first gap-fill layer has a thermal conductivity of no greater than 0.6W/(m · K).

In some embodiments, the second gap fill layer comprises silicon oxide, aluminum oxide, other related oxide materials, or combinations thereof.

In some embodiments, the memory device further includes a bottom bit line, a word line, a top bit line, a bottom bit line contact, a word line contact, and a top bit line contact. The bottom bitline is connected between a bottom bitline contact and the bottom PCM cell, the wordline is connected between a wordline contact and the bottom PCM cell and between the wordline contact and the top PCM cell, and the top bitline is connected between the top bitline contact and the top PCM cell.

In some embodiments, the storage device further comprises a peripheral stack below the plurality of bottom PCM cells. The periphery stack includes a bottom bit line selector connected to the bottom bit line contact, a top bit line selector connected to the top bit line contact, and a word line driver connected to the word line contact.

According to another aspect, a method of manufacturing a memory device includes: forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, filling a plurality of first trenches between adjacent bottom PCM cells and adjacent bottom dummy cells to form a first gap-fill layer, removing the first gap-fill layer outside the memory region, and patterning the bottom bit line layer in the dummy region to form a bottom bit line, forming a word line layer on the plurality of bottom PCM cells and bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, filling a plurality of second trenches between adjacent top PCM cells and adjacent top dummy cells to form a third gap-fill layer, removing the third gap-fill layer outside the memory region, and patterning the word line layer in the dummy region to form a word line, forming a top bit line layer on the plurality of top PCM cells and top dummy cells, and the top bit line on the top dummy cell is patterned to form a top bit line.

In some embodiments, the method further comprises: after removing the first gap fill layer outside the storage regions and patterning the bottom bit line layer in the dummy region, word line contacts are formed.

In some embodiments, a word line contact is connected between a word line layer and a bottom PCM cell.

In some embodiments, the method further comprises: after removing the first gap fill layer outside the memory region and patterning the bottom bit line layer in the dummy region, filling is performed to form a second gap fill layer covering the bottom PCM cells and the bottom dummy cells.

In some embodiments, the method further comprises: prior to forming a wordline layer over a plurality of bottom PCM cells and bottom dummy cells, a first planarization process is applied to a second gap fill layer to expose a first top surface of the bottom PCM cells.

In some embodiments, the method further comprises: after removing the third gap-fill layer outside the memory region and patterning the word line layer in the dummy region, a top bit line contact is formed.

In some embodiments, a top bitline contact is connected between a top bitline layer and a top PCM cell.

In some embodiments, the method further comprises: after removing the third gap-fill layer outside the memory region and patterning the word line layer in the dummy region, filling is performed to form a fourth gap-fill layer covering the top PCM cell and the top dummy cell.

In some embodiments, the method further comprises: prior to forming a top bit line layer on the plurality of top PCM cells and the top dummy cell, a second planarization process is applied to the fourth gap-fill layer to expose a second top surface of the top PCM cell.

In some embodiments, a length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than a length of the memory block. In plan view, the bottom dummy cell at least partially surrounds the bottom PCM cell in the memory block.

In some implementations, patterning the bottom bit line layer in the dummy region to form the bottom bit line also patterns the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit line in the storage region extends in a second lateral direction.

In some embodiments, patterning the word line layer in the dummy region to form the word line further patterns the word line layer in the storage region in a second lateral direction such that the word line in the storage region extends in the first lateral direction.

In some embodiments, patterning the top bit line layer in the dummy region to form the top bit line further patterns the top bit line layer in the storage region in a first lateral direction such that the top bit line in the storage region extends in a second lateral direction.

According to still another aspect, a method of manufacturing a memory device includes: forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, patterning the bottom bit line layer in the dummy cells to form a bottom bit line, forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, patterning the word line layer in the dummy cells to form word lines, forming a top bit line layer on the plurality of top PCM cells and the top dummy cells, and patterning the top bit line layer on the top dummy cells to form a top bit line. Each of the bottom bit line layer, the word line layer, and the top bit line layer has a length less than a length of the memory block, and the bottom dummy cell at least partially surrounds the bottom PCM cell in the memory block in a plan view. .

In some embodiments, the method further includes forming a word line contact after patterning the bottom bit line layer in the dummy region.

In some embodiments, the method further includes forming a top bit line contact after patterning the word line layer in the dummy region.

In some embodiments, patterning the bottom bit line layer in the dummy region to form the bottom bit line further patterns the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit line in the storage region extends in a second lateral direction.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a perspective view of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 2A and 2B illustrate side views of cross-sections of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 3 illustrates a perspective view of an example 3D memory device including an example 3D PCM device having an interconnect layer according to some aspects of the present disclosure.

Fig. 4A and 4B illustrate side views of cross sections of an example 3D memory device including an example 3D PCM device, an interconnect layer, and a peripheral device, according to some aspects of the present disclosure.

Fig. 5A and 5B illustrate side views of cross sections of an example 3D memory device including a 3D PCM device and an interconnect layer, according to some aspects of the present disclosure.

Fig. 6A-6L illustrate a fabrication process for forming an exemplary 3D memory device, according to some aspects of the present disclosure.

FIG. 7 illustrates a flow diagram of a method for forming an example 3D storage device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. One skilled in the relevant art will also recognize that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood, at least in part, from the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may likewise be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Additionally, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on," over, "and" over "in this disclosure should be interpreted in the broadest sense, such that" on "means not only directly on" but also includes the meaning of being "on" and having intervening features or layers therebetween, and "over" or "over" means not only "over" or "over" but also includes the meaning of being "over" or "over" and having no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "3D" memory device or PCM device refers to a semiconductor device having memory cells that may be arranged on a laterally oriented substrate such that the number of memory cells may be scaled up in a vertical direction relative to the substrate. As used herein, the term "vertical" refers to nominally perpendicular to a lateral surface of a substrate.

Based on electrothermal heating and quenching of a phase change material (e.g., a chalcogenide alloy), a PCM may utilize the difference between the resistivities of the amorphous and crystalline phases in the phase change material. Phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion of the material blocking the current path) between the two phases to store data. PCM cells may be vertically stacked in a 3D manner to form a 3D PCM device. 3D PCM devices store data based on a change in resistance of a bulk material property (e.g., in a high resistance state or a low resistance state) in conjunction with a bit-addressable, stackable cross-point data access array.

As memory devices have evolved, more stacks of memory cells have been arranged in memory devices. Specifically, a plurality of memory cells are stacked and arranged in a memory block. And a plurality of memory blocks are arranged in a single die. Conventionally, memory blocks are arranged in a die with memory cells predetermined in certain areas of the die to serve as memory areas, and dummy cells are arranged on dummy areas of the die between adjacent memory blocks. The dummy cell may have multiple uses depending on the circuit design. For example, the dummy cell is configured to operate as a storage capacitor, which is connected to a source line to provide a bias voltage, or to a source of a ground level.

One of the manufacturing methods of forming memory cells in a memory block and forming dummy cells is to first form a memory block and then form dummy cells around the memory block. However, the gap between the dummy cell and the memory block may generate some etching load effect due to the narrow block edge of the memory block. That is, the etch depth is not well controlled at the narrow block edge, resulting in uneven etch depth distribution and even some leakage paths between the dummy cell and the memory cell. In addition, Chemical Mechanical Polishing (CMP) or other planarization processes may not be easily performed at the edge of the tile. The low local pattern density at the edge of the block can result in uneven surfaces, such as metal dishing or dielectric erosion after the CMP process. These also create more defects on the memory cells at the edges of the block.

Another manufacturing method of forming memory blocks and dummy cells is to form both memory cells and dummy cells including bit lines and word lines connected between the memory cells and dummy cells in a single process, and then to cut all the bit lines and word lines connected between adjacent dummy cells and also to cut the bit lines and word lines connected between the dummy cells and memory cells. Thus, the area of the memory block is well defined after the cutting process. One of the problems, however, is that the bitlines and wordlines connected between the cells and extending along the entire die are too long. Longer bit lines and word lines can have a high risk of delamination or bowing problems during fabrication, creating some shorting or contact failure problems between adjacent memory cells, reducing overall performance and yield.

To address one or more of the above-mentioned problems, the present disclosure introduces a memory device and a method of manufacturing the same, in which lithographic printing on the memory device is block-by-block. That is, in order to solve the problem of performing full lithography printing on the entire die, which may generate a high peeling risk and a problem of bending of bit lines and word lines, by performing lithography printing on memory cells and dummy cells block by block, bit lines and word lines are not so long, and thus the peeling risk and the bending problem are minimized. In particular, according to some embodiments of the disclosure, the method comprises: forming a first semiconductor stack, patterning the first semiconductor stack to form a bottom memory cell in the memory region and a bottom dummy cell in the dummy region, wherein the bottom memory cell and the bottom dummy cell are connected to a sacrificial bottom bit line, gap filling the bottom memory cell and the bottom dummy cell to form a first gap fill layer, planarizing (e.g., CMP) the first gap fill layer to a top of the bottom memory cell and the bottom dummy cell, patterning to sever the sacrificial bottom bit line to form the bottom bit line, and also removing the first gap fill layer outside the memory region, forming a word line contact in the contact region, gap filling the dummy region, the memory region, and the contact region to form a second gap fill layer, planarizing the second gap fill layer to a top of the bottom memory cell and the bottom dummy cell, forming a sacrificial bottom word line on the bottom memory cell connected between the word line contact and the bottom memory cell, and patterned to sever the sacrificial bottom word lines to form bottom word lines and also to remove the second gap-fill layer in the dummy regions. A bottom memory cell having a bottom bit line and a bottom word line is then formed.

In addition, the method further comprises: forming a second semiconductor stack, patterning the second semiconductor stack to form a top memory cell in the memory region and a top dummy cell in the dummy region, wherein the top memory cell and the top dummy cell are both connected to the sacrificial top word line, gap filling the top memory cell and the top dummy cell to form a third gap fill layer, planarizing (e.g., CMP) the third gap fill layer to the top of the top memory cell and the top dummy cell, patterning to sever the sacrificial top word line to form the top word line, and also removing the third gap fill layer outside the memory region, forming a top bit line contact in the contact region, gap filling the dummy region, the memory region, and the contact region to form a fourth gap fill layer, planarizing the fourth gap fill layer to the top of the top memory cell and the top dummy cell, a sacrificial top bit line connected between the top bit line contact and the top memory cell is formed on the top memory cell and patterned to sever the sacrificial top bit line to form the top bit line and also to remove the fourth gap fill layer in the dummy region. A top memory cell having a top word line and a top bit line is then formed.

Note that in some embodiments, the first gap fill layer (and the third gap fill layer) and the second gap fill layer (and the fourth gap fill layer) may comprise different materials, such that the first gap fill layer formed between the trenches of the memory cells may provide better gap fill capability to fill the trenches under narrower spaces than the second gap fill layer. In addition, the first gap fill layer formed between the trenches of the memory cells may provide better thermal isolation capability, and thus may reduce thermal crosstalk that may undesirably switch adjacent unselected memory cells.

It should also be noted that in some embodiments, the sacrificial bit lines and the sacrificial word lines are deposited only for the block length, thereby minimizing the risk of stripping and bowing problems of the bit lines and word lines.

Fig. 1 illustrates a perspective view of an exemplary 3D PCM device 100 according to some embodiments of the present disclosure. According to some embodiments, the 3D PCM device 100 has a transistor-less cross-point architecture that positions memory cells at intersections of vertical conductors. The 3D PCM device 100 includes one or more bottom bitlines 133 in the same plane and one or more parallel top bitlines 131 in the same plane above the bottom bitlines 133. The 3D PCM device 100 also includes one or more parallel wordlines (e.g., top wordline 141, bottom wordline 143, or a combination thereof) in the same plane vertically between the bottom bitline 133 and the top bitline 131. As shown in fig. 1, each bottom bit line 133 and each top bit line 131 extends laterally in plan view (parallel to the plane of the wafer) along a bit line direction (e.g., the x-direction), and each word line 141/143 extends laterally in plan view along a word line direction (e.g., the y-direction). In plan view, each word line 141/143 intersects each bottom bit line 133 and each top bit line 131. In some embodiments, each word line 141/143 is perpendicular to each bottom bit line 133 and each top bit line 131.

Note that the x-axis and y-axis are included in fig. 1 to show two orthogonal directions in the plane of the wafer. The x-direction is the bit line direction and the y-direction is the word line direction. Note that the x-direction and y-direction are interchangeable; that is, the x-direction may be a word line direction and the y-direction may be a bit line direction. It should also be noted that the z-axis is included in fig. 1 to further illustrate the spatial relationship of components in the 3D PCM device 100. The substrate (not shown) of the 3D PCM device 100 comprises two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side of the wafer opposite the front side. The z-axis is perpendicular to the x-axis and the y-axis. As used herein, whether a component (e.g., a layer or device) of a semiconductor device is "on," "above," or "below" another component (e.g., a layer or device) in the z-direction is determined with respect to a substrate of the semiconductor device when the substrate is located in the lowest plane of the semiconductor device (e.g., 3D PCM device 100) in the z-direction (the vertical direction perpendicular to the x-y plane). The same concepts used to describe spatial relationships apply throughout this disclosure.

As shown in FIG. 1, the 3D PCM device 100 includes one or more top PCM cells 151, each top PCM cell 151 disposed at an intersection of a top bitline 131 and a corresponding wordline 141/143, and one or more bottom PCM cells 153, each bottom PCM cell 153 disposed at an intersection of a bottom bitline 133 and a corresponding wordline 141/143. In some embodiments, each of the top PCM cell 151 or the bottom PCM cell 153 has a vertical square pillar shape. In some embodiments, each of the top PCM cell 151 or the bottom PCM cell 153 includes at least a vertically stacked PCM element and a selector. In some embodiments, the selector is formed between the bottom bitline 133 and the PCM element. In some embodiments, each of the top PCM cell 151 or the bottom PCM cell 153 further includes a heater connected to the PCM element. Each of the top PCM cell 151 or the bottom PCM cell 153 stores a single bit of data and can be written or read by changing the voltage applied to the corresponding selector, which replaces the need for a transistor. Each of top PCM cell 151 or bottom PCM cell 153 is individually accessed by applying current through top and bottom conductors (e.g., a respective word line 141/143 and top or bottom bit line 131 or 133) in contact with each PCM cell. The top PCM cell 151 or the bottom PCM cell 153 in the 3D PCM device 100 is arranged in a memory array. In some embodiments, a PCM element may include a chalcogenide composition including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, each of the

bit lines

131, 133 and the word line 141/143 includes a metal, such as tungsten. In some embodiments, the PCM element may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) or TeGeSbS. In some embodiments, the selector may be an elliptical threshold switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material that exhibits OTS characteristics.

Furthermore, as shown in fig. 1, the 3D PCM device 100 may also include one or more top bitline contacts 121 connected to the top bitline 131, one or more bottom bitline contacts 123 connected to the bottom bitline 133, and one or more wordline contacts 125 connected to the wordline 141/143. The top bitline contact 121, the bottom bitline contact 123, and the wordline contact 125 may extend vertically in the z-direction. In some implementations, each of the top bit line contact 121, the bottom bit line contact 123, and the word line contact 125 includes a metal, such as tungsten.

Fig. 2A and 2B illustrate side views in schematic cross-section of an example 3D PCM device 100 according to some aspects of the present disclosure. In fig. 2A, in a y-z plane cross section, a 3D PCM device 100 includes one or more parallel top bitlines 131 formed above a top PCM cell 151 and one or more parallel bottom bitlines 133 formed below a bottom PCM cell 153. A wordline 141/143 extends laterally in the y-direction between the top PCM cell 151 and the bottom PCM cell 153. In fig. 2B, in an x-z plane cross section, the 3D PCM device 100 includes a top bitline 131, the top bitline 131 extending laterally in the x direction and connected to a top bitline contact 121, the top bitline contact 121 extending vertically in the z direction. The 3D PCM device 100 further comprises a bottom bitline 133, the bottom bitline 133 extending laterally in the x-direction and being connected to a bottom bitline contact 123, the bottom bitline contact 123 extending vertically in the z-direction. In some embodiments, the top bitline contact 121 and the wordline contact 125 run vertically in areas where no top or bottom PCM cell 151 or 153 is formed above or below.

Fig. 3 illustrates a perspective view of an exemplary 3D PCM device 300 according to some embodiments of the present disclosure. The 3D PCM device 300 includes one or more parallel bottom bit lines 333 (e.g., corresponding to the bottom bit line 133 in fig. 1), one or more parallel top bit lines 331 (e.g., corresponding to the top bit line 131 in fig. 1) in the same plane above the bottom bit lines 333, one or more parallel word lines 341/343 (e.g., corresponding to the word line 141/143 in fig. 1) in the same plane vertically between the bottom bit lines 333 and the top bit lines 331. As shown in fig. 3, each bottom bitline 333 and each top bitline 331 extend laterally in plan view (parallel to the wafer plane) along a bitline direction (e.g., the x-direction), and each wordline 341/343 extends laterally in plan view along a wordline direction (e.g., the y-direction). In plan view, each word line 341/343 intersects each bottom bit line 333 and each top bit line 331. In some embodiments, each word line 341/343 is perpendicular to each bottom bit line 333 and each top bit line 331.

As shown in FIG. 3, the 3D PCM device 300 includes one or more top PCM cells 351 (e.g., corresponding to the top PCM cell 151 of FIG. 1) and one or more bottom PCM cells 353 (e.g., corresponding to the bottom PCM cell 153 of FIG. 1), each top PCM cell 351 disposed at an intersection of a top bitline 331 and a respective wordline 341/343, each bottom PCM cell 353 disposed at an intersection of a bottom bitline 333 and a respective wordline 341/343. In some embodiments, each of the top PCM cell 351 or the bottom PCM cell 353 has a vertical square pillar shape. In some embodiments, each of the top PCM cell 351 or the bottom PCM cell 353 includes at least a vertically stacked PCM element (not shown) and a selector (not shown). Each of the top PCM cell 351 or the bottom PCM cell 353 stores a single bit of data and can be written or read by changing the voltage applied to the corresponding selector (not shown), which replaces the need for a transistor. Each of the top PCM cell 351 or the bottom PCM cell 353 is individually accessed by a current applied via top and bottom conductors (e.g., the respective word line 341/343 and top or bottom bit line 331 or 333) in contact with each PCM cell. The top PCM cell 351 or the bottom PCM cell 353 in the 3D PCM device 300 is arranged in a memory array. The 3D PCM device 300 may also include one or more top bitline contacts 321 (e.g., corresponding to the top bitline contacts 121 in fig. 1) connected to the top bitline 331, one or more bottom bitline contacts 323 (e.g., corresponding to the bottom bitline contacts 123 in fig. 1) connected to the bottom bitline 333, and one or more wordline contacts 325 (e.g., corresponding to the wordline contacts 125 in fig. 1) connected to the wordline 341/343. The top bit line contact 321, the bottom bit line contact 323, and the word line contact 325 may extend vertically in the z-direction. In some embodiments, each of the top bitline contact 321, the bottom bitline contact 323, and the wordline contact 325 comprises a metal, such as tungsten.

The 3D PCM device 300 may include one or more top interconnect layers 365 (also referred to as top metal layers or M5 layers) extending laterally over memory cells (e.g., top PCM cell 351 or bottom PCM cell 353) of a memory array. The 3D PCM device 300 may also include one or more first interconnect layers 364 (also referred to as M4 layers) that extend laterally under the PCM cells 351/353 of the storage array. The 3D PCM device 300 may further include one or more through via contacts 327 that extend vertically (e.g., in the z-direction) and connect between the top interconnect layer 365 and the first interconnect layer 364.

Fig. 4A and 4B illustrate side views in schematic cross-section of an example 3D PCM device 300 according to some aspects of the present disclosure. In fig. 4A, in a y-z plane cross section, a 3D PCM device 300 includes one or more parallel top bitlines 331 formed on top PCM cells 351 extending in the x-direction, and one or more parallel bottom bitlines 333 formed below bottom PCM cells 353 extending in the x-direction. Top bit line 331 is connected to top bit line contact 321 and bottom bit line 333 is connected to bottom bit line contact 323. A word line 341/343 extends laterally in the y-direction between the top PCM cell 351 and the bottom PCM cell 353. Word line 341/343 is also connected to word line contact 325. Top interconnect layer 365 (also referred to as a top metal layer or M5 layer) extends laterally (e.g., in the x-direction or y-direction) over PCM cells 351/353 of the memory array. In some embodiments, the top interconnect layer 365 extends in a y-direction, which is perpendicular to the bit lines and parallel to the word lines. The first interconnect layer 364 extends laterally in the x-direction or y-direction under the PCM cells 351/351 of the memory array. Through-hole contact 327 extends vertically in the z-direction and connects between top interconnect layer 365 and first interconnect layer 364. In some embodiments, through via contact 327 may extend further up to, into, or through the substrate. Since fig. 4A and 4B are for illustration only, a partial enlarged side view 500 of the exemplary 3D PCM device 300 will be discussed later to show a more detailed structure.

In fig. 4B, in an x-z plane cross section, the 3D PCM device 300 includes a top bitline 331, the top bitline 331 extending laterally in the x-direction and connected to a top bitline contact 321, the top bitline contact 321 extending vertically in the z-direction. The 3D PCM device 300 also includes a bottom bitline 333, the bottom bitline 333 extending laterally in the x-direction and connected to a bottom bitline contact 323, the bottom bitline contact 323 extending vertically in the z-direction. In some embodiments, the top bitline contact 321 and the wordline contact 325 extend vertically in areas where no top PCM cell 351 or bottom PCM cell 353 is formed above or below.

As shown in fig. 4A and 4B, the 3D PCM device 300 may further include one or more peripheral blocks located below the memory array. The peripheral block may include one or more peripheral cells including a bottom bitline selector 303, a wordline driver 305, or a top bitline selector 301. In some embodiments, the 3D PCM device 300 includes a substrate 307. The one or more peripheral cells include a bottom bitline selector 303, a wordline driver 305, or a top bitline selector 301 formed on a substrate 307. Word line driver 305 may be connected to word line 341/343 via word line contact 325. A plurality of interconnect layers, such as top interconnect layer 365, first interconnect layer 364, second interconnect layer 363 (also referred to as an M3 layer), third interconnect layer 362 (also referred to as an M2 layer), fourth interconnect layer 361 (also referred to as an M1 layer) may extend laterally (e.g., in the x-direction or y-direction) and connect between word lines or bit lines via contacts. Substrate 307 may comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, each of the word line drivers (e.g., word line driver 305), bit line drivers, or bit line selectors (e.g., bottom bit line selector 303 and top bit line selector 301) includes a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor, or a combination thereof. For convenience of description, the peripheral cell and the substrate may be referred to as a peripheral stack body 309, and the storage cell formed on the peripheral stack body 309 may be referred to as a storage stack body.

Fig. 5A and 5B are partial enlarged side views 500 of fig. 4A and 4B, illustrating a cross-section of an exemplary 3D PCM device 300. Although fig. 5A and 5B (as well as fig. 6A-6L) focus only on the storage stack, it should be noted that the peripheral stack 309 located below the storage stack remains the same or similar to the peripheral stack 309 in fig. 4A and 4B. As shown in fig. 5A, the 3D PCM device 300 includes a bottom PCM cell 353 and a top PCM cell 351 above the bottom PCM cell 353. Bottom PCM cell 353 is connected to one or more bottom bitline contacts 323 via one or more bottom bitlines 333. The top PCM cell 351 is connected to one or more top bitline contacts 321 via one or more top bitlines 331. Word line 341/343 extends between the top and bottom PCM cells and in the y-direction.

The first gap filling layer 371 is formed and filled between the adjacent bottom PCM cells 353. In some embodiments, the first gap filling layer 371 is filled in the memory region 381 (the region where the memory cell is located). A second gap fill layer 373 is formed and fills outside of memory region 381 and may be formed within contact region 385 (the area where contacts (e.g., word line contact 325 and/or top bit line contact 321) are located). The second gap fill layer 373 at least partially surrounds the first gap fill layer 371 or the bottom PCM cell 353 in plan view. Accordingly, the second gap fill layer 373 at least partially surrounds the memory region 381 in plan view. In some embodiments, the first gap fill layer 371 may comprise ceramic, glass, air, polymer, other related thermally insulating materials, or combinations thereof (e.g., polymer surrounding air). In some embodiments, the first gap-fill layer 371 has a thermal conductivity of no more than 0.6W/(m · K). In some embodiments, the second gap fill layer 373 may include silicon oxide, aluminum oxide, other related oxide materials, or combinations thereof. In some embodiments, the first gap fill layer 371 has better gap filling capability than the second gap fill layer 373 because the first gap fill layer 371 is configured to fill into the trenches between adjacent bottom PCM cells 353. In some embodiments, the first gap fill layer 371 has better thermal isolation capability, so that thermal cross talk, which may undesirably switch adjacent unselected memory cells, may be reduced.

A third gap-fill layer 375 is formed and filled between adjacent top PCM cells 351. In some embodiments, a third gap fill layer 375 fills in the memory region 381. A fourth gap filling layer 377 is formed and filled outside the storage region 381 and may be formed within the contact region 385. The fourth gap-fill layer 377 at least partially surrounds the third gap-fill layer 375 or the top PCM cell 351 in plan view. Accordingly, the fourth gap filling layer 377 at least partially surrounds the memory region 381 in plan view. In some embodiments, the third gap-fill layer 375 may include ceramic, glass, air, polymer, other related insulating materials, or combinations thereof (e.g., polymer surrounding air). In some embodiments, the thermal conductivity of the third gap-fill layer 375 does not exceed 0.6W/(m · K). In some embodiments, the fourth gap filling layer 377 may include silicon oxide, aluminum oxide, other related oxide materials, or combinations thereof. In some embodiments, the third gap-filling layer 375 has better gap-filling capability than the fourth gap-filling layer 377 because the third gap-filling layer 375 is configured to fill into the trenches between the adjacent top PCM cells 351. In some embodiments, the third gap-fill layer 375 has better thermal isolation capability, which may reduce thermal cross-talk that may undesirably switch adjacent unselected memory cells. Note that the third gap fill layer 375 may include the same or similar material as the first gap fill layer 371. In addition, the fourth gap filling layer 377 may include the same or similar material as the second gap filling layer 373.

Fig. 5B illustrates another side view of a cross section of an exemplary 3D PCM device 300. As shown in fig. 5B, the 3D PCM device 300 may further include dummy cells (e.g., a top dummy cell 355 and a bottom dummy cell 357) arranged to surround memory cells (e.g., a top PCM cell 351 and a bottom PCM cell 353) in the memory block. These dummy cells 355/357 are located in one or more dummy regions 383. These dummy areas 383 may at least partially surround the memory areas 381 in the memory block in a plan view. As described above, these dummy cells are configured to operate as storage capacitors, which are connected to a source line to provide a bias voltage, or to a source at ground level. Note that although the shape and stack of layers in the dummy cell are the same or similar to the memory cell, the dummy cell may not be connected to a bit line or word line as the memory cell. In some embodiments, the second gap fill layer may not be formed and filled between adjacent dummy cells 355/357 in dummy region 383, or may be only partially formed and filled between adjacent dummy cells 355/357.

Fig. 6A-6L illustrate a fabrication process for forming an exemplary 3D memory device, according to some aspects of the present disclosure. FIG. 7 illustrates a flow diagram of a method for forming an example 3D storage device, according to some aspects of the present disclosure. The 3D storage device may be any suitable 3D storage device disclosed herein. It will be understood that the operations shown in method 700 may not be exhaustive, and that other operations may be performed before, after, or in between any of the shown operations. Further, some operations may be performed concurrently or in a different order than shown in FIG. 7. Fig. 6A-6L may be discussed together with fig. 7.

Referring to fig. 7, the method 700 begins with operation 702 in which a plurality of bottom memory cells and a plurality of bottom dummy cells are formed on a periphery stack. In addition, a plurality of first trenches between adjacent bottom memory cells are filled with a first gap fill material to form a first gap fill layer. For example, as shown in fig. 6A, a plurality of bottom PCM cells 353 and a plurality of bottom dummy cells 357 are formed on the peripheral stack (e.g., 309 in fig. 4A and 4B). In some embodiments, the bottom PCM cell 353 and the bottom dummy cell 357 may be formed by depositing a bottom site line layer and depositing a first semiconductor stack on the bottom site line layer. In some embodiments, the bottom bit line layer is deposited only for the memory block length. That is, the bottom bit line layer may not extend from one memory block to another memory block. The length of the bottom bit line layer is smaller than the length of the memory block. Thus, the risk of delamination or bending problems is minimized. The first semiconductor stack may include a first bottom electrode layer, a first selector layer on the first bottom electrode layer, a first PCM element layer on the first selector layer, and a first top electrode layer on the first PCM element layer. By further etching or patterning the first semiconductor stack, a bottom PCM cell 353 and a bottom dummy cell 357 are formed. In some embodiments, etching or patterning to form the bottom PCM cell 353 and the bottom dummy cell 357 comprises a two-step etching process (also referred to as a double patterning process). That is, a first step etch is applied over the first semiconductor stack to form first trenches 391 between adjacent bottom PCM cells 353 and a second step etch is applied to cut the bottom bit line layer in the y-direction to form bottom bit lines 333 extending in the x-direction. When patterning the bottom bit line layer, the bottom bit line layer in dummy region 383 is also patterned so that the dummy cells are isolated from each other.

Next, as shown in fig. 6B, the first trench 391 between adjacent bottom PCM cells 353 is filled with a first gap filling material 3711. In some embodiments, Chemical Mechanical Polishing (CMP) or planarization may be applied to the first gap fill material 3711 up to the top surface of the bottom PCM cell 353 such that the top surface of the bottom PCM cell 353 is exposed.

The method 700 proceeds to operation 704 where the first gap fill layer outside the memory region is removed, as shown in fig. 7. In addition, word line contacts are formed thereafter. For example, as shown in fig. 6C, the first gap fill layer 371 is formed only on the memory region 381 by removing the first gap fill material 3711 outside the memory region 381. In some embodiments, the first gap fill material 3711 in contact regions 385 and dummy regions 383 is removed. The removal may be accomplished by wet etching, dry etching, or a combination thereof.

Next, as shown in fig. 6D, a word line contact 325 is formed in contact with, for example, a first interconnect layer (also referred to as M4 layer 364 in fig. 4B). The word line contact 325 is configured to extend vertically (e.g., in the z-direction) and connect between the word line and the peripheral cells below the memory stack.

Next, as also shown in fig. 6D, the second gap filling layer 373 is then filled and the second gap filling layer 373 covers the first gap filling layer 371, the bottom PCM cell 353, the bottom dummy cell 357, and the word line contact 325.

Next, as also shown in fig. 6D, another Chemical Mechanical Polishing (CMP) or planarization may be applied to the second gap fill material 373 up to the top surface of the bottom PCM cell 353 such that the top surface of the bottom PCM cell 353 is exposed.

The method 700 proceeds to operation 706 as shown in fig. 7 where a word line is formed that is connected between the word line contact and the plurality of bottom memory cells. For example, as also shown in fig. 6E, a bottom word line layer 3431 is formed and connected between the word line contact 325, the bottom PCM cell 353, and the bottom dummy cell 357. In some implementations, the bottom wordline layer 3431 deposits only the memory block length. That is, the bottom wordline layer 3431 may not extend from one memory block to another. The length of the bottom wordline layer 3431 is less than the length of the memory block. Thus, the risk of delamination or bending problems is minimized.

Next, as shown in fig. 6F, etching or patterning (e.g., double patterning) is applied to remove a portion of the second gap fill layer 373 in the dummy region 383 and to cut off the bottom word line layer 3431 to form the bottom word line 343. That is, a first step etch is applied to cut through the bottom word line layer 3431 in the x-direction to form the bottom word line 343 extending in the y-direction. Then, a second step etch is applied to remove portions of the second gap fill layer 373 in the dummy region 383. The bottom wordline 343 may be connected between the wordline contact 325 and the bottom PCM cell 353 as shown in another cross-sectional view. When the bottom word line layer 3431 is patterned, the bottom word line layer 3431 in the dummy area 383 is also patterned so that the dummy cells are isolated from each other.

The method 700 proceeds to operation 708 where a plurality of top memory cells are formed over a plurality of bottom memory cells, as shown in fig. 7. In addition, a plurality of second trenches between adjacent top memory cells are filled to form a third gap-fill layer. For example, as shown in fig. 6G, a top PCM cell 351 is formed on a bottom PCM cell 353, and a top dummy cell 355 is formed on a bottom dummy cell 357. The top PCM cell 351 and the top dummy cell 355 may be formed by depositing a top wordline layer and depositing a second semiconductor stack on the top wordline layer, the same or similar to forming the bottom PCM cell 353 and the bottom dummy cell 357. The second semiconductor stack may include a second bottom electrode layer, a second selector layer on the second bottom electrode layer, a second PCM element layer on the second selector layer, and a second top electrode layer on the second PCM element layer. By further etching or patterning the second semiconductor stack, a top PCM cell 351 and a top dummy cell 355 are formed.

Next, as shown in fig. 6H, the second trenches 393 between adjacent top PCM cells 351 are filled with a third gap fill material 3751. In some embodiments, Chemical Mechanical Polishing (CMP) or planarization may be applied to the third gap fill material 3751 until the top surface of the top PCM cell 351, such that the top surface of the top PCM cell 351 is exposed.

The method 700 proceeds to operation 710 where the third gap fill layer outside the memory region is removed and a top bitline contact is formed, as shown in fig. 7. For example, as shown in fig. 6I, an etching or patterning process is applied to remove the third gap fill material 3751 in the dummy regions 383 and contact regions 385 to form a third gap fill layer 375.

Next, as shown in fig. 6J, a top bit line contact 321 is formed in contact with, for example, another first interconnect layer (also referred to as M4 layer 364 in fig. 4B).

The method 700 proceeds to operation 712 where a top bit line is formed that connects between the top bit line contact and the plurality of top memory cells, as shown in fig. 7. For example, as shown in fig. 6K, prior to forming the top bit line, a fourth gap fill material (not shown) is filled and covers the third gap fill layer 375, the top PCM cell 351, the top dummy cell 355 and the top bit line contact 321.

Next, another CMP or planarization may be applied to the fourth gap filling material until the top surface of the top PCM cell 351 so that the top surface of the top PCM cell 351 is exposed. A fourth gap filling layer 377 is then formed.

Next, as also shown in FIG. 6K, a top bitline layer 3311 is deposited that connects between the top bitline contact 321 and the top PCM cell 351. In some embodiments, the top bit line layer 3311 is deposited only the memory block length. That is, the top bit line layer 3311 may not extend from one memory block to another. The length of top bit line layer 3311 is less than the length of the memory block. Thus, the risk of delamination or bending problems is minimized.

Next, as shown in fig. 6L, etching or patterning (e.g., double patterning) is applied to remove a portion of the fourth gap fill layer 377 in the dummy region 383 and to sever the top bit line layer 3311 (e.g., in fig. 6K) to form the top bit line 311. That is, a first step etch is applied to cut the top bit line layer 3311 in the x-direction to form top bit lines 331 extending in the y-direction. Then, a second step etch is applied to remove a portion of the fourth gap-fill layer 377 in the dummy region 383. When patterning top bit line layer 3311 in storage region 381, top bit line layer 3311 in dummy region 383 is also patterned so that dummy cells are isolated from each other. It is also noted that in another cross-sectional view, the top bitline 331 may be connected between the top bitline contact 321 and the top PCM cell 351.

The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not necessarily all exemplary embodiments of the present disclosure as contemplated by the inventors, and are, therefore, not intended to limit the disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising:

a plurality of bottom Phase Change Memory (PCM) cells;

a plurality of top PCM cells on the plurality of bottom PCM cells;

a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in a plan view;

a plurality of top dummy cells on the plurality of bottom dummy cells;

a first gap-fill layer between adjacent bottom PCM cells;

a second gap fill layer at least partially surrounding the plurality of bottom PCM cells in the plan view;

a third gap-fill layer between adjacent top PCM cells; and

a fourth gap-fill layer at least partially surrounding the plurality of top PCM cells in the plan view.

2. The memory device of claim 1, wherein the first gap fill layer has a gap filling capability that is better than a gap filling capability of the second gap fill layer, and the third gap fill layer has a gap filling capability that is better than a gap filling capability of the fourth gap fill layer.

3. The storage device of claim 1 or 2, wherein the first gap fill layer has a thermal insulation capability that is better than a thermal insulation capability of the second gap fill layer, and the third gap fill layer has a thermal insulation capability that is better than a thermal insulation capability of the fourth gap fill layer.

4. The memory device of any one of claims 1-3, wherein the first gap fill layer comprises a material that is the same as a material of the third gap fill layer, and the second gap fill layer comprises a material that is the same as a material of the fourth gap fill layer.

5. The memory device of any one of claims 1-4, wherein the first gap fill layer has a thermal conductivity of no greater than 0.6W/(m-K).

6. The memory device of any one of claims 1-5, wherein the second gap fill layer comprises silicon oxide, aluminum oxide, other related oxide materials, or combinations thereof.

7. The storage device of any of claims 1-6, further comprising:

a bottom bit line;

a word line;

a top bit line;

a bottom bitline contact;

a word line contact; and

a top bitline contact, wherein the bottom bitline is connected between the bottom bitline contact and the bottom PCM cell, the wordline is connected between the wordline contact and the bottom PCM cell and between the wordline contact and the top PCM cell, and the top bitline is connected between the top bitline contact and the top PCM cell.

8. The storage device of claim 7, further comprising:

a peripheral stack below the plurality of bottom PCM cells, wherein the peripheral stack comprises:

a bottom bit line selector connected to the bottom bit line contact;

a top bit line selector connected to the top bit line contact; and

a word line driver connected to the word line contact.

9. A method of manufacturing a memory device, comprising:

forming a bottom part line layer;

forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom site line layer;

filling a plurality of first trenches between adjacent bottom PCM cells and adjacent bottom dummy cells to form a first gap-fill layer;

removing the first gap filling layer outside the storage area, and patterning the bottom position line layer in the dummy area to form a bottom position line;

forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cell;

forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer;

filling a plurality of second trenches between adjacent top PCM cells and adjacent top dummy cells to form a third gap-fill layer;

removing the third gap filling layer outside the storage area, and patterning the word line layer in the dummy area to form a word line;

forming a top bit line layer on the plurality of top PCM cells and the top dummy cell; and

patterning the top bit line layer on the top dummy cell to form a top bit line.

10. The method of claim 9, further comprising:

forming word line contacts after removing the first gap-fill layer outside the memory region and patterning the bottom bit line layer in the dummy region.

11. The method of claim 10, wherein the wordline contact is connected between the wordline layer and the bottom PCM cell.

12. The method according to any one of claims 9-11, further comprising:

filling to form a second gap fill layer covering the bottom PCM cells and the bottom dummy cells after removing the first gap fill layer outside the memory region and patterning the bottom bit line layer in the dummy region.

13. The method of claim 12, further comprising:

applying a first planarization process to the second gap fill layer to expose a first top surface of the bottom PCM cells prior to forming the word line layer on the plurality of bottom PCM cells and the bottom dummy cell.

14. The method according to any one of claims 9-13, further including:

after removing the third gap-fill layer outside the storage region and patterning the word line layer in the dummy region, a top bit line contact is formed.

15. The method of claim 14, wherein the top bitline contact connects between the top bitline layer and the top PCM cell.

16. The method according to any one of claims 9-15, further including:

after removing the third gap-fill layer outside the storage region and patterning the word line layer in the dummy region, filling to form a fourth gap-fill layer covering the top PCM cells and the top dummy cells.

17. The method of claim 16, further comprising:

applying a second planarization process to the fourth gap-fill layer to expose a second top surface of the top PCM cells prior to forming the top bit line layer on the plurality of top PCM cells and the top dummy cell.

18. The method of any of claims 9-17, wherein a length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than a length of a memory block, and wherein the bottom dummy cell at least partially surrounds the bottom PCM cell in the memory block in a plan view.

19. The method of any of claims 9-18, wherein patterning the bottom bit line layer in the dummy region to form the bottom bit line further patterns the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit line in the storage region extends in a second lateral direction.

20. The method of any of claims 9-19, wherein patterning the word line layer in the dummy region to form the word line further patterns the word line layer in the storage region in the second lateral direction such that the word line in the storage region extends in the first lateral direction.

21. The method of any of claims 9-20, wherein patterning the top bit line layer in the dummy region to form the top bit line further patterns the top bit line layer in the storage region in the first lateral direction such that the top bit line in the storage region extends in the second lateral direction.

22. A method of manufacturing a memory device, comprising:

forming a bottom part line layer;

forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer;

patterning the bottom bit line layer in a dummy region to form a bottom bit line;

patterning the word line layer in the dummy region to form a word line;

patterning the top bit line layer on the top dummy cells to form top bit lines, wherein a length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than a length of a memory block, and wherein the bottom dummy cells at least partially surround the bottom PCM cells in the memory block in plan view.

23. The method of claim 22, further comprising:

after patterning the bottom site line layer in the dummy region, word line contacts are formed.

24. The method of claim 23, wherein the wordline contact is connected between the wordline layer and the bottom PCM cell.

25. The method according to any one of claims 22-24, further comprising:

after patterning the word line layer in the dummy region, a top bit line contact is formed.

26. The method of claim 25, wherein the top bitline contact is connected between the top bitline layer and the top PCM cell.

27. The method of any of claims 22-26, wherein patterning the bottom bit line layer in the dummy region to form the bottom bit line further patterns the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit line in the storage region extends in a second lateral direction.

28. The method of any of claims 22-27, wherein patterning the word line layer in the dummy region to form the word line further patterns the word line layer in the storage region in the second lateral direction such that the word line in the storage region extends in the first lateral direction.

29. The method of any of claims 22-28, wherein patterning the top bit line layer in the dummy region to form the top bit line further patterns the top bit line layer in the storage region in the first lateral direction such that the top bit line in the storage region extends in the second lateral direction.