CN112602152A

CN112602152A - Memory device having memory cells with multiple threshold voltages and methods of forming and operating the same

Info

Publication number: CN112602152A
Application number: CN202080003338.6A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-11-09
Filing date: 2020-11-09
Publication date: 2021-04-02
Also published as: WO2022095007A1

Abstract

Embodiments of a memory device and methods of forming and operating the same are disclosed. In an example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

Description

Memory device having memory cells with multiple threshold voltages and methods of forming and operating the same

Background

Embodiments of the present disclosure relate to memory devices and methods of fabricating and operating the same.

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripherals for controlling signals to and from the memory array. For example, Phase Change Memories (PCMs) may utilize the difference between the resistivities of amorphous and crystalline states in a phase change material, which is based on heating and quenching the phase change material electrically and thermally. PCM array cells may be vertically stacked in 3D to form a 3D PCM.

Disclosure of Invention

Embodiments of a memory device and methods for forming and operating a memory device are disclosed herein.

In an example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

In another example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes a stacked metal ion reservoir, a solid electrolyte, and a separator vertically positioned between the metal ion reservoir and the solid electrolyte.

In yet another example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes doped arsenic selenide.

In yet another example, a method for forming a memory device is disclosed. A unit cell layer is formed. A plurality of gaps are formed through the cell layer to divide the cell layer into a plurality of cell elements, each cell element configured to have a plurality of threshold voltages. A plurality of insulating structures are formed in the plurality of gaps between the plurality of unit cells.

In yet another example, a method for operating a memory device is disclosed. The 3D memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell being disposed at an intersection of a corresponding bit line of the plurality of bit lines and a corresponding word line of the plurality of word lines. One of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines. The memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. The memory cell is sensed at a sensing voltage between the first and second threshold voltages.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

FIG. 1 illustrates a perspective view of an exemplary 3D crosspoint (XPoint) memory device, in accordance with some embodiments of the present disclosure.

Fig. 2 illustrates a side view of a cross-section of a 3D cross-point memory device having an Ovonic Threshold Switch (OTS) selector.

Fig. 3A-3C illustrate side views of cross sections of an exemplary memory device including memory cells having multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 4 illustrates a side view of a cross-section of another exemplary memory cell having multiple threshold voltages, according to some embodiments of the present disclosure.

Fig. 5A and 5B illustrate schematic diagrams of the operation of an exemplary memory cell array having multiple threshold voltages, according to some embodiments of the present disclosure.

Fig. 6A-6H illustrate an exemplary fabrication process for forming a memory device including memory cells having multiple threshold voltages, according to some embodiments of the present disclosure.

Fig. 7 illustrates a flow diagram of an exemplary method for forming a memory device including memory cells having multiple threshold voltages, in accordance with some embodiments of the present disclosure.

Fig. 8 illustrates a flow chart of an exemplary method for operating a memory device including memory cells having multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 9 illustrates exemplary first and second threshold voltages of a memory cell according to some embodiments of the present disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or a plural use depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors not necessarily expressly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on", "above" and "over" in this disclosure should be interpreted in the broadest manner, such that "on" means not only directly on something, but also on something with intervening features or layers therebetween, and "on" or "over" means not only on "above" or "over" something, but may also include the meaning that it is "on" or "over" something without intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below," "lower," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire structure of the lower or upper layer or may have a smaller extent than the structure of the lower or upper layer. Further, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductive and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "nominal" refers to a desired or target value, and a range of values above and/or below the desired value, of a characteristic or parameter of a component or process operation that is set at a design stage of a product or process. The range of values may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity, which may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may indicate a given number of values that vary, for example, within 10-30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.

As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may be scaled up in a vertical direction relative to the substrate. As used herein, the term "vertical" refers to nominally perpendicular to a lateral surface of a substrate.

PCMs may utilize the difference between the electrical resistivity of amorphous and crystalline states in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quench cooling of the phase change material. Phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch material (or at least a portion of material to block the current path) between the two phases to store data. PCM cells may be vertically stacked in 3D to form a 3D PCM. In the reset state, a short high current/high voltage is applied to heat the PCM cell material to melt and quench the molten material into an amorphous high resistance state, which shows an electronic threshold transition above the threshold voltage Vt prior to the crystallization step. In the set state, a long and medium current/voltage is applied to heat the PCM cell material to crystallize the amorphous material into a crystalline low resistance state, much like a resistor.

The 3D PCM includes a 3D cross-point memory that stores data based on resistance changes in bulk material properties (e.g., in a high resistance state or a low resistance state), and incorporates a stackable cross-point data access array to be bit addressable. For example, fig. 1 illustrates a perspective view of an exemplary 3D cross-point memory device 100, according to some embodiments of the present disclosure. According to some embodiments, the 3D cross-point memory device 100 has a transistor-less cross-point architecture that positions memory cells at the intersections of vertical conductors. The 3D cross-point memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above the lower bit lines 102. The 3D cross-point memory device 100 also includes a plurality of parallel word lines 106 vertically located in the same plane between the lower bit lines 102 and the upper bit lines 104. As shown in fig. 1, each lower bitline 102 and each upper bitline 104 extend laterally in plan view (parallel to the wafer plane) along a bitline direction, and each wordline 106 extends laterally in plan view along a wordline direction. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

Note that the x-axis and y-axis are included in fig. 1A to show two orthogonal directions in the wafer plane. The x-direction is the word line direction and the y-direction is the bit line direction. Note that the z-axis is also included in fig. 1 to further illustrate the spatial relationship of the components in the 3D cross-point memory device 100. The substrate (not shown) of the 3D cross-point memory device 100 comprises two side surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether a component (e.g., a layer or device) of a semiconductor device (e.g., 3D cross-point memory device 100) is "above", "over" or "under" another component (e.g., a layer or device) is determined relative to a substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is located in the lowest plane of the semiconductor device in the z-direction. The same concepts that describe spatial relationships apply throughout this disclosure.

As shown in fig. 1, the 3D cross-point memory device 100 includes a plurality of memory cells 108, each memory cell 108 being arranged at an intersection of a lower or

upper bit line

102 or 104 and a corresponding word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each memory cell 108 stores a single bit of data and can be written to or read by varying the voltage applied to the corresponding selector 112, which replaces the need for a transistor. Each memory cell 108 is individually accessed by currents applied through top and bottom conductors (e.g., the respective word line 106 and the lower or upper bit line 102 or 104) in contact with each memory cell 108. The memory cells 108 in the 3D cross-point memory device 100 are arranged in a memory array.

In existing 3D cross-point memories, the material of the selector 112 is an Ovonic Threshold Switch (OTS) material, such as zinc telluride (ZnTe), when applied above a threshold voltage (V)_th) External bias voltage (V)_a) It exhibits field-dependent volatile resistance-switching behavior (referred to as the "OTS phenomenon"). For example, fig. 2 shows a side view of a cross-section of a 3D cross-point memory device 200 with an OTS selector. The 3D cross-point memory device 200 includes a plurality of parallel bit lines 204 over a substrate 202 and a plurality of parallel word lines 216 over the bit lines 204. The 3D cross-point memory device 200 further includes a plurality of memory cells 201, each memory cell 201 being arranged at an intersection of a respective pair of bit lines 204 and word lines 216. Adjacent memory cells 201 are separated by insulating structures 203. Each memory cell 201 includes an OTS selector 208 and a PCM element 212 located above the OTS selector 208 (e.g., a single cellExamples of meta-elements). Each memory cell 201 also includes three

electrodes

206, 210 and 214, respectively, vertically positioned between a corresponding bitline 204, OTS selector 208, PCM element 212 and a corresponding wordline 216.

The OTS selector 208 includes an OTS material, such as zinc telluride. At lower voltages (| V)_a|<V_th) Next, the high resistance of the OTS selector 208 in the OFF state causes the OFF state current (I)_off) And remains low. At higher voltages (| V)_a|>V_th) Lower, the OTS selector 208 experiences the OTS phenomenon and transitions to a low resistance on state; thus, the current (I) through the OTS selector 208 in the on state_on) And (4) increasing. The volatile on state is maintained as long as a high voltage is supplied. In the reset operation, the threshold voltage Vt of the memory cell 201 is the sum of the threshold voltage Vt (OTS) of the OTS selector 208 and the threshold voltage Vt (PCM) of the PCM element 212. In the set state, the threshold voltage Vt of the memory cell 201 is only the threshold voltage Vt (OTS) of the OTS selector 208. In other words, the OTS selector 208 and the PCM element 212 are required to together set different threshold voltages of the memory cell 201 at different cell states (e.g., a reset state or a set state). In other examples, the selector 112 may be replaced with a switching device other than the OTS selector 208, such as a transistor or diode.

However, since the cell elements (e.g., PCM element 212) and the selector (e.g., OTS selector 208) are vertically stacked and each cell element and selector includes a stack of thin films patterned with high aspect ratio lines, the process is challenging, thereby affecting product yield. The multiple thin film stack structure also results in thinner word line and bit line films and higher sheet resistance, which limits the device size and electrical performance of the 3D cross-point memory device 200.

Various embodiments according to the present disclosure provide memory devices, such as 3D cross-point memory devices, including selector-less memory cells having multiple threshold voltages, and methods of fabricating and operating the same. The selector-less memory cell may remain in a threshold switching state, but wherein the threshold voltage Vt is adjustable to store data. That is, without any selector, the cell element of the memory cell itself may have two or more threshold voltages (e.g., threshold switching voltages) that may be programmed, for example, by applying positive or negative programming pulses having different amplitudes and/or widths. Thus, compared to conventional PCM devices with selectors (e.g., OTS selectors), the selector-less memory cells disclosed herein can be greatly simplified, and the height of the memory cells can also be reduced to reduce the aspect ratio of the memory cell structure, thereby enabling larger array sizes and reducing sheet resistance by increasing the thickness of the word line and bit line films. In some embodiments, the selector-less memory cells having multiple threshold voltages disclosed herein are formed in a self-aligned manner at the intersection of a pair of word lines and bit lines. In addition, cross-contamination between the selector and the cell during processing can be avoided. As a result, the process can be simplified, and the product yield can be increased.

Figures 3A-3C illustrate side views of cross sections of an exemplary memory device 300 including memory cells having multiple threshold voltages, according to some embodiments of the present disclosure. The memory device 300 (e.g., a 3D cross-point memory device) may include a plurality of bit lines 304 over a substrate 302, and the substrate 302 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The bit lines 304 may be parallel to each other and in the same plane. In some embodiments, the plurality of parallel bit lines 304 each extend laterally in the y-direction (e.g., bit line direction) in fig. 3A. The memory device 300 may also include a plurality of word lines 318 located over the bit lines 304. The word lines 318 may be parallel to each other and in the same plane. In some embodiments, a plurality of parallel word lines 318 each extend laterally in the x-direction (e.g., word line direction) in fig. 3A. The word lines 318 and bit lines 304 of the memory device 300 (e.g., a 3D cross-point memory device) may be vertically arranged conductors in a cross-point architecture. The bit lines 304 and word lines 318 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the bit lines 304 and word lines 318 and sub-lines comprises a metal, such as tungsten.

In some embodiments, memory device 300 includes a plurality of memory cells 301, each memory cell 301 disposed at an intersection of a respective bit line 304 and a respective word line 318. Each memory cell 301 may be individually accessed by a current applied through a corresponding word line 318 and a corresponding bit line 304 in contact with the memory cell 301. As shown in fig. 3A, the memory device 300 may further include insulating structures 303 laterally between adjacent memory cells 301. In some embodiments, each memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in fig. 1), and insulating structures 303 may extend laterally in both the x-direction and the y-direction to separate the pillar-shaped memory cells 301. In some embodiments, insulating structure 303 includes one or more dielectric layers, such as an encapsulation layer 322 formed along the sidewalls of memory cells 301 and bit lines 304, and a capping layer 323 filling the remaining space between memory cells 301. The dielectric layer of the insulating structure 303 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, encapsulation layer 322 and capping layer 323 comprise silicon nitride and silicon oxide, respectively.

Each memory cell 301 may include a cell element without a selector. That is, the memory cell 301 may be a selector-less memory cell. Unlike known memory cells each including a cell element and a selector connected in series, the cell element of the memory cell 301 can perform dual functions of storing data and converting because it can be configured to have a plurality of threshold voltages without a separate selector. A single data bit may be stored in each memory cell 301 and may be written or read by varying the voltage applied to the corresponding cell element, which eliminates the need for a selector (e.g., an OTS selector, transistor, or diode).

As shown in fig. 3A, the cell elements of each storage cell 301 may include a stacked metal ion reservoir 306, solid electrolyte 308, and separator 310. In some embodiments, the metal ion reservoirs 306 are located below and in contact with the respective wordlines 318, the solid electrolyte 308 is located above and in contact with the respective bitlines 304, and the separator 310 is vertically located between, i.e., sandwiched between, the metal ion reservoirs 306 and the solid electrolyte 308. For example, the separator 310 may be in contact with the metal ion reservoir 306 and the solid electrolyte 308 on opposite sides thereof. In some embodiments, the metal ion reservoir 306 has a thickness between about 5 nanometers and about 50 nanometers, such as between 5 nanometers and 50 nanometers (e.g., 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, any range bounded by any one of these values, or any range bounded by any two of these values). In some embodiments, the thickness of the solid electrolyte is between about 10 nanometers and about 100 nanometers, such as between 10 nanometers and 100 nanometers (e.g., 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, 80 nanometers, 85 nanometers, 90 nanometers, 95 nanometers, 100 nanometers, any range bounded below by any one of these values, or any range bounded by any two of these values). In some embodiments, the thickness of separator 310 is between about 1 nanometer and about 10 nanometers, such as between 1 nanometer and 10 nanometers (e.g., 1 nanometer, 1.5 nanometers, 2 nanometers, 2.5 nanometers, 3 nanometers, 3.5 nanometers, 4 nanometers, 4.5 nanometers, 5 nanometers, 5.5 nanometers, 6 nanometers, 6.5 nanometers, 7 nanometers, 7.5 nanometers, 8 nanometers, 8.5 nanometers, 9 nanometers, 9.5 nanometers, 10 nanometers, any range bounded by any one of these values, or any range bounded by any two of these values).

The metal ion reservoir 306 may contain metal ions, such as silver ions or copper ions. In some embodiments, the metal ion reservoir 306 comprises silver, copper, silver sulfide (AgS), copper sulfide (CuS), silver selenide (AgSe), copper selenide (CuSe), or any combination thereof. In some embodiments, the solid electrolyte 308 comprises germanium selenide (GeSe), germanium sulfide (GeS), silver selenide (AgSe), silver sulfide (AgS), copper telluride (CuTe), or any combination thereof. It is to be understood that silver selenide and silver sulfide may be used as the material of metal ion reservoir 306 and/or solid electrolyte 308, depending on, for example, the concentration of silver selenide or silver sulfide in metal ion reservoir 306 and/or solid electrolyte 308. For example, the concentration of silver selenide or silver sulfide in metal ion reservoir 306 may be greater than the concentration of silver selenide or silver sulfide in solid electrolyte 308. The splitter 310 can help maintain multiple threshold voltages programmed to the cell elements of the memory cell 301. In some embodiments, the separator 310 includes a dielectric, such as silicon oxide (SiO), aluminum oxide (AlO), gadolinium oxide (GdO), or any combination thereof.

Referring to fig. 3B, the memory device 300 may be a 3D cross-point memory device, in which the cell elements may be in a dual stack memory/selector structure. For ease of description, the structure, function, and materials of the same components described above with respect to memory device 300 in fig. 3A are not repeated. As shown in fig. 3B, another memory cell array 321 in the same plane may be formed above the memory cell array 301 and share the word line 318 with the memory cell array 301. Each memory cell 321 may include a bottom-to-top cell element including a stack of solid electrolyte 308, separator 310, and metal ion reservoir 306, similar to memory cell 301. A plurality of bit lines 324 may be formed over and in contact with memory cells 321 to drive memory cells 321 along word lines 318. Like insulating structures 303, insulating structures 325 can also be formed over word lines 318 and laterally between memory cells 321. By vertically stacking more layers of memory cell arrays having word lines and bit lines in a cross-point architecture, the array cell density of memory device 300 may be continuously increased.

It should be understood that the structure of the memory cell 301 is not limited to the examples in fig. 3A and 3B, and may include any suitable structure. In one example, in other examples, the relative positions of the metal ion reservoir 306 and the solid electrolyte 308 may be switched. In another example, an electrode may be disposed between the metal ion reservoir 306 and the word line 318. As shown in fig. 3C, according to some embodiments, the electrode 312 is vertically positioned between, i.e., sandwiched between, the metal ion reservoir 306 and the word line 318. For example, the electrode 312 may be in contact with the metal ion reservoir 306 and the word line 318 on opposite sides thereof. The electrode 312 may comprise a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, metal nitrides, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, the electrode 312 comprises tungsten or titanium nitride (TiN). Although not shown, it is understood that another electrode may also be disposed between the solid electrolyte 308 and the bit line 304 in some examples. That is, the memory cell 301 may also include a first electrode between the metal ion reservoir 306 and the word line 318 and/or a second electrode between the solid electrolyte 308 and the bit line 304.

It should also be understood that the cell element of the memory cell 301 is not limited to the examples in fig. 3A and 3B, as long as the cell element can be programmed to have multiple threshold voltages in the selector-less memory cell 301. Fig. 4 illustrates a side view of a cross-section of another exemplary memory cell 401 having multiple threshold voltages, according to some embodiments of the present disclosure. In some examples, memory cell 401 may replace memory cell 301 in memory device 300 in FIGS. 3A-3C.

As shown in fig. 4, the memory cell 401 may include a cell element without a selector. That is, the memory unit 401 may be a selector-less memory unit. Unlike known memory cells each including a cell element and a selector connected in series, the cell element of the memory cell 401 can perform dual functions of storing data and converting because it can be configured to have a plurality of threshold voltages without a separate selector. A single data bit may be stored in each memory cell 401 and may be written or read by varying the voltage applied to the corresponding cell element, which eliminates the need for a selector (e.g., an OTS selector, transistor, or diode). As shown in fig. 4A, the cell element of each memory 401 may include doped arsenic selenide 402. In some embodiments, arsenic selenide 402 is doped with silver (Ag), copper (Cu), silicon (Si), germanium (Ge), or any combination thereof. In some embodiments, memory cell 401 further includes electrodes 404 on one or both sides of doped arsenic selenide 402 to contact word lines and/or bit lines (e.g., word line 318 and bit line 304 in fig. 3A-3C).

Cell elements (e.g., memory cells 301 and 401) in the selector-less memory cells disclosed herein can be configured to have multiple threshold voltages (e.g., threshold switching voltages) at different levels, such as a first threshold voltage Vt1 and a second threshold voltage Vt2 that is greater than Vt1, as shown in fig. 9. Two different threshold voltages, Vt1 and Vt2 (or even more) can be set using a programming operation, i.e., programming to cell elements of a selector-less memory cell, by positive or negative programming pulses having different amplitudes and/or widths as described in detail below. In some embodiments, when a first voltage pulse is applied across a cell element, the cell element is configured to have a first threshold voltage Vt 1; when the second voltage pulse is applied to the cell element, the cell element is configured to have a second threshold voltage Vt 2. In some embodiments, the second threshold voltage Vt2 is greater than the first threshold voltage Vt2 when the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, and/or when the width of the first voltage pulse is greater than the width of the second voltage pulse. That is, the first program pulse having a low amplitude and/or a long width may program the first threshold voltage Vt1, the first threshold voltage Vt1 being less than the second threshold voltage Vt2 programmed by the second program pulse having a high amplitude and/or a short width.

With respect to the memory cell 301 in fig. 3A-3C, a positive programming pulse (e.g., a positive voltage pulse) applied to the solid electrolyte 308 from the metal ion reservoir 306 (e.g., in the negative z-direction in fig. 3A-3C) can be used to program the threshold voltage of the memory cell 301. In some embodiments, the cell elements of memory cell 301 are configured to be isolated (i.e., native/primitive cells) prior to a programming operation. In some embodiments, the cell element of the memory cell 301 is configured to have a first threshold voltage Vt1 when a first positive voltage pulse is applied from the metal ion reservoir 306 to the solid electrolyte 308, i.e., using a first programming operation. In some embodiments, the cell elements of the memory cell 301 are configured to be insulated again when a negative voltage pulse is applied from the solid electrolyte 308 to the metal ion reservoir 306, i.e., when an erase operation is used. In some embodiments, the cell element of the memory cell 301 is configured to have a second threshold voltage Vt2 when a second positive voltage pulse is again applied from the metal ion reservoir 306 to the solid electrolyte 308, i.e., using a second programming operation. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the second positive voltage pulse is less than the width of the first positive voltage pulse. In yet another example, the amplitude of the second positive voltage pulse is greater than the amplitude of the first positive voltage pulse, and the width of the second positive voltage pulse is less than the width of the first positive voltage pulse. In any of the three examples described above, the second threshold voltage Vt2 may be programmed to be greater than the first threshold voltage Vt 1. In some embodiments, the magnitude of the negative voltage pulse is greater than the magnitude of the first and second positive voltage pulses in order to set the cell element of the memory cell 301 back to insulation, i.e., to erase the memory cell 301.

With respect to memory cell 401 in fig. 4, the cell element may not be configured to be insulated in the native/original cell or using an erase operation, which is different from memory cell 301. In some embodiments, the cell element of memory cell 401 is configured to have a native threshold voltage Vtn as opposed to an isolated prior to a programming operation (i.e., a native/original cell). In some embodiments, the cell of memory cell 401 is configured to have a first threshold voltage Vt1 when a first voltage pulse is applied across the cell, i.e., using a first programming operation. In some embodiments, the cell of the memory cell 401 is configured to have the second threshold voltage Vt2 when the second voltage pulse is applied to the cell again, i.e., using the second programming operation. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the second voltage pulse is less than the width of the first voltage pulse. In yet another example, the second voltage pulse has an amplitude greater than the amplitude of the first voltage pulse, and the second voltage pulse has a width less than the width of the first voltage pulse. In any of the three examples described above, the second threshold voltage Vt2 may be programmed to be greater than the first threshold voltage Vt 1. In some embodiments, no erase operation is performed to erase the cell of memory cell 401, i.e., the cell is set to be insulated.

Fig. 5A and 5B illustrate schematic diagrams of the operation of an exemplary memory cell array having multiple threshold voltages, according to some embodiments of the present disclosure. As shown in fig. 5A and 5B, an array of memory cells 502 (e.g., corresponding to memory cell 301 in fig. 3A-3C or memory cell 401 in fig. 4) may be formed as intersections (cross-points) of word lines 504 (e.g., corresponding to word lines 318 in fig. 3A-3C) and bit lines 506 (e.g., corresponding to bit lines 304 in fig. 3A-3C), respectively. Each memory cell 502 may be a selector-less memory cell having a cell element configured to have multiple threshold voltages.

In FIG. 5A, to operate the array of memory cells 502, the word line voltage (V) has a value of 0 or V/2_w) A bit line voltage (V) that may be applied to each word line 504 and has a value of 0 or-V/2_b) May be applied to each bit line 506. Thus, the voltage (Va) applied to each memory cell 502 may be 0, V/2, or V. In some embodiments, V is set to any of the voltage pulses described above for programming or erasing the cell elements of memory cell 502. As shown in fig. 5A, only the memory cells 502 at the intersection of a pair of word lines 504 and bit lines 506 with a non-zero voltage (Va ═ V, in the dashed circle in fig. 5A) can be selected for programming or erasing. According to some embodiments, other memory cells 502(Va ═ 0 or V/2) at each intersection of a respective pair of word lines 504 and bit lines 506 with at least one zero voltage are not selected for programming or erasing.

In FIG. 5B, to operate the array of memory cells 502, the word line voltage (V) has a value of V/2 or V_w) May be applied to each word line 504 and have a bit line voltage (V) of 0 or V/2 value_b) May be applied to each bit line 506. Thus, the voltage (Va) applied to each memory cell 502 may be 0, V/2, or V. In some embodiments, V is set to the single cell described above for programming or erasing memory cell 502Any voltage pulse of the cell. As shown in fig. 5B, only the memory cell 502 at the intersection of a pair of word line 504 and bit line 506 with a non-V/2 voltage (Va ═ V, in the dashed circle in fig. 5B) can be selected for programming or erasing. According to some embodiments, other memory cells 502(Va ═ 0 or V/2) at each intersection of a respective pair of word lines 504 and bit lines 506 having at least one V/2 voltage are not selected for programming or erasing.

Fig. 6A-6H illustrate an exemplary fabrication process for forming a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. Fig. 7 illustrates a flow diagram of an exemplary method 700 for forming a memory device having memory cells with multiple threshold voltages, in accordance with some embodiments of the present disclosure. Examples of the memory devices depicted in fig. 6A-6H and 7 include the memory device 300 depicted in fig. 3A-3C. Fig. 6A to 6H and 7 will be described together. It should be understood that the operations shown in method 700 are not comprehensive, and that other operations may be performed before, after, or between any of the shown operations. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 7.

Referring to fig. 7, a method 700 begins with operation 702, where a cell element layer is formed on a substrate. In some embodiments, to form the cell element layer, the solid electrolyte layer, the separator layer, and the metal ion storage layer are deposited sequentially. The metal ion reservoir may include at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide. The solid electrolyte may include at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride. The separator may comprise at least one of silica, alumina or gadolinium oxide. In some embodiments, before forming the unit cell layer, a conductor layer is formed on the substrate so that the unit cell layer is formed on the conductor layer.

Referring to fig. 6A, a conductor layer 604 is formed on a substrate 602. In some embodiments, the metal layer, e.g., tungsten layer, is deposited using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

As shown in fig. 6A, a unit element layer 605 is formed on the conductor layer 604. In some embodiments, to form the cell element layer 605, the solid electrolyte layer 606, the separation layer 612, and the metal ion storage layer 614 are sequentially deposited on the conductor layer 604 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. For example, the metal ion storage layer 614 may include silver, copper, silver sulfide, copper sulfide, silver selenide, copper selenide, or any combination thereof, the solid electrolyte layer 606 may include germanium selenide, germanium sulfide, silver selenide, silver sulfide, copper telluride, or any combination thereof, and the separation layer 612 may include silicon oxide, aluminum oxide, gadolinium oxide, or any combination thereof. In one example, the thickness of the solid electrolyte layer 606 may be between about 10 nanometers and about 100 nanometers, the thickness of the metal ion storage layer 614 between about 5 nanometers and about 50 nanometers, and the thickness of the separation layer 612 between about 1 nanometer and about 10 nanometers.

In some embodiments, dielectric layer 618 is formed on cell element layer 605 by depositing a dielectric material (e.g., silicon nitride) using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to serve as an etch mask for cell element layer 605 in subsequent processes. In some embodiments, an electrode layer (not shown) is formed between the cell element layer 605 and the dielectric layer 618 by depositing a conductive material such as tungsten using one or more thin film deposition processes (including, but not limited to, CDV, PVD, ALD, or any combination thereof) to form an electrode (e.g., electrode 312 in fig. 3C) between the cell element 622 and the conductor layer (wordline) 630.

In some embodiments, to form the cell element layer, an arsenic selenide layer is deposited and doped with at least one of silver, copper, silicon, or germanium. As shown in fig. 4, the arsenic selenide layer 402 (e.g., as shown in fig. 6A) may be deposited on the conductor layer 604 using one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. Ion implantation and/or thermal diffusion may then be used to dope arsenic selenide layer 402 with silver, copper, silicon, and/or germanium. In some embodiments, in situ doping is performed to dope the arsenic selenide layer 402 while the arsenic selenide layer 402 is deposited, for example, using CVD.

The method 700 proceeds to operation 704, as shown in fig. 7, where a plurality of gaps are formed through the cell layer to divide the cell layer into a plurality of cell elements, each cell element configured to have a plurality of threshold voltages. In some embodiments, in order to form the plurality of gaps, the unit cell layer is double-patterned, and the double-patterned unit cell layer is etched through.

As shown in fig. 6B, the cell element layer 605, the conductor layer 604, and the dielectric layer 618 (shown, for example, in fig. 6A) are etched through in the y-direction (e.g., bit line direction) to form a plurality of gaps 620. In some embodiments, the cell element layer 605, the conductor layer 604, and the dielectric layer 618 are first double patterned. For example, dielectric layer 618 may be patterned by photolithography, development, and etching. Double patterning may include, but is not limited to, photo-etch-photo-etch (LELE) pitch division or self-aligned double patterning (SADP) to control the critical dimensions of the unit cell 622 formed from the unit cell layer 605. In some embodiments, the double patterned cell element layer 605 and the conductor layer 604 are then etched through in the y-direction to form parallel gaps 620 in the y-direction using the double patterned dielectric layer 618 as an etch mask. The cell element layer 605 and the conductor layer 604 may be etched by one or more wet and/or dry etching processes, such as Deep Reactive Ion Etching (DRIE), using a double patterned etch mask to simultaneously form the parallel gaps 620. According to some embodiments, cell elements 622 separated by gaps 620 are thereby formed, and each cell element 622 includes a portion of cell element layer 605 (e.g., solid electrolyte layer 606, separation layer 612, and metal ion storage layer 614, or doped arsenic selenide layer 402 in fig. 4). As described in detail above, each cell element 622 may be configured to have multiple threshold voltages. In some embodiments, the conductive layers 604 are also separated by gaps 620, respectively forming bit lines under the cell elements 622 and in contact with the cell elements 622.

The method 700 proceeds to operation 706, as shown in fig. 7, where a plurality of insulating structures are formed in a plurality of gaps between a plurality of unit cells. In some embodiments, to form the plurality of insulating structures, one or more dielectric layers are deposited on and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the plurality of unit elements.

As shown in fig. 6C, an encapsulation layer 624 is deposited over the cell 622 and into the gap 620 to protect the exposed cell 622. In some embodiments, a dielectric layer, such as a silicon nitride layer, is deposited along the sidewalls and top surface of the cell elements 622 to completely cover the cell elements 622 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, any other suitable deposition process, or any combination thereof, to form the encapsulation layer 624. In some embodiments, the encapsulation layer 624 is deposited using ALD to form a thin conformal layer without completely filling the gaps 620 between the cell elements 622.

As shown in fig. 6D, a cover layer 626 is deposited over the encapsulation layer 624 to fill the gap 620. In some embodiments, a dielectric layer, such as a silicon oxide layer, is deposited on the encapsulation layer 624 and into the gap 620 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, any other suitable deposition process, or any combination thereof, to form the cap layer 626. In some embodiments, to completely fill gap 620 without an air gap, capping layer 626 is formed by depositing silicon oxide using ALD or flowable CVD, or by spin-on dielectric (SOD). According to some embodiments, lateral insulating structures 629 between the unit elements 622 are thereby formed, each including an encapsulation layer 624 and a cover layer 626.

As shown in fig. 6E, the cover layer 626 and the encapsulation layer 624 are planarized using a planarization process such as Chemical Mechanical Polishing (CMP), grinding, or etching to remove the partially planarized cover layer 626 and encapsulation layer 624 on the top surface of the unit elements 622. In some embodiments, the planarization process continues to remove the dielectric layer 618 (e.g., as shown in fig. 6D) to expose the metal ion storage layer 614 of each cell element 622. Although fig. 6A-6E illustrate only the gap etch and fill process in the y-direction for ease of description, it should be understood that to form a pillar-shaped memory cell that can be self-aligned at the intersection of a vertical bit line and a word line, the cell element layer 605 may need to be etched in two vertical directions (e.g., both the x-direction and the y-direction) to form a vertical gap that is filled with an insulating structure. The same gap etch and fill processes described above with respect to fig. 6A-6E may be performed again in the x-direction as desired.

The method 700 proceeds to operation 708, as shown in FIG. 7, where a plurality of word lines are formed over and in contact with a plurality of cell elements. As shown in fig. 6F, a conductor layer 630 is formed on the unit element 622 and the insulating structure 629. In some embodiments, a metal layer, such as a tungsten layer, is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The conductor layer 630 can then be patterned using, for example, double patterning and etched in the x-direction (e.g., word line direction) of fig. 6F, for example, using RIE, to form a plurality of word lines over the cell elements 622 (e.g., metal ion storage layer 614) and in contact with the cell elements 622.

In some embodiments, another array of cell elements over and in contact with the word lines is formed using a process similar to that described above with respect to fig. 6A-6E and 7. As shown in fig. 6G, a cell element layer 631 is formed on the conductor layer 630 (forming a word line), and a conductor layer 644 is formed on the cell element layer 631. In some embodiments, to form cell element layer 631 and conductor layer 644, solid electrolyte layer 632, separation layer 638, metal ion storage layer 640, and conductor layer 644 are sequentially deposited using one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. As shown in fig. 6H, cell elements 651 each comprise a portion of solid electrolyte layer 632, separation layer 638 and metal ion storage layer 640, and are laterally separated by insulating structure 649, cell element 651 being formed from cell element layer 631 using the process described above with respect to fig. 6B-6E. The conductor 644 can be patterned and etched to form a plurality of bitlines respectively over and in contact with the cell element 651. For ease of description, the processes described above with reference to fig. 6A-6E for forming similar components are not repeated.

FIG. 8 illustrates a flow chart of an exemplary method 800 for operating a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. Examples of the memory device depicted in FIG. 8 include the memory device 300 depicted in FIGS. 3A-3C or any other memory device disclosed herein. It should be understood that the operations shown in method 800 are not comprehensive and that other operations may be performed before, after, or between any of the shown operations. Further, some operations may be performed concurrently or in a different order than shown in FIG. 8.

Referring to fig. 8, a method 800 begins with operation 802 where one of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. For example, the memory cell 301 may be programmed to a first threshold voltage Vt1 by applying a first positive voltage pulse from the metal ion reservoir 306 to the solid electrolyte 308.

The method 800 proceeds to operation 804, as shown in FIG. 8, where the memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. In some embodiments, the second threshold voltage is greater than the first threshold voltage at least one of (i) the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, or (ii) the width of the first voltage pulse is greater than the width of the second voltage pulse. For example, the memory cell 301 can be programmed to a second threshold voltage Vt2 that is greater than the first threshold voltage Vt1 by applying a second positive voltage pulse from the metal ion reservoir 306 to the solid electrolyte 308. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the first voltage pulse is greater than the width of the second voltage pulse. In yet another example, the second voltage pulse has an amplitude greater than an amplitude of the first voltage pulse, and the first voltage pulse has a width greater than a width of the second voltage pulse.

In some embodiments, the memory cell is programmed to be insulated by applying a third voltage pulse between the bit line and the word line. The polarity of the third voltage pulse may be opposite to the polarity of the first voltage pulse or the polarity of the second voltage pulse. For example, the memory cell 301 may be programmed to be contained (i.e., erased) by applying a negative voltage pulse from the solid electrolyte 308 to the metal ion reservoir 306.

The method 800 proceeds to operation 806, as shown in FIG. 8, where the memory cell is sensed at a sensing voltage between the first and second threshold voltages. For example, the memory cell 301 can be sensed at a sense voltage Vs between the first and second threshold voltages Vt1 and Vt2, e.g., Vt1< Vs < Vt 2.

According to one aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell being arranged at an intersection of a corresponding bit line of the plurality of bit lines and a corresponding word line of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

In some embodiments, the cell element comprises a stacked metal ion reservoir, a solid electrolyte, and a separator positioned vertically between the metal ion reservoir and the solid electrolyte.

In some embodiments, the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.

In some embodiments, the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.

In some embodiments, the separator comprises a dielectric. In some embodiments, the dielectric comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.

In some embodiments, the thickness of the solid electrolyte is between about 10 nanometers and about 100 nanometers.

In some embodiments, the thickness of the solid electrolyte is between about 10 nanometers and about 100 nanometers, the thickness of the metal ion reservoir is between about 5 nanometers and about 50 nanometers, and the thickness of the separator is between about 1 nanometer and about 10 nanometers.

In some embodiments, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte. In some embodiments, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte. In some embodiments, the cell element is configured to be insulated when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir.

In some embodiments, the second threshold voltage is greater than the first threshold voltage in at least one of (i) the second amplitude of the second positive voltage pulse is greater than the first amplitude of the first positive voltage pulse, or (ii) the first width of the first positive voltage pulse is greater than the second width of the second positive voltage pulse.

In some embodiments, the cell element comprises doped arsenic selenide. In some embodiments, the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

In some embodiments, when the first voltage pulse is applied to the cell element, the cell element is configured to have a first threshold voltage of a plurality of threshold voltages. In some embodiments, when the second voltage pulse is applied to the cell element, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages.

In some embodiments, the second threshold voltage is greater than the first threshold voltage in at least one of (i) the second amplitude of the second voltage pulse is greater than the first amplitude of the first voltage pulse, or (ii) the first width of the first voltage pulse is greater than the second width of the second voltage pulse.

In some embodiments, the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

According to another aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell being disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes a stacked metal ion reservoir, a solid electrolyte, and a separator vertically positioned between the metal ion reservoir and the solid electrolyte.

In some embodiments, the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide, the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride, and the separator comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.

According to yet another aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell being disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines. Each of the plurality of memory cells includes doped arsenic selenide.

In some embodiments, the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

In accordance with yet another aspect of the present disclosure, a method for forming a memory device is disclosed. A unit cell layer is formed. A plurality of gaps are formed through the cell layer to divide the cell layer into a plurality of cell elements, each cell element configured to have a plurality of threshold voltages. A plurality of insulating structures are formed in the plurality of gaps between the plurality of unit cells.

In some embodiments, to form the cell element layer, the solid electrolyte layer, the separator layer, and the metal ion storage layer are deposited sequentially.

In some embodiments, in order to form the plurality of gaps, the unit cell layer is double-patterned, and the double-patterned unit cell layer is etched through.

In some embodiments, to form the plurality of insulating structures, one or more dielectric layers are deposited on the plurality of cell elements and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the cell elements.

In some embodiments, after forming the plurality of insulating structures, a plurality of word lines are formed over and in contact with the plurality of cell elements.

According to another aspect of the present disclosure, a method for operating a 3D memory device is disclosed. The memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell being disposed at an intersection of a corresponding bit line of the plurality of bit lines and a corresponding word line of the plurality of word lines. One of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines. The memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. The memory cell is sensed at a sensing voltage between the first and second threshold voltages.

In some embodiments, the memory cell is programmed to be insulated by applying a third voltage pulse between the bit line and the word line. In some embodiments, the third polarity of the third voltage pulse is opposite to the first polarity of the first voltage pulse or the second polarity of the second voltage pulse.

The foregoing description of the specific embodiments will so reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, the memory device comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells, each memory cell disposed at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines,

wherein each of the plurality of memory cells includes a cell element without a selector, and the cell element is configured to have a plurality of threshold voltages.

2. The memory device of claim 1, wherein the cell element comprises a stacked metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.

3. The memory device of claim 2, wherein the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.

4. The memory device of claim 2 or 3, wherein the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.

5. The memory device of any one of claims 2-4, wherein the separator comprises a dielectric.

6. The memory device of claim 5, wherein the dielectric comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.

7. The memory device of any one of claims 2-6, wherein the solid electrolyte has a thickness between about 10 nanometers and about 100 nanometers, the metal ion reservoir has a thickness between about 5 nanometers and about 50 nanometers, and the separator has a thickness between about 1 nanometer and about 10 nanometers.

8. The storage device of any one of claims 2-7, wherein

The cell element is configured to have a first threshold voltage of the plurality of threshold voltages when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte;

the cell element is configured to have a second threshold voltage of the plurality of threshold voltages when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte; and

the cell element is configured to be insulated when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir.

9. The memory device of claim 8, wherein the second threshold voltage is greater than the first threshold voltage in the event of at least one of: (i) a second amplitude of the second positive voltage pulse is greater than a first amplitude of the first positive voltage pulse, or (ii) a first width of the first positive voltage pulse is greater than a second width of the second positive voltage pulse.

10. The memory device of claim 1, wherein the cell element comprises doped arsenic selenide.

11. The memory device of claim 10, wherein the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

12. The memory device of claim 10 or 11, wherein

When a first voltage pulse is applied across the cell element, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages; and

the cell element is configured to have a second threshold voltage of the plurality of threshold voltages when a second voltage pulse is applied across the cell element.

13. The memory device of claim 12, wherein the second threshold voltage is greater than the first threshold voltage in the event of at least one of: (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse.

14. The memory device of any one of claims 1-13, wherein the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

15. A memory device, the memory device comprising:

a plurality of bit lines;

a plurality of word lines; and

wherein each of the plurality of memory cells comprises a stacked metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.

16. The memory device of claim 15, wherein

The metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide;

the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride; and

the separator includes at least one of silica, alumina, or gadolinium oxide.

17. The memory device of claim 15 or 16, wherein

The memory cell is configured to have a first threshold voltage when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte;

the memory cell is configured to have a second threshold voltage when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte; and

the memory cell is configured to be insulated when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir.

18. A memory device, the memory device comprising:

a plurality of bit lines;

a plurality of word lines; and

wherein each memory cell of the plurality of memory cells comprises doped arsenic selenide.

19. The memory device of claim 18, wherein the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

20. The memory device of claim 18 or 19, wherein

When a first voltage pulse is applied across the memory cell, the memory cell is configured to have a first threshold voltage; and

the memory cell is configured to have a second threshold voltage when a second voltage pulse is applied across the memory cell.

21. A method for forming a memory device, the method comprising:

forming a unit element layer;

forming a plurality of gaps through the unit cell layer to separate the unit cell layer into a plurality of unit cells, each of the unit cells configured to have a plurality of threshold voltages; and

forming a plurality of insulating structures in the plurality of gaps between the plurality of unit elements.

22. The method of claim 21, wherein forming the cell element layers comprises sequentially depositing layers of a solid electrolyte, a separator, and a metal ion reservoir.

23. The method of claim 22, wherein:

the separator includes at least one of silica, alumina, or gadolinium oxide.

24. The method of claim 21, wherein forming the cell element layer comprises:

depositing an arsenic selenide layer; and

doping the arsenic selenide layer with at least one of silver, copper, silicon, or germanium.

25. The method of any of claims 21-24, wherein forming the plurality of gaps comprises:

double patterning the unit cell layer; and

etching through the double patterned unit cell layer.

26. The method of any of claims 21-25, wherein forming the plurality of insulating structures comprises:

depositing one or more dielectric layers on the plurality of unit elements and into the plurality of gaps to fill the plurality of gaps; and

planarizing the deposited dielectric layer to expose the plurality of unit cells.

27. The method according to any one of claims 21-26, further comprising: after forming the plurality of insulating structures, a plurality of word lines over and in contact with the plurality of cell elements are formed.

28. A method for operating a memory device, the memory device comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each of the memory cells being arranged at an intersection of a respective bit line of the plurality of bit lines and a respective word line of the plurality of word lines, the method comprising:

programming one of the memory cells to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines;

programming the memory cell to a second threshold voltage by applying a second voltage pulse between the bit line and the word line; and

sensing the memory cell at a sensing voltage between the first threshold voltage and the second threshold voltage.

29. The method of claim 28, further comprising: programming the memory cell to be insulated by applying a third voltage pulse between the bit line and the word line, wherein a third polarity of the third voltage pulse is opposite to the first polarity of the first voltage pulse or the second polarity of the second voltage pulse.

30. The method of claim 28 or 29, the second threshold voltage being greater than the first threshold voltage in the event of at least one of: (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse.