WO2023004609A1

WO2023004609A1 - Phase-change memory device and method for forming the same

Info

Publication number: WO2023004609A1
Application number: PCT/CN2021/108810
Authority: WO
Inventors: Wenlin PENG; Jun Liu; Haibo YANG; Guangyu Liu; Rui KUANG
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2023-02-02
Also published as: CN113795937A

Abstract

In certain aspects, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each one of the plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each one of the plurality of memory cells includes stacked a phase-change memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. An area of the top surface is smaller than that of the bottom surface.

Description

PHASE-CHANGE MEMORY DEVICE AND METHOD FOR FORMING THE SAME

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

In one aspect, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each one of the plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each one of the plurality of memory cells includes stacked a phase-change memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. An area of the top surface is smaller than that of the bottom surface.

In another aspect, a phase-change memory (PCM) cell includes a PCM element and a selector. The PCM element includes a top surface and a bottom surface. An area of the top surface is smaller than that of the bottom surface.

In still another aspect, a method for forming a memory device includes sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a phase-change memory (PCM) element on a substrate, depositing a mask on the PCM element, etching the PCM element via an opening of the mask to form a recess in the PCM element, removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess, etching the sacrificial insulation layer to form an insulation layer in the recess, depositing a third electrode on the PCM element and the insulation layer, and depositing a word line on the third electrode.

In yet another aspect, a method for forming a phase-change memory (PCM) cell includes sequentially depositing a first electrode, a selector, a second electrode, and a PCM element, depositing a mask on the PCM element, etching the PCM element via an opening of the mask to form a recess in the PCM element, removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess, etching the sacrificial insulation layer to form an insulation layer in the recess, and depositing a third electrode on the PCM element and the insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of an exemplary 3D cross-point (XPoint) memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a side view of a cross-section of a 3D phase-change memory (PCM) memory device.

FIG. 3 illustrates a side view of a cross-section of an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

FIG. 4A illustrates a schematic of current distribution in an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

FIG. 4B illustrates a 3D schematic of an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

FIG. 5 illustrates a schematic diagram of the operation of an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

FIGs. 6A-6J illustrate an exemplary fabrication process for forming a 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method for forming a 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some implementations, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other implementations whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. PCM cells can be vertically stacked in 3D to form a 3D PCM.

3D PCMs include 3D cross-point (XPoint) memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device 100, according to some implementations of the present disclosure. 3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102.3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along the word line direction in the plan view. Each word line 106 is intersected with each lower bit line 102 and each upper bit line 104 in the plan view. In some implementations, each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.

FIG. 2 illustrates a side view of a cross-section of an exemplary memory device 200, according to some aspects of the present disclosure. In FIG. 2, memory device 200 includes a substrate 202, a plurality of parallel bit lines 204 formed on substrate 202, and a plurality of parallel word lines 216 formed above bit lines 204. Substrate 202 may include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. Bit lines 204 and word lines 216 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of bit lines 204 and word lines 216 includes a metal, such as tungsten.

Memory device 200 may be divided by isolation layer 222 to form a plurality of separated pillar-shaped memory cell 201. In some implementations, each pillar-shaped memory cell 201 is disposed at an intersection of a respective one of bit lines 204 and a respective one of word lines 216. Each pillar-shaped memory cell 201 may be accessed individually by a current applied through a respective word line 216 and a respective bit line 204 in contact with pillar-shaped memory cell 201. Each pillar-shaped memory cell 201 has a vertical pillar shape (e.g., similar to memory cell 108 in FIG. 1) , and isolation layer 222 may extend laterally in both x-direction and y-direction to separate pillar-shaped memory cells 201.

Each pillar-shaped memory cell 201 includes a first electrode layer 206 formed on bit line 204, a selector 208 formed on first electrode layer 206, and a second electrode layer 210 formed on selector 208. Pillar-shaped memory cell 201 further includes a phase-change memory (PCM) element 212 formed on second electrode layer 210, and a third electrode layer 214 formed on PCM element 212. First electrode layer 206, selector 208, and second electrode layer 210 are functioned and used as a selector in pillar-shaped memory cell 201. Second electrode layer 210, PCM element 212, and third electrode layer 214 are functioned and used as a storage element in pillar-shaped memory cell 201. It is understood that second electrode layer 210 is used as a common electrode in both the selector and the storage element.

First electrode layer 206 is formed on bit line 204 and is in contact with selector 208, so that first electrode layer 206 serves as a current path and may be formed of a conductive material. In some implementations, first electrode layer 206 may be a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, first electrode layer 206 may be a titanium nitride (TiN) layer, but the present disclosure is not limited thereto.

Selector 208 is formed on first electrode layer 206, and the resistance of selector 208 is changed in response to a selection voltage applied between first electrode layer 206 and second electrode layer 210. In some implementations, selector 208 may be an ovonic threshold switch (OTS) device made of at least one of oxygen (O) , sulfur (S) , selenium (Se) , tellurium (Te) , germanium (Ge) , antimony (Sb) , silicon (Si) , or arsenic (As) . The OTS device is formed by OTS material exhibiting an OTS property. With regard to the function of selector 208 including the OTS material, when a voltage lower than a threshold voltage Vth is applied between first electrode layer 206 and second electrode layer 210, selector 208 may be in a high-resistance state preventing a current from flowing therethrough, and when a voltage higher than the threshold voltage Vth is applied between first electrode layer 206 and second electrode layer 210, selector 208 may be in a low-resistance state, allowing a current to flow therethrough.

Second electrode layer 210 is formed between the selector and the storage element and functions as one of the electrodes of both the selector and the storage element, so second electrode layer 210 should be formed by a thermal and electrical insulating material to reduce temperature and electrical interference from the selector and the storage element. Second electrode layer 210 may be formed of or include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, second electrode layer 210 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some implementations, second electrode layer 210 may be formed by amorphous carbon.

PCM element 212 is formed on second electrode layer 210. PCM element 212 is a material whose phase can be reversibly switched between amorphous and crystalline states, depending on a heating time. In general, PCM element 212 may exist in an amorphous and one or sometimes several crystalline phases and can be rapidly and repeatedly switched between these phases. In some implementations, PCM element 212 may include a material whose phase can be reversibly changed using Joule’s heat, which is generated when a voltage is applied between second electrode layer 210 and third electrode layer 214, and the resistance of PCM element 212 may be changed by such a change in phase. In some implementations, PCM element 212 may include a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) . In some implementations, PCM element 212 may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) , or TeGeSbS. In some implementations, PCM element 212 may be GeSbTe.

Third electrode layer 214 is formed on PCM element 212. In some implementations, the material of third electrode layer 214 may be similar to the material of first electrode layer 206 or second electrode layer 210. In some implementations, the material of third electrode layer 214 may be similar to the material of second electrode layer 210. Then, word line 216 is formed on third electrode layer 214.

It is understood that the position of bit lines 204 and word line 216 corresponding to pillar-shaped memory cell 201 may be exchanged according to different memory designs. In other words, first electrode layer 206 may be formed on a word line, and a bit line may be formed on third electrode layer 214.

FIG. 3 illustrates a side view of a cross-section of an exemplary memory device 300, according to some aspects of the present disclosure. In FIG. 3, memory device 300 includes a substrate 302, a plurality of parallel bit lines 304 formed on substrate 302, and a plurality of parallel word lines 316 formed above bit lines 304. Substrate 302 may include silicon (e.g., single crystalline silicon) , SiGe, GaAs, Ge, SOI, or any other suitable materials. Bit lines 304 and word lines 316 can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of bit lines 304 and word lines 316 includes a metal, such as tungsten.

Memory device 300 may be divided by isolation layer 322 to form a plurality of separated pillar-shaped memory cell 301. In some implementations, each pillar-shaped memory cell 301 is disposed at an intersection of a respective one of bit lines 304 and a respective one of word lines 316. Each pillar-shaped memory cell 301 may be accessed individually by a current applied through a respective word line 316 and a respective bit line 304 in contact with pillar-shaped memory cell 301. Each pillar-shaped memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in FIG. 1) , and isolation layer 322 may extend laterally in both x-direction and y-direction to separate pillar-shaped memory cells 301.

Each pillar-shaped memory cell 301 includes a first electrode layer 306 formed on bit line 304, a selector 308 formed on first electrode layer 306, and a second electrode layer 310 formed on selector 308. Pillar-shaped memory cell 301 further includes a PCM element 312 having a shape of polygonal cylinder with narrow top and wide bottom formed on second electrode layer 310, a third electrode layer 314 formed on PCM element 312, and an insulation layer 309 formed between third electrode layer 314 and PCM element 312. The polygonal cylinder includes a cylinder, a triangular prism, a quadrangular prism, a pentagonal prism, a hexagonal prism, a cone, a truncated cone, a triangular pyramid, a quadrangular pyramid, a pentagonal pyramid, a hexagonal pyramid, a triangular frustum, a quadrangular frustum, a pentagonal frustum, or a hexagonal frustum. First electrode layer 306, selector 308, and second electrode layer 310 are functioned and used as a selector in pillar-shaped memory cell 301. Second electrode layer 310, PCM element 312, and third electrode layer 314 are functioned and used as a storage element in pillar-shaped memory cell 301. It is understood that second electrode layer 310 is used as a common electrode in both the selector and the storage element. PCM element 312 having a shape of narrow top and wide bottom is used to reduce the contact interface area between PCM element 312 and third electrode layer 314, thereby increasing the current density across the contact interface and thus, reduce the energy consumption of pillar-shaped memory cell 301. Insulation layer 309 is used to reduce the heat dissipation of the contact interface, which increases the efficiency of heating PCM element 312 having a shape of narrow top and wide bottom and therefore reduces the energy consumption of pillar-shaped memory cell 301. The details of PCM element 312 and insulation layer 309 will be discussed later.

First electrode layer 306 is formed on bit line 304 and is in contact with selector 308, so that first electrode layer 306 serves as a current path and may be formed of a conductive material. In some implementations, first electrode layer 306 may be a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, first electrode layer 306 may be a titanium nitride (TiN) layer, but the present disclosure is not limited thereto.

Selector 308 is formed on first electrode layer 306, and the resistance of selector 308 is changed in response to a selection voltage applied between first electrode layer 306 and second electrode layer 310. In some implementations, selector 308 may be an OTS device made of at least one of O, S, Se, Te, Ge, Sb, Si, or As. The OTS device is formed by OTS material exhibiting an OTS property. With regard to the function of selector 308 including the OTS material, when a voltage lower than a threshold voltage Vth is applied between first electrode layer 306 and second electrode layer 310, selector 308 may be in a high-resistance state preventing a current from flowing therethrough, and when a voltage higher than the threshold voltage Vth is applied between first electrode layer 306 and second electrode layer 310, selector 308 may be in a low-resistance state, allowing a current to flow therethrough.

Second electrode layer 310 is formed between the selector and the storage element and functions as one of the electrodes of both the selector and the storage element, so second electrode layer 310 should be formed by a thermal and electrical insulating material to reduce temperature and electrical interference from the selector and the storage element. Second electrode layer 310 may be formed of or include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, second electrode layer 310 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some implementations, second electrode layer 310 may be formed by amorphous carbon.

PCM element 312 is formed on second electrode layer 310. PCM element 312 includes a material whose phase can be reversibly switched between amorphous and crystalline states, depending on a heating time. In general, the material of PCM element 312 may exist in an amorphous and one or sometimes several crystalline phases and can be rapidly and repeatedly switched between these phases. In some implementations, PCM element 312 may include a material whose phase can be reversibly changed using Joule’s heat, which is generated when a voltage is applied between second electrode layer 310 and third electrode layer 314, and the resistance of PCM element 312 may be changed by such a change in phase. In some implementations, PCM element 312 may include a chalcogenide composition including at least one of Ge, Sb, Te, In, or Ga. In some implementations, PCM element 312 may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) , or TeGeSbS. In some implementations, PCM element 312 may be GeSbTe. PCM element 312 includes a shape of narrow top and wide bottom in a cross-section view of the x-z plane or the y-z plane. In some implementations, PCM element 312 has four cross-section views, and each cross-section view of PCM element 312 includes a shape of narrow top and wide bottom. In some implementations, PCM element 312 includes a pyramid shape with a flat top surface, a flat bottom surface, and a slope and/or a side surface between the flat top surface and the flat bottom surface. For instance, PCM element 312 may include a pyramid shape with a flat top surface, a flat bottom surface, a slope connected to the flat top surface, and a side surface connected between the slope and the flat bottom surface. The side surface is perpendicular to the bottom surface. In some implementations, PCM element 312 includes a pyramid shape with one or many steps, and each step includes a side surface extending vertically (z-direction) and perpendicular to the bottom surface, and a top surface connected to the side surface and extending laterally (x-or y-direction) and parallel to the bottom surface. In some implementations, each step includes a slope connected to the side surface and extending in a tilt direction. In some implementations, one or more slopes of PCM element 312 include an arc shape, which is formed due to the etching process, for instance, a wet etching process. In some implementations, the thickness of PCM element (which is measured from the top surface to the bottom surface) is 10 to 100 nm, for instance, 30 to 50 nm.

Third electrode layer 314 is formed on PCM element 312. In some implementations, the material of third electrode layer 314 may be similar to the material of first electrode layer 306 or second electrode layer 310. In some implementations, the material of third electrode layer 314 may be similar to the material of second electrode layer 310. Then, word line 316 is formed on third electrode layer 314.

Insulation layer 309 is formed between PCM element 312 and third electrode layer 314. In particular, insulation layer 309 is formed on a slope of PCM element 312 (e.g., slope 3121 in FIG. 4A) and co-planer with a top surface of PCM element 312 (e.g., top surface 3123 in FIG. 4A) . In some implementations, insulation layer 309 is embedded among isolation layer 322, PCM element 312, and third electrode layer 314, as shown in FIG. 3. In some implementations, a material of insulation layer 309 includes at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) . In some implementations, a thickness of insulation layer 309 (which is measured from top surface of PCM element 312 to the end of the slope 3121 as in FIG. 4A) is 5 to 30 nm, for instance, 10 to 20 nm.

It is understood that the position of bit lines 304 and word line 316 corresponding to pillar-shaped memory cell 301 may be exchanged according to different memory designs. In other words, first electrode layer 306 may be formed on a word line, and a bit line may be formed on third electrode layer 314.

FIG. 4A illustrates a schematic of current distribution in an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure. As shown in FIG. 4A, pillar-shaped memory cell 301 includes first electrode layer 306 formed on bit line (e.g., 304 in FIG. 3) , selector 308 formed on first electrode layer 306, and second electrode layer 310 formed on selector 308. Pillar-shaped memory cell 301 further includes PCM element 312 having a shape of narrow top and wide bottom formed on second electrode layer 310, a third electrode layer (e.g., 314 in FIG. 3) formed on PCM element 312, and an insulation layer 309 formed between third electrode layer (e.g., 314 in FIG. 3) and PCM element 312. PCM element 312 includes a top surface 3123, a bottom surface 3127, a slope 3121 connected to top surface 3123, and a side surface 3125 connected between slope 3121 and bottom surface 3127.

In some implementations, a width of top surface 3123 is smaller than a width of bottom surface 3127 in a cross-sectional view such that PCM element 312 having a shape of narrow top and wide bottom. In some implementations, an area of top surface 3123 is smaller than that of bottom surface 3127. By reducing the contact interface between PCM element 312 and third electrode layer 314, it increases the current density across the contact interface and thus reduces the overall energy consumption of pillar-shaped memory cell 301. Furthermore, since the contact interface is significantly reduced, the heat dissipation from PCM element 312 to third electrode layer 314 is also reduced, thereby transferring the heating zone from the contact interface to the center of PCM element 312. This also increases the efficiency of heating PCM element 312. In some implementations, top surface 3123 includes a flat top surface and thus provides better electrical contact with third electrode layer 314. In some implementations, to prevent from over-etching to form a leakage path within PCM element 312 or over-etching second electrode layer 310 in the processing of PCM element 312 (which will be discussed later) , a side surface 3125 connected between slope 3121 and bottom surface 3127 is needed. In some implementations, side surface 3125 may also be a vertical side surface forming when processing to separate pillar-shaped memory cells 301.

Insulation layer 309 is formed on slope 3121 and co-planer with top surface 3123. In some implementations, insulation layer 309 can also cover a portion of top surface 3123. In some implementations, insulation layer 309 is embedded among isolation layer 322, PCM element 312, and third electrode layer 314, as shown in FIG. 3. Insulation layer 309 is also used to reduce the heat dissipation of the contact interface, which increases the efficiency of heating PCM element 312 and therefore reduces the energy consumption of pillar-shaped memory cell 301.

FIG. 4B illustrates a 3D schematic of an exemplary 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure. As mentioned above, slope 3121 may include an arc shape. The shape of slope 3121 may be determined according to the type of etching process. For instance, when applying a wet etching over PCM element 312, the arc shape of slope 3121 can be formed.

FIG. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells, according to some implementations of the present disclosure. As shown in FIG. 5, an array of PCM cells 502 (e.g., corresponding to pillar-shaped memory cells 301 in FIG. 3) can be formed as the intersections (cross-points) of word lines 504 (e.g., corresponding to word lines 316 in FIG. 3) and bit lines 506 (e.g., corresponding to bit lines 304 in FIG. 3) , respectively. Each PCM cell 502 can include a PCM element 508 (e.g., corresponding to PCM element 312 in FIG. 3) in series with a selector (e.g., corresponding to selector 308 in FIG. 3) . To operate the array of PCM cells 502, a word line voltage (Vw) having a value of either 0 or Vhh can be applied to each word line 504, and a bit line voltage (Vb) having a value of either 0 or Vll can be applied to each bit line 506. The voltage (Va) applied to each PCM cell 502 (and selector 510 thereof) can thus be either Vhh, –Vll, 0, or Vhh–Vll. In some implementations, Vhh and Vll are set based on the intrinsic threshold voltage (Vth) of selector 510, such that |Vhh–Vll| ≥ Vth >|Vhhl|, |Vll|, or 0. As shown in FIG. 5, the voltage (Va) is equal to or greater than the threshold voltage (Vth) at only one intersection of word line 504 and bit line 506 with non-zero voltages, according to some implementations. Thus, only PCM cell 502 (in the dotted circle in FIG. 5) at the intersection of the pair of word line 504 and bit line 506 with non-zero voltages can be selected (i.e., (applied with a voltage of Vhh–Vll and in the on-state) . Other PCM cells 502 are not selected and are in the off-state, according to some implementations.

FIGs. 6A-6J illustrate an exemplary fabrication process for forming a 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some aspects of the present disclosure. FIG. 7 illustrates a flowchart of an exemplary method 700 for forming a 3D PCM device with a PCM element having a shape of narrow top and wide bottom, according to some implementations of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 6A–6J and 7 include memory device 300 depicted in FIG. 3. Examples of the memory cell depicted in FIGs. 6A–6J and 7 include pillar-shaped memory cell 301 depicted in FIGs. 3 and 4A-4B. Examples of PCM elements having a shape of narrow top and wide bottom depicted in FIGs. 6A–6J and 7 include PCM element 312 depicted in FIGs. 3 and 4A-4B. FIGs. 6A–6J and 7 will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.

Referring to FIG. 7, method 700 starts at operation 702, in which a bit line, a first electrode layer, a selector, a second electrode layer, and a PCM element are deposited above a substrate sequentially. That is, the bit line is deposited on the substrate, the first electrode layer is deposited on the bit line, the selector is deposited on the first electrode layer, the second electrode layer is deposited on the selector, and the PCM element is deposited on the second electrode layer. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6A, a bit line 604 (e.g., corresponding to bit line 304 in FIG. 3) is formed on a substrate 602 (e.g., corresponding to substrate 302 in FIG. 3) , a first electrode layer 606 (e.g., corresponding to first electrode layer 306 in FIG. 3) is formed on bit line 604, a selector 608 (e.g., corresponding to selector 308 in FIG. 3) is formed on first electrode layer 606, a second electrode layer 610 (e.g., corresponding to second electrode layer 310 in FIG. 3) is formed on selector 608, and PCM element 612 (e.g., corresponding to PCM element 312 in FIG. 3) is formed on second electrode layer 610. In some implementations, bit line 604 may include W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, first electrode layer 606 may include W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, first electrode layer 606 includes carbon, such as amorphous carbon (a-C) .

Method 700 proceeds to operation 704, as illustrated in FIG. 7, in which a mask is deposited on a portion of the PCM element. In particular, the mask includes a photoresist. A pattern of the mask is produced by applying the photoresist to the surface of the PCM element to be etched, exposing the photoresist to form one or more openings, and then developing the pattern into the photoresist using a resist developer.

Referring to FIG. 6B, a mask 621 is formed on PCM element 612. Mask 621 includes a photoresist. The photoresists are organic compositions consisting of light-sensitive polymers or polymer precursors dissolved in one or more organic solvents. A pattern of mask 621 is produced by applying the photoresist to the top surface of PCM element 612 to be etched, and after lithography, etching to form one or more openings 6211. In some implementations, mask 621 can also include an oxide material, for instance, a SiO ₂ layer.

Method 700 proceeds to operation 706, as illustrated in FIG. 7, in which the PCM element is etched via an opening of the mask to form a recess in the PCM element. In some implementations, the etching of the PCM element may include using one or more etching processes including, but not limited to, wet etching, dry etching, any other suitable etching process, or any combination thereof. In some implementations, the etching process can form a pyramid-shaped hole (or recess) instead of a hole with rounded sidewalls. This is because the PCM element exhibits anisotropic etching in certain chemicals instead of isotropic etching during a wet etching process.

Referring to FIG. 6C, an etching process, for instance, a wet etching process, is applied via one or more openings 6211 (e.g., in FIG. 6B) of mask 621 to form one or more recesses 625 in PCM element 612. In some implementations, recess 625 includes a pyramid shape extending through PCM element 612. The depth of the etching may be 5 to 30 nm, for example, 10 to 20 nm.

Method 700 proceeds to operation 708, as illustrated in FIG. 7, in which the mask is removed, and a sacrificial insulation layer is formed on the PCM element and the recess. The removal of the mask includes employing an organic or non-organic solvent that attacks and removes the photoresist material. The deposition of the sacrificial insulation layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6D, mask 621 is removed by employing an organic or non-organic solvent over mask 621 to dissolve and remove mask 621 on PCM element 612. After the removal, a top surface 6123 and a slope 6121 of PCM element 612 are exposed. Slope 6121 is also a part of recess 625. In some implementations, a bottom surface (not shown) of recess 625 connected to slope 6121 can also be formed.

After that, referring to FIG. 6E, a sacrificial insulation layer 6091 is formed on PCM element 612 and recess 625. In particular, sacrificial insulation layer 6091 is formed on slope 6121 and top surface 6123 of PCM element 612. In some implementations, sacrificial insulation layer 6091 includes at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) .

Method 700 proceeds to operation 710, as illustrated in FIG. 7, in which the sacrificial insulation layer is etched to form an insulation layer in the recess. In particular, the sacrificial insulation layer on the top surface of the PCM element is etched away, and an insulation layer is reserved and formed in the recess. In some implementations, the etching process of the sacrificial insulation layer may include wet etching, or drying etching.

Referring to FIG. 6F, sacrificial insulation layer (e.g., 6091 in FIG. 6E) is etched to form an insulation layer 609 in recess 625. In particular, insulation layer 609 is filled in recess 625 and also on slope 6121 of PCM element 612. In some implementations, insulation layer 609 may also cover a portion of top surface 6123 of PCM element 612 while expose most of top surface 6123 to be in contact with the third electrode layer. In some implementations, the portion of insulation layer 609 covering the portion of top surface 6123 of PCM element 612 may be removed. In some implementations, the etching of sacrificial insulation layer may include chemical mechanical planarization (CMP) to remove insulation layer 609 covering the portion of top surface 6123 of PCM element 612.

Method 700 proceeds to operation 712, as illustrated in FIG. 7, in which the third electrode layer is formed on the PCM element and the insulation layer. That is, the third electrode layer is deposited and covers the top surface of the PCM element and also the insulation layer in the recess. The deposition of the third electrode layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6G, third electrode layer 614 is formed on PCM element 612 and insulation layer 609. In particular, third electrode layer 614 is deposited and covers top surface 6123 of PCM element 612 and also insulation layer 609 in recess 625.

Method 700 proceeds to operation 714, as illustrated in FIG. 7, in which a trench is formed by an etching process to expose a top surface of the substrate. In particular, the trench is etched through the third electrode layer, the insulation layer, the PCM element, the second electrode layer, the selector, the first electrode layer, and the bit line, to expose the top surface of the substrate. In some implementations, the etching process of the trench may include drying etching, such as reactive-ion etching (RIE) .

Referring to FIG. 6H, one or more trenches 603 are formed by an etching process to expose a top surface 6021 of substrate 602. In particular, trench 603 is etched through third electrode layer 614, insulation layer 609, PCM element 612, second electrode layer 610, selector 608, first electrode layer 606, and bit line 604, to expose top surface 6021 of substrate 602. These trenches 603 are used to divide the memory device (e.g., memory device 300 in FIG. 3) to form a plurality of separated memory cells (e.g., pillar-shaped memory cell 301 in FIG. 3) .

Method 700 proceeds to operation 716, as illustrated in FIG. 7, in which an isolation layer is formed on a sidewall of the trench and the top surface of the substrate. This can be done by depositing a sacrificial isolation layer over the third electrode, the sidewall of the trench, and the top surface of the substrate. And then, the part of the sacrificial isolation layer on the third electrode is etched away, leaving the isolation layer on the sidewall of the trench and the top surface of the substrate. The deposition of the isolation layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6I, an isolation layer 622 (e.g., corresponding to 322 in FIG. 3) is formed on a sidewall of trench 603 and top surface 6021 of substrate 602. In some implementations, trench 603 may be filled up with isolation layer 622 or only covered up the sidewall of the trench and leave some spaces within.

Method 700 proceeds to operation 718, as illustrated in FIG. 7, in which a word line is formed on the third electrode. The deposition of the word line may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6J, a word line 616 (e.g., corresponding to 316 in FIG. 3) is formed on third electrode layer 614. And the memory device (e.g., memory device 300 in FIG. 3) is formed.

According to one aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each one of the plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each one of the plurality of memory cells includes stacked a phase-change memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. An area of the top surface is smaller than that of the bottom surface.

In some implementations, the PCM element further includes a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.

In some implementations, the slope includes an arc shape.

In some implementations, the side surface is perpendicular to the bottom surface of the PCM element.

In some implementations, the memory device further includes an insulation layer formed on the slope and co-planer with the top surface of the PCM element.

In some implementations, a material of the insulation layer includes at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) .

In some implementations, a thickness of the insulation layer is between 10 nm and 20 nm.

In some implementations, each one of the plurality of memory cells further includes a first electrode formed between the selector and the respective bit line, a second electrode formed between the PCM element and the selector, and a third electrode formed between the respective word line and the PCM element.

In some implementations, the PCM element includes a pyramid shape.

In some implementations, a thickness of the PCM element is between 30 nm and 50 nm.

In some implementations, the PCM element includes a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .

According to another aspect of the present disclosure, a phase-change memory (PCM) cell includes a PCM element and a selector. The PCM element includes a top surface and a bottom surface. An area of the top surface is smaller than that of the bottom surface.

In some implementations, the slope includes an arc shape.

In some implementations, the PCM cell further includes an insulation layer formed on the slope and co-planer with the top surface of the PCM element.

In some implementations, the PCM element includes a pyramid shape.

According to still another aspect of the present disclosure, a method for forming a memory device includes sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a phase-change memory (PCM) element on a substrate, depositing a mask on the PCM element, etching the PCM element via an opening of the mask to form a recess in the PCM element, removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess, etching the sacrificial insulation layer to form an insulation layer in the recess, depositing a third electrode on the PCM element and the insulation layer, and depositing a word line on the third electrode.

In some implementations, the mask includes a photoresist.

In some implementations, the etching of the PCM element includes wet etching.

In some implementations, the recess includes a pyramid shape.

In some implementations, the etching of the sacrificial insulation layer to form the insulation layer includes etching the sacrificial insulation layer on a top surface of the PCM element.

In some implementations, the method further includes etching through the third electrode, the PCM element, the second electrode, the selector, the first electrode, and the bit line to form a trench and exposing a top surface of the substrate, and depositing an isolation layer on a sidewall of the trench and the top surface of the substrate.

In some implementations, the etching to form the trench includes a dry etching.

According to yet another aspect of the present disclosure, a method for forming a phase-change memory (PCM) cell includes sequentially depositing a first electrode, a selector, a second electrode, and a PCM element, depositing a mask on the PCM element, etching the PCM element via an opening of the mask to form a recess in the PCM element, removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess, etching the sacrificial insulation layer to form an insulation layer in the recess, and depositing a third electrode on the PCM element and the insulation layer.

In some implementations, the mask includes a photoresist.

In some implementations, the etching of the PCM element includes wet etching.

In some implementations, the recess includes a pyramid shape.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary implementations of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises stacked a phase-change memory (PCM) element and a selector, and the PCM element comprises:

a top surface, and a bottom surface, an area of the top surface being smaller than that of the bottom surface.
The memory device of claim 1, wherein the PCM element further comprises a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.
The memory device of claim 2, wherein the slope includes an arc shape.
The memory device of claim 2 or 3, wherein the side surface is perpendicular to the bottom surface of the PCM element.
The memory device of any one of claims 1-4, further comprising:

an insulation layer formed on the slope and co-planer with the top surface of the PCM element.
The memory device of claim 5, wherein a material of the insulation layer comprises at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) .
The memory device of claim 5 or 6, wherein a thickness of the insulation layer is between 10 nm and 20 nm.
The memory device of any one of claims 1-7, wherein each of the plurality of memory cells further comprises:

a first electrode formed between the selector and the respective bit line;

a second electrode formed between the PCM element and the selector; and

a third electrode formed between the respective word line and the PCM element.
The memory device of any one of claims 1-8, wherein the PCM element comprises a pyramid shape.
The memory device of any one of claims 1-9, wherein a thickness of the PCM element is between 30 nm and 50 nm.
The memory device of any one of claims 1-10, wherein the PCM element comprises a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
A phase-change memory (PCM) cell, comprising:

a PCM element; and

a selector, wherein the PCM element comprises:

a top surface, and a bottom surface, an area of the top surface being smaller than that of the bottom surface.
The PCM cell of claim 12, wherein the PCM element further comprises a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.
The PCM cell of claim 12 or 13, wherein the slope includes an arc shape.
The PCM cell of any one of claims 12-14, wherein the side surface is perpendicular to the bottom surface of the PCM element.
The PCM cell of any one of claims 12-15, further comprising:

an insulation layer formed on the slope and co-planer with the top surface of the PCM element.
The PCM cell of claim 16, wherein a material of the insulation layer comprises at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) .
The PCM cell of claim 16 or 17, wherein a thickness of the insulation layer is between 10 nm and 20 nm.
The PCM cell of any one of claims 12-18, further comprising:

a first electrode formed below the selector;

a second electrode formed between the PCM element and the selector; and

a third electrode formed on the PCM element.
The PCM cell of any one of claims 12-19, wherein the PCM element comprises a pyramid shape.
The PCM cell of any one of claims 12-20, wherein a thickness of the PCM element is between 30 nm and 50 nm.
The PCM cell of any one of claims 12-21, wherein the PCM element comprises a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
A method for forming a memory device, comprising:

sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a phase-change memory (PCM) element on a substrate;

depositing a mask on the PCM element;

etching the PCM element via an opening of the mask to form a recess in the PCM element;

removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess;

etching the sacrificial insulation layer to form an insulation layer in the recess;

depositing a third electrode on the PCM element and the insulation layer; and

depositing a word line on the third electrode.
The method of claim 23, wherein the mask comprises a photoresist.
The method of claim 23 or 24, wherein the etching of the PCM element comprises wet etching.
The method of any one of claims 23-25, wherein the recess comprises a pyramid shape.
The method of any one of claims 23-26, wherein etching the sacrificial insulation layer to form the insulation layer comprises etching the sacrificial insulation layer on a top surface of the PCM element.
The method of any one of claims 23-27, further comprising:

etching through the third electrode, the PCM element, the second electrode, the selector, the first electrode, and the bit line to form a trench and exposing a top surface of the substrate; and

depositing an isolation layer on a sidewall of the trench and the top surface of the substrate.
The method of claim 28, wherein the etching to form the trench comprising a dry etching.
A method for forming a phase-change memory (PCM) cell, comprising:

sequentially depositing a first electrode, a selector, a second electrode, and a PCM element;

depositing a mask on the PCM element;

etching the PCM element via an opening of the mask to form a recess in the PCM element;

removing the mask and depositing a sacrificial insulation layer on the PCM element and the recess;

etching the sacrificial insulation layer to form an insulation layer in the recess; and

depositing a third electrode on the PCM element and the insulation layer.
The method of claim 30, wherein the mask comprises a photoresist.
The method of claim 30 or 31, wherein the etching of the PCM element comprises wet etching.
The method of any one of claims 30-32, wherein the recess comprises a pyramid shape.
The method of any one of claims 30-33, wherein etching the sacrificial insulation layer to form the insulation layer comprises etching the sacrificial insulation layer on a top surface of the PCM element.