CN114784109B - Planar gate SiC MOSFET and manufacturing method thereof - Google Patents
Planar gate SiC MOSFET and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a planar gate SiC MOSFET and a manufacturing method thereof. The invention adopts the injection mode that the P injection region and the N injection region are spaced in the y direction of the SiC MOSFET, which is beneficial to reducing the cell size and the chip cost while ensuring good contact. The high concentration of the N + implant region ensures good ohmic contact and the low concentration of the N-implant region introduces a ballast resistor in the source region which helps to reduce the current density at high voltage. Meanwhile, the N-injection region with low concentration and the P+ injection regions with high concentration at two sides form a JFET structure, and when the JFET structure is conducted in the forward direction, the depletion region is narrower in width due to lower voltage, so that the influence on current circulation is avoided. When short circuit occurs, the power voltage directly acts on the two ends of the source and drain of the SiC MOSFET, so that the potential of the P+ injection region is very high, the width of the depletion region is wider, the JFET region is pinched off, the saturation current density is greatly reduced, and the short circuit robustness of the device is improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a planar gate SiC MOSFET and a manufacturing method thereof.
Background
The advent of electrical energy has prompted the rapid development of modern social science and technology, and how to more efficiently process electrical energy has long been a popular topic of worldwide scientific research. Efficient use of electrical energy is highly dependent on the power electronics system, and the core electronics of the various power electronics systems are semiconductor power devices. The semiconductor power device is widely applied to the fields of various household appliances, various industrial equipment mainly based on electric power and the like. After entering the 21 st century, the global warming problem is focused by more and more people, and the energy conservation, emission reduction and energy utilization efficiency improvement are more important. Today, the proportion of clean renewable energy sources is larger and larger, the whole society has higher expectations on energy conversion efficiency, and higher requirements are put on the performance of power semiconductor devices of an energy control core.
Conventional power semiconductor devices are mainly silicon-based devices, and the device types include thyristors, schottky barrier diodes (JBS), power Bipolar Junction Transistors (BJTs), power insulated gate field effect transistors (MOSFETs), and power Insulated Gate Bipolar Transistors (IGBTs). Currently, silicon-based power semiconductor devices have taken up the dominant market for power semiconductor devices. However, the performance of the conventional silicon-based power device is approaching to the theoretical limit of silicon materials, and it is difficult to greatly improve the performance of the device through structural design and optimization.
Based on the development of silicon carbide (SiC) power semiconductor devices and SiC semiconductor technology, the demand for more efficient electrical energy applications is further met. SiC has very excellent physical, chemical and electrical properties as a typical representative of third generation semiconductor materials, with a larger forbidden band width, higher electron saturation velocity, higher thermal conductivity and 10 times the critical breakdown field of silicon materials than silicon materials. These excellent material characteristics make SiC power semiconductor devices have great advantages in terms of reducing power consumption of the power system, improving efficiency, and the like. In addition, the SiC material is one of the most mature wide bandgap semiconductor materials in the current crystal growth technology and device manufacturing technology, is beneficial to realizing the industrial production of silicon carbide-based power devices, and improves the market share of the SiC-based power devices.
In recent years, siC MOSFETs have been successfully commercialized and exhibit excellent performance, and in some applications, the performance of SiC MOSFETs has been comparable to or even superior to Si-based IGBTs, but there is still room for optimization in some key parameters, not only to further improve the electrical characteristics of the device such as on-resistance and switching loss, but also to further improve the reliability of the MOSFETs, thereby further promoting the application of SiC MOSFETs in high voltage fields. Due to the characteristics of materials, the SiC MOSFET can realize high withstand voltage and simultaneously maintain high doping concentration, so that the on-resistance of the device is reduced, but the high doping concentration also causes the SiC MOSFET to have high saturation current. When the device works in an actual application circuit, if the system is abnormal at a certain moment to directly bear the power supply voltage, namely short circuit occurs, the power supply voltage is fully loaded at two ends of the device, and high voltage and high saturation current of the SiC MOSFET can cause large power loss when the device is short-circuited, so that a large amount of heat is generated in a short time, and the device is damaged. The shorter short-circuit withstand time reduces the reliability of the device, limiting the range of applications for SiC MOSFETs. Designing a new SiC MOSFET structure to reduce the saturation current of the device or to design a protection circuit to turn off the short-circuit device in time is an important way to improve the short-circuit reliability of the device, but the new device structure puts new requirements on the process, which is not beneficial to control the production cost, and adopting the short-circuit protection circuit also increases additional design cost. Accordingly, a new device structure is needed to reduce the saturation current of the device to enhance the short circuit endurance of the device.
Disclosure of Invention
The invention aims to solve the technical problems existing in the prior art and provides a planar gate SiC MOSFET and a manufacturing method thereof.
In order to solve the technical problems, the embodiment of the invention provides a planar gate SiC MOSFET, in which three-dimensional directions of devices are defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, namely the third dimension, wherein the half cell structure comprises: a back drain metal 11, an N+ type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 3 is arranged on one side of the top layer of the N-drift region 2, an N-source region 4 and a P+ source region 6 with side surfaces in contact with each other are arranged on one side of the top layer of the P-type base region 3, and the P+ source region 6 is arranged close to the side surfaces of the N-drift region 2; along the Y-axis direction, the top layer of the N-drift region 2 is provided with a P-type base region 3, the top layer of the P-type base region 3 is provided with P+ source regions 6 distributed at intervals, and N+ source regions 5 are arranged between the P+ source regions 6;
a gate structure is arranged on the N-drift region 2, the P-type base region 3 and a part of the N-source region 4 along the Z axis direction, a source metal 10 is arranged on the N+ source region 5 between a part of the P+ source region 6 and the P+ source region 6 distributed along the Y axis direction, and a dielectric layer 9 is arranged between the source metal 10 and the gate structure;
the source metal 10 forms ohmic contacts with the n+ source region 5 and the p+ source region 6 along the Y-axis direction.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the doping concentration of the P-type base region 3 below the N-source region 4 and the n+ source region 5 is higher than that of other regions of the P-type base region 3.
Further, the junction depth of the p+ source region 6 is the same as the junction depth of the P-type base region 3.
In order to solve the technical problems, the embodiment of the invention provides a planar gate SiC MOSFET, in which three-dimensional directions of devices are defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, namely the third dimension, wherein the half cell structure comprises: a back drain metal 11, an N+ type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 3 is arranged on one side of the top layer of the N-drift region 2, an N-source region 4 and an N+ source region 5 with side surfaces in contact are arranged on one side of the top layer of the P-type base region 3, a first P+ source region 6-1 is arranged in the N-source region 4, the N-source region 4 is arranged on two sides of the first P+ source region 6-1, and the N+ source region 5 is arranged close to the side surfaces of the N-drift region 2; along the Y-axis direction, the top layer of the N-drift region 2 is provided with a P-type base region 3, the top layer of the P-type base region 3 is provided with first P+ source regions 6-1 distributed at intervals and N+ source regions 5 distributed at intervals, N-source regions 4 are arranged between the first P+ source regions 6-1, and a second P+ source region 6-2 is arranged between the N+ source regions 5;
along the Z-axis direction, gate structures are arranged on the N-drift region 2, the P-type base region 3 and part of the N-source region 4, source metal 10 is arranged on the N+ source region 5 and the second P+ source region 6-2, and a dielectric layer 9 is arranged between the source metal 10 and the gate structures;
the source metal 10 forms ohmic contacts with the n+ source region 5 and the second p+ source region 6-2 in the Y-axis direction.
Further, the junction depth of the first p+ source region 6-1 and the second p+ source region 6-2 is the same as the junction depth of the P-type base region 3.
Further, the gate structure comprises a gate oxide layer 7 and a gate electrode 8 which are sequentially stacked from bottom to top.
Further, the gate electrode 8 is a metal gate electrode or a polysilicon gate electrode.
Further, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Further, the source metal 10 is titanium, nickel, copper or aluminum.
In order to solve the technical problems, an embodiment of the present invention provides a method for manufacturing a planar gate SiC MOSFET, including the following steps:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N+ type substrate layer 1 of the device;
step 2: forming an N-drift region 2 on an N-type heavily doped monocrystalline silicon carbide wafer by adopting an epitaxial process;
step 3: forming a P-type base region 3 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N-source region 4 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 5: forming an N+ source region 5 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a P+ source region 6 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 7: forming a gate oxide layer 7 through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer 7 to serve as a gate electrode 8;
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer 9 to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal to serve as source metal 10;
step 9: the device is flipped over and a layer of metal is sputtered on the back as drain metal 11.
In order to solve the technical problems, an embodiment of the present invention provides a method for manufacturing a planar gate SiC MOSFET, including the following steps:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N+ type substrate layer 1 of the device;
step 2: forming an N-drift region 2 on an N-type heavily doped monocrystalline silicon carbide wafer by adopting an epitaxial process;
step 3: forming a P-type base region 3 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N-source region 4 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 5: forming an N+ source region 5 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a first P+ source region 6-1 and a second P+ source region 6-2 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 7: forming a gate oxide layer 7 through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer 7 to serve as a gate electrode 8;
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer 9 to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal to serve as source metal 10;
step 9: the device is flipped over and a layer of metal is sputtered on the back as drain metal 11.
The working principle of the invention is as follows: when the SiC MOSFET is operating normally, the drain is at a high potential, the source is at a low potential, and electron current from the N-source region 4 and the n+ source region 5 flows through the channel to the JFET region and spreads in the N-drift region 2, with current flowing from the drain to the source. At this time, the potential of the p+ source region 6 is higher than that of the N-source region 4, and the depletion region mainly expands toward the N-source region 4 due to a large concentration difference, but when the SiC MOSFET is normally operated, the potential difference between the source and drain is small, the depletion region is narrow, and the current flow is less affected.
When the circuit is short-circuited, the power supply voltage is fully loaded on two ends of the device, so that the SiC MOSFET is in a high-voltage and high-current state, and a large amount of heat is generated in a short time, so that the SiC MOSFET is damaged. In the invention, the N-source region 4 is introduced into the source region, and after current flows through the channel, the current can enter the source electrode through the N-source region 4 doped with low concentration, and the existence of the N-source region 4 is equivalent to the introduction of a ballast resistor which is beneficial to limiting the current density of the SiC MOSFET under the condition of short circuit. Meanwhile, a JFET structure is introduced at the contact position of the source region, when the SiC MOSFET is in a short circuit state, the potential difference between the P+ source region 6 and the N-source region 4 is very large, and the concentration difference between the P+ source region and the N-source region 4 is very large, so that the N-source region 4 is pinched off by the depletion region, and the saturation current of the SiC MOSFET is limited. The current flowing through the SiC MOSFET under the condition of short circuit is reduced by introducing the ballast resistor and the JFET structure, so that the power of the SiC MOSFET during short circuit is reduced, the heat generated by the SiC MOSFET in unit time is reduced, and the short circuit robustness of the SiC MOSFET is improved.
The beneficial effects of the invention are as follows: according to the invention, the ballast resistor and the JFET structure are introduced into the active region of the SiC MOSFET, and the introduced ballast resistor and JFET structure can effectively limit the current density of the SiC MOSFET in the short circuit process, so that when the SiC MOSFET is in the short circuit, the smaller current density reduces the power of the SiC MOSFET, reduces the heat generated in the unit time of the SiC MOSFET, and further effectively improves the short circuit robustness of the SiC MOSFET. When the SiC MOSFET works normally, the depletion region is narrower in width due to lower voltage, and the introduced JFET structure does not have great influence on current circulation. Meanwhile, the active region of the SiC MOSFET adopts an injection mode that the N injection region is separated from the P injection region to introduce the JFET region, so that the area of the active region is not required to be additionally increased, the area of the active region can be effectively reduced on the premise of ensuring that good ohmic contact is formed, and the cost of a chip is reduced. Moreover, the scheme of the invention can be used for adopting the traditional SiC MOSFET process without complicating the manufacturing process.
Drawings
Fig. 1 is a schematic diagram of a half cell structure of a conventional planar gate SiC MOSFET;
fig. 2 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET according to a third embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a planar gate SiC MOSFET according to a third embodiment of the present invention, taken along section line AA';
fig. 6 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET according to a fourth embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of a planar gate SiC MOSFET according to a fourth embodiment of the invention, taken along section line AA';
fig. 8-16 are schematic process flow diagrams of a method for manufacturing a planar gate SiC MOSFET according to a fifth embodiment of the present invention.
In the drawings, the list of components represented by the various numbers is as follows:
1. the semiconductor device comprises an N+ type substrate layer, 2, an N-drift region, 3, a P type base region, 4, an N-source region, 5, an N+ source region, 6, a P+ source region, 6-1, a first P+ source region, 6-2, a second P+ source region, 7, a gate oxide layer, 8, a gate electrode, 9, a dielectric layer, 10, source metal, 11 and back drain metal.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in fig. 2, in the planar gate SiC MOSFET provided in the first embodiment of the present invention, three dimensions of the device are defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, namely the third dimension, wherein the half cell structure comprises: a back drain metal 11, an N+ type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 3 is arranged on one side of the top layer of the N-drift region 2, an N-source region 4 and a P+ source region 6 with side surfaces in contact with each other are arranged on one side of the top layer of the P-type base region 3, and the P+ source region 6 is arranged close to the side surfaces of the N-drift region 2; along the Y-axis direction, the top layer of the N-drift region 2 is provided with a P-type base region 3, the top layer of the P-type base region 3 is provided with P+ source regions 6 distributed at intervals, and N+ source regions 5 are arranged between the P+ source regions 6;
a gate structure is arranged on the N-drift region 2, the P-type base region 3 and a part of the N-source region 4 along the Z axis direction, a source metal 10 is arranged on the N+ source region 5 between a part of the P+ source region 6 and the P+ source region 6 distributed along the Y axis direction, and a dielectric layer 9 is arranged between the source metal 10 and the gate structure;
the source metal 10 forms ohmic contacts with the n+ source region 5 and the p+ source region 6 along the Y-axis direction. In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Optionally, the doping concentration of the P-type base region 3 below the N-source region 4 and the n+ source region 5 is higher than the doping concentration of other regions of the P-type base region 3.
As shown in fig. 3, a planar gate SiC MOSFET according to a second embodiment of the present invention is based on the first embodiment, where the junction depth of the p+ source region 6 is the same as the junction depth of the P-type base region 3.
As shown in fig. 4 to 5, in the planar gate SiC MOSFET according to the third embodiment of the present invention, a three-dimensional direction of a device is defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, namely the third dimension, wherein the half cell structure comprises: a back drain metal 11, an N+ type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 3 is arranged on one side of the top layer of the N-drift region 2, an N-source region 4 and an N+ source region 5 with side surfaces in contact are arranged on one side of the top layer of the P-type base region 3, a first P+ source region 6-1 is arranged in the N-source region 4, the N-source region 4 is arranged on two sides of the first P+ source region 6-1, and the N+ source region 5 is arranged close to the side surfaces of the N-drift region 2; along the Y-axis direction, the top layer of the N-drift region 2 is provided with a P-type base region 3, the top layer of the P-type base region 3 is provided with first P+ source regions 6-1 distributed at intervals and N+ source regions 5 distributed at intervals, N-source regions 4 are arranged between the first P+ source regions 6-1, and a second P+ source region 6-2 is arranged between the N+ source regions 5;
along the Z-axis direction, gate structures are arranged on the N-drift region 2, the P-type base region 3 and part of the N-source region 4, source metal 10 is arranged on the N+ source region 5 and the second P+ source region 6-2, and a dielectric layer 9 is arranged between the source metal 10 and the gate structures;
the source metal 10 forms ohmic contacts with the n+ source region 5 and the second p+ source region 6-2 in the Y-axis direction.
The embodiment introduces the JFET region through the alternate distribution of the P+ source region 6 and the N-source region 4 in the x direction and the y direction at the same time, so that the saturation current of the SiC MOSFET can be effectively reduced, and the short circuit robustness of the SiC MOSFET is improved.
As shown in fig. 6 to 7, a planar gate SiC MOSFET according to a fourth embodiment of the present invention is based on the third embodiment, so that the junction depth of the first p+ source region 6-1 and the second p+ source region 6-2 is the same as the junction depth of the P-type base region 3.
Alternatively, the gate structure includes a gate oxide layer 7 and a gate electrode 8 which are sequentially stacked from bottom to top.
Alternatively, the gate electrode 8 is a metal gate electrode or a polysilicon gate electrode.
Alternatively, the source metal 10 may be titanium, nickel, copper or aluminum.
As shown in fig. 8-16, a fifth embodiment of the present invention provides a method for manufacturing a planar gate SiC MOSFET, including the steps of:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer with a certain thickness is selected as an N+ type substrate layer 1 of the device;
step 2: forming an N-drift region 2 on an N-type heavily doped monocrystalline silicon carbide wafer with a certain thickness through an epitaxial process;
step 3: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 4: an ion implantation window of the P-type base region 3 is formed through a photoetching process, and the P-type base region 3 is formed through multiple times of ion implantation of P-type impurities under certain target temperature and different energy and dosage, as shown in fig. 8;
step 5: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 6: an ion implantation window of the N-source region 4 is formed through a photoetching process, and N-type impurities are implanted for a plurality of times to form the N-source region 4 under certain target temperature and different energy and dosage, as shown in fig. 9;
step 7: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 8: an ion implantation window of the N+ source region 5 is formed through a photoetching process, and N-type impurities are implanted for a plurality of times to form the N+ source region 5 under certain target temperature and different energy and dosage, as shown in fig. 10;
step 9: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 10: an ion implantation window of the P+ source region 6 is formed through a photoetching process, and P-type impurities are implanted for a plurality of times to form the P+ source region 6 at a certain target temperature and different energy and dosage, as shown in FIG. 11;
step 11: sputtering a carbon film on the surface of the wafer, and carrying out high-temperature annealing on the wafer under certain conditions;
step 12: forming a gate oxide layer 7 by an oxidation process at a high temperature, and depositing a layer of polycrystal as a gate electrode 8 on the gate oxide layer, as shown in fig. 12;
step 13: etching part of the polycrystal and the gate oxide layer by an etching process to form a split gate structure, as shown in fig. 13, and depositing a dielectric layer 9 to cover the polycrystal, as shown in fig. 14;
step 14: forming a source metal hole on the front surface of the wafer through a photoetching process, and sputtering a layer of metal as source metal 10, as shown in fig. 15;
step 15: the wafer is turned over and a layer of metal is sputtered on the back as drain metal 11, as shown in fig. 16.
As shown in fig. 4-5, a sixth embodiment of the present invention provides a method for manufacturing a planar gate SiC MOSFET, which includes steps 1-5, 7, 9, 11-15, which are the same as those of embodiment 5, and different steps are:
step 6: an ion implantation window of the N-source region 4 is formed through photoetching technology, N-type impurities are implanted for a plurality of times under certain target temperature and different energy and dosage to form the N-source region 4, and the implantation region is shown in figure 5;
step 8: an ion implantation window of the N+ source region 5 is formed through photoetching technology, N-type impurities are implanted for a plurality of times to form the N+ source region 5 under certain target temperature and different energy and dosage, and the implantation region is shown in figure 5;
step 10: ion implantation windows of a first P+ source region 6-1 and a second P+ source region 6-2 are formed through photoetching technology, and N-type impurities are implanted for a plurality of times under certain target temperature and different energy and dosage to form the first P+ source region 6-1 and the second P+ source region 6-2, wherein the implantation regions are shown in figure 5;
the invention adopts the injection mode that the P injection region is separated from the N injection region in the three-dimensional y direction of the SiC MOSFET, and the injection concentration of different N injection regions is different. The implantation mode of spacing the P implantation region and the N implantation region in the y direction can reduce the cell size and the chip cost on the basis of ensuring good source electrode contact. The high concentration of the N + implant region ensures good ohmic contact and the low concentration of the N-implant region introduces a ballast resistor in the source region which helps to reduce the current density at high voltage. Meanwhile, the low-concentration N-implantation region and the P+ implantation regions at the two sides form the JFET, and when the JFET region is conducted in the forward direction, the depletion region is narrower in width due to lower voltage, so that the current circulation cannot be influenced. When short circuit occurs, the power voltage directly acts on the two ends of the source and drain of the SiC MOSFET, so that the potential of the P injection region is very high, the width of the depletion region is wider, the JFET region is pinched off, the saturation current density is greatly reduced, and the short circuit robustness of the device is improved.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A planar gate SiC MOSFET defines the three-dimensional direction of a device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back drain metal (11), an N+ type substrate layer (1) and an N-drift region (2) are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region (3) is arranged on one side of the top layer of the N-drift region (2), an N-source region (4) and a P+ source region (6) with side surfaces in contact with each other are arranged on one side of the top layer of the P-type base region (3), and the P+ source region (6) is arranged close to the side surfaces of the N-drift region (2); along the Y-axis direction, the top layer of the N-drift region (2) is provided with a P-type base region (3), the top layer of the P-type base region (3) is provided with P+ source regions (6) distributed at intervals, and N+ source regions (5) are arranged between the P+ source regions (6);
along the Z-axis direction, a grid structure is arranged on the N-drift region (2), the P-type base region (3) and part of the N-source region (4), source metal (10) is arranged on the N+ source region (5) between part of the P+ source region (6) and the P+ source region (6) distributed along the Y-axis direction, and a dielectric layer (9) is arranged between the source metal (10) and the grid structure;
and the source metal (10) forms ohmic contact with the N+ source region (5) and the P+ source region (6) along the Y-axis direction.
2. A planar gate SiC MOSFET according to claim 1, characterized in that the doping concentration of the P-type base region (3) below the N-source region (4) and n+ source region (5) is higher than the doping concentration of other regions of the P-type base region (3).
3. A planar gate SiC MOSFET according to claim 1, characterized in that the junction depth of said p+ source region (6) is the same as the junction depth of said P-type base region (3).
4. A planar gate SiC MOSFET defines the three-dimensional direction of a device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back drain metal (11), an N+ type substrate layer (1) and an N-drift region (2) are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region (3) is arranged on one side of the top layer of the N-drift region (2), an N-source region (4) and an N+ source region (5) which are in contact with each other on one side of the top layer of the P-type base region (3) are arranged on one side of the top layer, a first P+ source region (6-1) is arranged in the N-source region (4), the N-source region (4) is arranged on two sides of the first P+ source region (6-1), and the N+ source region (5) is arranged close to the side face of the N-drift region (2); along the Y-axis direction, the top layer of the N-drift region (2) is provided with a P-type base region (3), the top layer of the P-type base region (3) is provided with first P+ source regions (6-1) which are distributed at intervals and N+ source regions (5) which are distributed at intervals, N-source regions (4) are arranged between the first P+ source regions (6-1), and second P+ source regions (6-2) are arranged between the N+ source regions (5);
along the Z-axis direction, a grid structure is arranged on the N-drift region (2), the P-type base region (3) and part of the N-source region (4), source metal (10) is arranged on the N+ source region (5) and the second P+ source region (6-2), and a dielectric layer (9) is arranged between the source metal (10) and the grid structure;
and the source metal (10) forms ohmic contact with the N+ source region (5) and the second P+ source region (6-2) along the Y-axis direction.
5. A planar gate SiC MOSFET according to claim 4, characterized in that the junction depth of said first p+ source region (6-1) and said second p+ source region (6-2) is the same as the junction depth of said P-type base region (3).
6. A planar gate SiC MOSFET according to claim 1 or claim 4, characterized in that the gate structure comprises a gate oxide layer (7) and a gate electrode (8) arranged in sequence from bottom to top.
7. A planar gate SiC MOSFET according to claim 1 or claim 4, characterised in that the semiconductor material used in the device is any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
8. A planar gate SiC MOSFET according to claim 1 or claim 4, characterized in that the source metal (10) is titanium, nickel, copper or aluminum.
9. A method of fabricating a planar gate SiC MOSFET according to any one of claims 1-3,6-8, comprising the steps of:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N+ type substrate layer (1) of the device;
step 2: an epitaxial process is adopted to form an N-drift region (2) on the N-type heavily doped monocrystalline silicon carbide piece;
step 3: forming a P-type base region (3) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N-source region (4) by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 5: forming an N+ source region (5) by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a P+ source region (6) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 7: forming a gate oxide layer (7) through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer (7) to serve as a gate electrode (8);
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer (9) to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal as source metal (10);
step 9: the device is turned over and a layer of metal is sputtered on the back as drain metal (11).
10. A method of fabricating a planar gate SiC MOSFET according to any one of claims 4 to 8, comprising the steps of:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N+ type substrate layer (1) of the device;
step 2: an epitaxial process is adopted to form an N-drift region (2) on the N-type heavily doped monocrystalline silicon carbide piece;
step 3: forming a P-type base region (3) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N-source region (4) by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 5: forming an N+ source region (5) by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a first P+ source region (6-1) and a second P+ source region (6-2) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 7: forming a gate oxide layer (7) through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer (7) to serve as a gate electrode (8);
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer (9) to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal as source metal (10);
step 9: the device is turned over and a layer of metal is sputtered on the back as drain metal (11).
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