CN109065638B

CN109065638B - Power diode device

Info

Publication number: CN109065638B
Application number: CN201810961364.4A
Authority: CN
Inventors: 张金平; 邹华; 赵阳; 罗君轶; 刘竞秀; 李泽宏; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2018-08-22
Filing date: 2018-08-22
Publication date: 2021-02-12
Anticipated expiration: 2038-08-22
Also published as: CN109065638A

Abstract

A power diode device belongs to the field of semiconductor power devices. The cell structure comprises a cathode metal, an N + semiconductor substrate and an N-semiconductor drift region which are sequentially arranged from bottom to top, wherein groove structures are symmetrically arranged on two sides of the top layer of the N-semiconductor drift region, each groove structure comprises a P + semiconductor protective layer and polycrystalline silicon which are arranged from bottom to top, and an anode metal is arranged on the upper surface of the N-semiconductor drift region between each groove structure and the corresponding groove structure; the cathode metal forms ohmic contact with the N + semiconductor substrate, the anode metal forms ohmic contact with the polysilicon gate, the anode metal forms Schottky contact with the N-semiconductor drift region, and the polysilicon gate forms a heterojunction with the N-semiconductor drift region. The invention has the characteristics of high forward current density, high reverse voltage resistance and low reverse leakage.

Description

Power diode device

Technical Field

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a power diode device structure.

Background

The development and efficient utilization of energy resources are the subject of constant human development. Since the 21 st century of human history, fossil energy has been the dominant source of energy for world energy production and consumption. Combined with the development and utilization of current energy resources, fossil energy remains the energy basis for human survival and development for a long period of time. The fossil energy will be exhausted and environmental pollution will be caused easily, so that the environmental and sustainable development problems caused by the exhaustion of the fossil energy are the problems that human beings must face. Electric energy is one of the main forms of energy available for human beings, and the improvement of the use efficiency of the electric energy is an important solution for solving the energy problem of the world. The electric power system is a necessary way for human beings to utilize electric energy and improve the use efficiency of the electric energy, and the electric power system reflects the modernization degree of the electric power system on the aspects of the transportation, management and use efficiency of the electric energy. Specifically, the power system mainly adjusts, measures, controls, protects, schedules, communicates, and the like, in the process of generating electric energy, and in the process, the power semiconductor device plays a central role. The performance of the power semiconductor device determines the performance of the power system. To some extent, the performance of the power semiconductor device is good and bad, and the energy saving and emission reduction benefits are concerned.

The traditional power device is mainly a silicon-based power device, mainly comprising a thyristor, a power PIN device, a power bipolar junction device, a Schottky barrier diode, a power MOSFET and an insulated gate field effect transistor, and the silicon-based power device is widely applied in the full power range, and occupies the leading market of the power semiconductor device by virtue of long history, mature design technology and process technology. However, since researchers have studied the mechanism of the silicon-based power device more thoroughly, the performance of the silicon-based power device is close to the theoretical limit of the silicon material, and it is difficult to achieve a large improvement in performance by designing and optimizing the silicon-based power device.

Wide bandgap semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN), also called next-generation semiconductor materials, are highly favored by power device designers for their excellent material characteristics. Silicon carbide material is a typical representative of the third generation semiconductor material, and is one of the most mature and widely applied wide bandgap semiconductor materials in the crystal growth technology and device manufacturing level at present. Compared with silicon materials, the silicon material has larger forbidden band width, higher thermal conductivity, higher electron saturation drift velocity and critical breakdown electric field which is 10 times that of the silicon materials, so that the silicon material becomes an ideal semiconductor material in the application occasions of high temperature, high frequency, high power and radiation resistance. Because the silicon carbide power device can obviously reduce the energy consumption of electronic equipment, the silicon carbide power device has the name of a green energy device which drives a new energy revolution.

As one of the representative silicon carbide power devices that have been commercialized successfully, a silicon carbide schottky barrier diode (SiC SBD) device has the advantages of fast switching speed, low forward conduction voltage drop, good reverse recovery characteristics, high thermal conductivity, and the like, and has received a certain amount of attention in the power device market. However, the problems of large reverse leakage current, low reverse withstand voltage and the like exist, and the further use of the silicon carbide Schottky barrier diode is influenced. The trench gate MOS Barrier schottky diode, TMBS (trench MOS Barrier schottky diode), which is proposed earlier in 1993 by b.j.baliga, although the device improves the above problems of the silicon carbide schottky Barrier diode, the TMBS device still has a space for further improvement due to the problems of poor reliability of the schottky junction at high temperature and low reliability of the gate oxide layer.

Disclosure of Invention

Aiming at the problems of poor high-temperature reliability of a Schottky junction, low reliability of a gate oxide layer, large reverse leakage, low reverse withstand voltage and the like of the traditional Schottky barrier diode, the invention provides the power diode device and the manufacturing method thereof, wherein the forward current level of the device is improved by forming a heterojunction between the first polycrystalline silicon 2 and the N-semiconductor drift region 4; the P + semiconductor protective layer 7 at the bottom of the first polycrystalline silicon 2 and a depletion region formed by the N-semiconductor drift region 4 just cut off the conductive channel when the device is reversely blocked, and the power line from the N-semiconductor drift region 4 is stopped, so that structures such as a trench gate and a Schottky junction contact are protected, the voltage blocking capability of the device is improved, and the reliability of a gate oxide layer is improved;

in order to achieve the purpose, the invention adopts the following technical scheme:

a power diode device comprises a cell structure, wherein the cell structure comprises a cathode metal 6, an N + semiconductor substrate 5 and an N-semiconductor drift region 4 which are sequentially arranged from bottom to top, groove structures are symmetrically arranged on two sides of the top layer of the N-semiconductor drift region 4, each groove structure comprises a P + semiconductor protective layer 7 and first polycrystalline silicon 2 which are arranged from bottom to top, and an anode metal 1 is arranged on the upper surface of the N-semiconductor drift region 4 between each groove structure and the corresponding groove structure; the cathode metal 6 forms ohmic contact with the N + semiconductor substrate 5, the anode metal 1 forms ohmic contact with the first polycrystalline silicon 2, the anode metal 1 forms Schottky contact with the N-semiconductor drift region 4, the first polycrystalline silicon 2 forms a heterojunction with the N-semiconductor drift region 4, and the heterojunction has a rectifying characteristic.

Specifically, the P + semiconductor protection layer 7 may be short-circuited with the anode metal 1, may be short-circuited with the ground, and may also be arranged in a floating manner.

Specifically, a dielectric layer 3 is arranged at the contact position of the upper side face of the first polycrystalline silicon 2 and the N-semiconductor drift region 4, so that the first polycrystalline silicon 2, the dielectric layer 3 and the N-semiconductor drift region 4 form a metal-insulator-semiconductor MIS structure, and the lower side face of the first polycrystalline silicon 2 is in contact with the N-semiconductor drift region 4 to form a heterojunction.

Specifically, the P + semiconductor protection layers 7 on the two sides extend towards the other side respectively, but the P + semiconductor protection layers 7 on the two sides are not in contact, so that the width dimension of the P + semiconductor protection layer 7 in the trench structure along the device transverse direction is larger than the width dimension of the first polysilicon 2 along the device transverse direction.

Specifically, the upper surface of the P + semiconductor protection layer 7 is provided with a through hole, the through hole comprises a plurality of discontinuous through holes in the Z direction, and the through hole is filled with the first polysilicon 2, so that the bottom of the first polysilicon 2 can be in contact with the N-semiconductor drift region 4 through the through hole arranged in the P + semiconductor protection layer 7.

Specifically, the through hole is filled with the first polysilicon 2 and the N-semiconductor drift region 4, so that the bottom of the first polysilicon 2 can be in contact with the N-semiconductor drift region 4 through the through hole arranged in the P + semiconductor protection layer 7.

Specifically, the dielectric layer 3 is arranged on the upper surface of the P + semiconductor protection layer 7, so that the P + semiconductor protection layer 7 is isolated from the first polysilicon 2; meanwhile, a dielectric layer 3 is arranged at the contact position of the first polycrystalline silicon 2 and the N-semiconductor drift region 4, so that the first polycrystalline silicon 2 is isolated from the N-semiconductor drift region 4; and a second polysilicon 8 is arranged between the dielectric layer 3 and the P + semiconductor protection layer 7, and the second polysilicon 8 is in short circuit with the anode metal 1.

Specifically, a super junction structure is arranged between the first polysilicon 2 and the N + semiconductor substrate 5, the super junction structure comprises N columns 4a and P columns 7a which are alternately arranged, and the N columns 4a and the P columns 7a meet the requirement that the charge amount is equal to Qn (Qp) by controlling and adjusting process parameters, and full depletion occurs in a blocking state; the doping concentration of the P columns 7a is lower than that of the P + semiconductor protection layer 7 and replaces the P + semiconductor protection layer 7, the doping concentration of the N columns 4a is higher than that of the N-semiconductor drift region 4, and the doping concentration of the N-semiconductor drift region 4 between the first polysilicon 2 is increased to be higher than that of the N-semiconductor drift region 4.

Specifically, a semiconductor P + + doped region 7b is further disposed between the P pillar 7a and the first polysilicon 2, the doping concentration of the semiconductor P + + doped region 7b is higher than that of the P pillar 7a, and the bottom of the semiconductor P + + doped region 7b and the top of the N pillar 4a keep the same depth.

Specifically, the first polysilicon 2 is replaced by the anode metal 1, and the metal replacing the first polysilicon 2 is in contact with the semiconductor, and the barrier height of the metal is not less than the contact barrier height formed by the original anode metal 1 and the semiconductor.

Specifically, the wide bandgap material and the narrow bandgap material in the heterojunction are silicon carbide and silicon material, respectively, and the semiconductor materials of the N-semiconductor drift region 4, the N + semiconductor substrate 5 and the P + semiconductor protection layer 7 are silicon carbide.

In particular, the wide bandgap material and the narrow bandgap material in the heterojunction are also applicable to other combinations of wide bandgap materials and narrow bandgap materials.

The invention provides a manufacturing method of a power diode device, which comprises the following steps:

step 1: manufacturing an N + semiconductor substrate 5 and an N-semiconductor drift region 4 which are sequentially stacked from bottom to top;

step 2: respectively etching symmetrical grooves on two sides of the top layer of the N-semiconductor drift region 4;

and 3, step 3: forming a P + semiconductor protection layer 7 at the bottom of the groove;

and 4, step 4: forming a first polysilicon 2 on the P + semiconductor protection layer 7;

and 5, step 5: an anode metal 1 is formed on the upper surface of the first polysilicon 2 and the upper surface of the N-semiconductor drift region 4 between the trenches, and a cathode metal 6 is formed on the lower surface of the N + semiconductor substrate 5.

Specifically, in the step 1, a silicon carbide wafer with proper resistivity and thickness is selected to manufacture an N + silicon carbide substrate 5 and an N-silicon carbide drift region 4 which are sequentially stacked from bottom to top.

Specifically, the step 2 is to etch the symmetrical grooves by using a Trench mask through a groove etching process.

Specifically, after the symmetrical trenches are etched in the step 2, the etching depth is increased, the P columns and the N-type epitaxial layers formed by multiple times of epitaxy, thermal diffusion and etching are distributed alternately, and proper doping concentrations and widths of the N columns 4a and the P columns 7a are formed through process control, so that the charge numbers of the N columns 4a and the P columns 7a are the same, and a super junction structure is formed.

Specifically, after the super junction structure is formed, ion implantation is performed once in the top end region of the P pillar 7a, so as to form the higher doped P + + silicon carbide protective layer 7 b.

Specifically, a layer of P-type silicon carbide is deposited at the bottom of the trench in the step 3, and then unnecessary P-type silicon carbide is removed by etching to form a P + silicon carbide protective layer 7.

Specifically, after the P + silicon carbide protective layer 7 is formed in the step 3, thermal diffusion is performed once, so that the P + silicon carbide protective layers 7 on the two sides extend to the other side respectively to form the P + silicon carbide protective layer 7 with a larger transverse width, and the P + silicon carbide protective layers 7 on the two sides are not in contact with each other.

Specifically, after the P + semiconductor protection layer 7 is formed in the step 3, a trench having the same depth as the P + semiconductor protection layer 7 is etched in the P + semiconductor protection layer 7, so that the first polysilicon 2 formed in the step 4 is in contact with the N-semiconductor drift region 4 at the bottom of the trench.

Specifically, in the step 4, a layer of polycrystalline silicon is deposited on the upper surface of the P + silicon carbide protective layer 7 at the bottom of the groove, and redundant polycrystalline silicon is removed through etching to form the first polycrystalline silicon 2.

Specifically, step a is further included between the 4 th step and the 5 th step, and the step a includes the following steps:

a 1: forming a dielectric layer 3 on the upper surface of the first polysilicon 2 and the side wall of the groove;

a 2: etching the dielectric layer 3 on the upper surface of the first polysilicon 2;

a 3: and continuously depositing polycrystalline silicon on the upper surface of the first polycrystalline silicon 2 and removing redundant polycrystalline silicon by etching to form the first polycrystalline silicon 2 positioned on the P + semiconductor protection layer 7 in the groove, wherein a dielectric layer 3 is arranged at the contact part of the upper side surface of the first polycrystalline silicon 2 and the N-semiconductor drift region 4.

Specifically, the first polysilicon 2 deposited in step 4 and step a3 may be either N-type polysilicon or P-type polysilicon.

Specifically, when the dielectric layer 3 and the first polysilicon 2 are formed, a layer of silicon nitride is deposited, thermal oxidation is performed, then the silicon nitride is etched by hot phosphoric acid, finally the first polysilicon 2 is deposited in the trench by deposition and etching processes,

specifically, step a1 forms the dielectric layer 3 through a dry oxygen oxidation process.

Specifically, the anode metal 1 and the cathode metal 6 are formed in the step 5 through deposition, photolithography and etching processes.

Specifically, without performing step 4, the anode metal 1 is directly formed on the P + semiconductor protection layer 7 and the upper surface of the N-semiconductor drift region 4 between the first trench and the second trench.

The principle of the present invention is illustrated below by taking as an example that the wide bandgap material and the narrow bandgap material in the heterojunction of the present invention are silicon carbide and silicon material, respectively, and the semiconductor materials of the N-semiconductor drift region 4, the N + semiconductor substrate 5 and the P + semiconductor protection layer 7 are silicon carbide. The principle of the invention is explained as follows: although the groove gate MOS barrier Schottky diode provided by B.J.Baliga improves the problems of larger reverse leakage, lower reverse withstand voltage and the like of the silicon carbide Schottky barrier diode, the problems of poor high-temperature reliability of a Schottky junction, low reliability of a gate oxide layer and the like of the Schottky junction enable a TMBS device to have a further optimization space. The present invention proposes a structure capable of optimizing the above-mentioned deficiencies of the trench gate MOS barrier schottky diode by structural improvement, as shown in fig. 2. For convenience in explaining the principles of the present invention, a power diode device functional block of the present invention is labeled as in fig. 3. The A functional block is a Schottky barrier structure part formed by anode metal 1 and an N-silicon carbide drift region 4; the B functional block is a metal-insulating layer-semiconductor MIS structure part consisting of first polysilicon 2, a dielectric layer 3 and an N-silicon carbide drift region 4; the C functional block is a Si/SiC heterojunction part with rectification characteristic, which is formed by the first polycrystalline silicon 2 and the N-silicon carbide drift region 4; the D functional block is a PN junction structure formed by the P + silicon carbide protective layer 7 and the N-silicon carbide drift region 4.

When the device is in a forward conducting state, the anode metal 1 is connected with a high potential, and the cathode metal 6 is connected with a low potential. The PN junction formed by the P + silicon carbide protective layer 7 (taking the P + silicon carbide protective layer 7 shorted with the anode metal 1 as an example) and the N-silicon carbide drift region 4 is forward biased, the depletion region is shown by a dotted line in fig. 4, and a large multi-sub-channel is formed by a very narrow depletion region width. When the device is in an off state, the anode metal 1 is connected with a low potential, the cathode metal 6 is connected with a high potential, a PN junction formed by the P + silicon carbide protective layer 7 (also taking short circuit with the anode metal 1 as an example) and the N-silicon carbide drift region 4 is reversely biased, and a narrower leakage channel is formed due to the increase of the width of a depletion region caused by the PN junction reverse bias. When the voltage of the cathode metal 6 further rises, the depletion region of the reverse biased PN junction further expands, and finally the leakage channel is completely isolated, as shown by a dotted line in FIG. 5, and at the moment, the voltage resistance of the device is completely born by the PN junction formed by the P + silicon carbide protective layer 7 and the N-silicon carbide drift region 4. Because the silicon carbide PN junction has high potential barrier when being reversely biased, and does not have 'mirror force', compared with a groove gate MOS barrier Schottky diode, the power diode has lower reverse leakage, and simultaneously improves the high-temperature reliability of the device in a blocking state. In addition, as the P + silicon carbide protective layer 7 shields electric lines from the N-silicon carbide drift region 4, the gate dielectric of the device has a lower electric field, thereby improving the gate reliability and the voltage resistance level of the device, as shown in FIG. 6. Meanwhile, when the device is in a forward conducting state, the anode metal 1 is connected with a high potential, and the cathode metal 6 is connected with a low potential. When the voltage of the applied anode metal 1 is larger than the forward conduction voltage drop of the Schottky junction, the device is in a forward conduction state, and the device is conducted. The side wall of the gate dielectric is provided with a multi-sub accumulation layer by the B functional region, namely the MIS structure, and the forward conduction voltage drop of the device is remarkably reduced by the accumulation layer; when the voltage of the applied anode metal 1 is greater than the forward conduction voltage of the Si/SiC heterojunction, the Si/SiC heterojunction formed by the first polysilicon 2 and the N-silicon carbide drift region 4 starts to conduct, and the branch currents are the same as the majority current, increasing the current density level when the device conducts in the forward direction, as shown in fig. 6. The PN junction structure formed by the D functional block, namely the P + silicon carbide protective layer 7 and the N-silicon carbide drift region 4, because the P + silicon carbide protective layer 7 is in short circuit with the anode metal 1, when the device is in a forward conduction state, if the voltage of the anode metal 1 reaches the conduction condition (namely about 3.1V) of the PN junction, the PN junction is conducted, and the structure can improve the surge current resistance of the device. In addition, the voltage blocking capability of the super junction structure is remarkably improved by the epitaxial layer formed by the super junction structure, so that the better compromise characteristic of forward voltage drop and breakdown voltage is obtained.

By combining the above analysis, the beneficial effects of the invention are:

compared with the traditional groove gate MOS barrier Schottky diode, the power diode structure provided by the invention has lower reverse leakage, higher voltage blocking capability and better high-temperature reliability, so that the structure has a larger reverse safe working area;

compared with the traditional groove gate MOS barrier Schottky diode, the power diode structure provided by the invention has a lower gate dielectric electric field, so that higher gate reliability is realized;

thirdly, the power diode structure provided by the invention has a Si/SiC heterojunction structure, and increases the current branch of the device in the forward conducting state, so that the current density of the device in the forward conducting state is improved;

fourthly, the power diode structure provided by the invention has a PN junction structure, and is conducted under the condition that the voltage of anode metal is larger, and the conduction of the structure has a certain lightening effect on the harm brought by surge current reduction, so that the structure has a larger forward safe working area;

fifthly, the voltage blocking capability of the structure is remarkably improved by the epitaxial layer formed by the super junction structure, so that the better compromise characteristic of forward voltage drop and breakdown voltage is obtained.

Drawings

Fig. 1 is a schematic diagram of a cell structure of a conventional trench gate MOS barrier schottky diode (TMBS) device.

Fig. 2 is a schematic structural diagram of a power diode device cell provided in embodiment 1 of the present invention.

Fig. 3 is a schematic diagram illustrating the principle of a power diode device according to the present invention.

Fig. 4 is a schematic diagram illustrating the principle of a power diode device according to the present invention.

Fig. 5 is a schematic diagram illustrating the principle of a power diode device according to the present invention.

Fig. 6 is a schematic diagram illustrating the principle of a power diode device according to the present invention.

Fig. 7 is a schematic structural diagram of a power diode device cell according to embodiment 2 of the present invention.

Fig. 8 is a schematic structural diagram of a power diode device cell according to embodiment 3 of the present invention.

Fig. 9 is a schematic diagram of a power diode device cell structure and a module a provided in embodiment 1 of the present invention in a YZ plane.

Fig. 10 is a schematic structural diagram of a power diode device cell according to embodiment 4 of the present invention.

Fig. 11 is a schematic structural diagram of a power diode device cell according to embodiment 5 of the present invention.

Fig. 12 is a schematic structural diagram of a power diode device cell according to embodiment 7 of the present invention.

Fig. 13 is a schematic structural diagram of a power diode device cell according to embodiment 8 of the present invention.

Fig. 14 is a schematic structural diagram of a power diode device cell according to embodiment 9 of the present invention.

Fig. 15 is a schematic view of an N + silicon carbide substrate 5 and an N-silicon carbide drift region 4 provided in embodiment 10 of the present invention.

Fig. 16 is a schematic diagram of etching a first Trench and a second Trench by using a Trench mask through a Trench etching process according to embodiment 10 of the present invention.

Fig. 17 is a schematic diagram of forming a P + silicon carbide protective layer 7 by deposition and etching processes according to embodiment 10 of the present invention.

Fig. 18 is a schematic diagram of forming a portion of the first polysilicon 2 by deposition and etching processes according to embodiment 10 of the present invention.

Fig. 19 is a schematic diagram of forming the dielectric layer 3 by a dry oxygen oxidation process according to embodiment 10 of the present invention.

Fig. 20 is a schematic diagram of the dielectric layer 3 selectively etching the surface of the first polysilicon 2 by an etching process according to embodiment 10 of the present invention.

Fig. 21 is a schematic diagram of depositing polysilicon in the trench to form the first polysilicon 2 by deposition and etching processes according to embodiment 10 of the present invention.

Fig. 22 is a schematic diagram of forming the anode metal 1 and the cathode metal 6 by deposition, photolithography and etching processes according to embodiment 10 of the present invention.

The numbering in the figures means the following:

1 is anode metal; 2 is a polysilicon gate; 3 is a polysilicon gate medium; 4/4a/4b is an N-semiconductor drift region; 5 is an N + semiconductor substrate; 6 is a cathode metal; 7/7a/7b is P + semiconductor protection layer; and 8 is polysilicon.

Detailed Description

The technical solutions and implementation principles of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments. The examples are given solely for the purpose of illustration and are not intended to limit the scope of the invention.

Example 1:

in this embodiment, a 1200V silicon carbide power diode device is taken as an example, and a schematic diagram of a cell of the power diode device is shown in fig. 2, and the power diode device includes a cathode metal 6, an N + semiconductor substrate 5, and an N-semiconductor drift region 4, which are sequentially disposed from bottom to top, and is characterized in that trench structures are symmetrically disposed on two sides of a top layer of the N-semiconductor drift region 4, each trench structure includes a P + semiconductor protection layer 7 and first polysilicon 2 disposed from bottom to top, and an anode metal 1 is disposed on an upper surface of the N-semiconductor drift region 4 between the trench structure and the trench structure; in the embodiment, the P + silicon carbide protective layer 7 is in short circuit with the anode metal 1, and the P + silicon carbide protective layer 7 can also be in short circuit with the ground or float; a dielectric layer 3 is arranged at the contact position of the top layer of the first polycrystalline silicon 2 and the N-silicon carbide drift region 4, and the first polycrystalline silicon 2, the dielectric layer 3 and the N-silicon carbide drift region 4 form a metal-insulating layer-silicon carbide MIS structure; the cathode metal 6 forms ohmic contact with the N + semiconductor substrate 5, the anode metal 1 forms ohmic contact with the first polycrystalline silicon 2, the anode metal 1 forms Schottky contact with the N-semiconductor drift region 4, and the first polycrystalline silicon 2 forms a heterojunction with the N-semiconductor drift region 4.

Wherein, the thickness of the anode metal 1 and the cathode metal 6 is 0.5-2 μm, and the width is 0.5-2 μm; the doping concentration of the N + silicon carbide substrate 5 is 1e 18-9 e18/cm³The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide drift region 4 is 2e 15-8 e15/cm³The thickness is 5-8 μm, and the width is 0.5-2 μm; the P + silicon carbide protective layer 7 has a thickness of about 0.8 to 1.1 μm and a doping concentration of about 1e19 to 7e19/cm³The width is about 0.3-0.5 μm; the width of the first polysilicon 2 is about 0.3-0.5 μm, and the thickness is about 0.8-1.6 μm; the thickness of the dielectric layer 3 is about 10nm to 50 nm.

The power diode provided by the embodiment forms four functional blocks such as a schottky junction structure, an MIS structure, a Si/SiC heterojunction and a silicon carbide PN junction, and the P + silicon carbide protective layer 7 terminates a power line from the N-silicon carbide drift region 4 when the device is reversely blocked, so that structures such as a trench gate and a schottky junction contact are protected, the voltage blocking capability of the device is improved, and the reliability of a gate oxide layer is improved; when the device is in a reverse state, a depletion region formed by the P + silicon carbide protective layer 7 and the N-silicon carbide drift region 4 just cuts off a conductive channel, namely, the withstand voltage is completely borne by a silicon carbide PN junction, the improvement obviously reduces the leakage current level of the TMBS device and improves the high-temperature reliability of the Schottky junction; the Si/SiC heterojunction well improves the forward current level of the TMBS device, so that the device has the advantages of being superior to a groove gate MOS barrier Schottky diode in performance in many aspects.

Example 2:

the present embodiment is modified to a certain extent from embodiment 1, and has a structure substantially the same as that of embodiment 2, except that the P + silicon carbide protective layers 7 on both sides extend toward the other side, respectively, so that the P + silicon carbide protective layers 7 have a larger lateral width, which is 0.4 to 0.7 μm, as shown in fig. 7. The larger the lateral width of the P + silicon carbide region protective layer 7 is made, the stronger the electric field shielding effect on the region above the P + silicon carbide protective layer 7 when the device is in the blocking state, that is, the Si/SiC heterojunction, the MIS structure, and the schottky junction structure are protected. The voltage resistance of the device is improved while the structure is protected. It should be noted, however, that the wider the width of the P + silicon carbide protective layer 7, the greater the on-resistance of the device when it is operating in the forward direction. The width of the P + silicon carbide protective layer 7 therefore needs to be considered between forward and reverse operation.

Example 3:

the present embodiment is modified to some extent with respect to embodiment 1 and embodiment 2, and the structure thereof is substantially the same as embodiment 2, except that the improved structure does not include the dielectric layer 3, that is, the first polysilicon 2 and the N-SiC drift region 4 completely form a Si/SiC heterojunction structure at the sidewall contact surface of the first trench and the second trench. The improvement of the structure further increases the level of the branch current in the on state of the device and optimizes the forward performance of the device, as shown in fig. 8.

Example 4:

this embodiment is modified to some extent with respect to embodiment 1, embodiment 2, and embodiment 3, and has a structure substantially the same as that of embodiment 1, except that a plurality of discontinuous through holes in the Z direction are disposed on the upper surface of the P + silicon carbide protective layer 7, and the through holes are filled with the first polysilicon 2, so that the bottom of the first polysilicon 2 can contact the N-semiconductor drift region 4 through the through holes disposed in the P + semiconductor protective layer 7, as shown in fig. 10. The mode increases the area of the heterojunction and improves the on-state current density of the device.

Example 5:

this embodiment is modified to a certain extent with respect to embodiment 4, and has a structure substantially the same as that of embodiment 4, except that the through hole is filled with an N-semiconductor material, so that the bottom of the first polysilicon 2 can contact the N-semiconductor drift region 4 through the through hole disposed in the P + semiconductor protection layer 7, as shown in fig. 11. The mode increases the area of the heterojunction and improves the on-state current density of the device. Meanwhile, the leakage current is further reduced because the newly added heterojunction part has P + region protection.

Example 6:

this embodiment is modified to some extent with respect to embodiment 1, embodiment 2, and embodiment 3, and has a structure substantially the same as that of embodiment 3, except that the modified structure does not include the first polysilicon 2, and the anode metal 1 is directly deposited in the first trench and the second trench to contact the P + silicon carbide protective layer 7. Because the P + silicon carbide protective layer 7 protects the Schottky junction barrier, the problems of large leakage current, poor high-temperature reliability and the like of the Schottky junction can be avoided, so that the area of the Schottky junction can be enlarged to improve the forward current level of the device.

Example 7:

the present embodiment is modified to a certain extent with respect to embodiment 1, and the structure thereof is substantially the same as that of embodiment 1, except that the first polysilicon 2 may be divided into two parts, which are separated by the dielectric layer 3, the dielectric layer 3 extends along the trench sidewall and the upper surface of the P + silicon carbide protection layer 7 to separate the P + silicon carbide protection layer 7 from the first polysilicon 2, and the second polysilicon 8 is disposed between the dielectric layer 3 and the P + silicon carbide protection layer 7, the second polysilicon 8 is short-circuited with the anode metal 1 through ohmic contact, and the material of the second polysilicon 8 may be the same as that of the first polysilicon 2, that is, as shown in fig. 12. The second polysilicon 8 and the N-SiC drift region 4 form a Si/SiC heterojunction on the sidewall. The heterojunction increases current branch in on-state, and improves the on-state current level of the device.

Example 8:

this embodiment is modified to some extent with respect to embodiment 1, embodiment 2, embodiment 3, embodiment 6, and embodiment 7, and has a structure substantially the same as that of embodiment 1, except that a P + silicon carbide protective layer 7 and an N-silicon carbide region 4 may be made into a super junction structure, taking the modification of embodiment 1 as an example, as shown in fig. 13, the super junction structure includes N columns 4a and P columns 7a alternately arranged, and the N columns 4a and the P columns 7a meet the requirement of equal charge amount Qn — Qp by controlling and adjusting process parameters; the doping concentration of the P pillars 7a is lower than that of the P + silicon carbide protective layer 7, the doping concentration of the N pillars 4a is higher than that of the N-silicon carbide drift region 4, and the doping concentration of the N-silicon carbide drift region 4 between the first polysilicon 2 is increased to be higher than that of the N-silicon carbide drift region 4. The super junction structure improves the voltage blocking capability of the device by optimizing the electric field distribution in the blocking mode, and obtains better compromise characteristics of forward voltage drop and the voltage blocking capability.

Example 9:

this embodiment is a modification of embodiment 8 to a certain extent, and has a structure substantially the same as that of embodiment 8, except that, at the same time, the P + silicon carbide protective layer 7 and the N-silicon carbide drift region 4 are made into a super junction structure, and at the same time, a P + + silicon carbide protective layer 7b doped higher is made on the top of the P pillar 7a, as shown in fig. 14. The improvement can play a better protection role for the MIS structure and the Si/SiC heterojunction above the P column 7a and the N column 4a under the condition of full depletion.

Example 10:

in this embodiment, a method for manufacturing a 1200V sic power diode device is also taken as an example to describe the specific implementation manner of the embodiments 1 to 9, and devices with different performance parameters can be prepared according to actual requirements according to common knowledge in the art.

Step 1: and selecting a silicon carbide wafer with proper resistivity and thickness to manufacture an N + silicon carbide substrate 5 and an N-silicon carbide drift region 4 which are sequentially stacked from bottom to top. Wherein the doping concentration of the N + silicon carbide substrate 5 is 1e 18-9 e18/cm³The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of N-silicon carbide epitaxy 4 is 2e 15-8 e15/cm³The thickness is 5 μm to 8 μm, and the width is 0.5 μm to 2 μm, as shown in FIG. 15;

step 2: through a groove etching process, two grooves which are symmetrically distributed, have the width of about 0.3-0.5 mu m and the depth of about 1.1-2 mu m are respectively etched on two sides of the top layer of the N-silicon carbide drift region 4 by utilizing a Trench mask, as shown in figure 16;

and 3, step 3: respectively depositing a layer of P-type silicon carbide at the bottom of the symmetrically arranged grooves by deposition and etching processes, and removing unnecessary P-type silicon carbide by etching to form the silicon carbide with the thickness of about 0.8-1.1 mu m and the doping concentration of about 1e 19-7 e19/cm³A P + silicon carbide region 7 having a width of about 0.3 μm to about 0.5 μm, as shown in FIG. 17;

and 4, step 4: depositing a layer of polysilicon on the side surface of the trench and the surface of the P + silicon carbide protective layer 7 by deposition and etching processes, and removing redundant polysilicon by etching to form first polysilicon 2 on the surface of the P + silicon carbide region 7, as shown in fig. 18;

and 5, step 5: forming a dielectric layer 3 with a thickness of about 10nm to 50nm on the surface of the first polysilicon 2 and the side wall of the trench by a dry oxygen oxidation process at a temperature of about 1100 ℃ to 1300 ℃, as shown in fig. 19;

and 6, step 6: selectively etching the dielectric layer on the surface of the first polysilicon 2 by an etching process, and leaving the dielectric layer 3 with the thickness of about 10 nm-50 nm on the side wall of the groove, as shown in FIG. 20;

and 7, step 7: depositing a layer of polysilicon in the trench by deposition and etching processes, and removing redundant polysilicon by etching to obtain first polysilicon 2 deposited on the surface of the original first polysilicon 2, wherein the first polysilicon 2 has a width of about 0.3-0.5 μm and a thickness of about 0.8-1.6 μm, as shown in fig. 21;

and 8, step 8: an anode metal 1 and a cathode metal 6 with a thickness of 0.5 to 2 μm and a width of 0.5 to 2 μm are formed on the upper surface and the lower surface of the device by deposition, photolithography and etching processes, as shown in fig. 22. Thus, the device is completed.

Further, after the P + silicon carbide is deposited in the step 3, a thermal diffusion may be performed to extend the P + silicon carbide protective layers 7 on the two sides to the other side to form the P + silicon carbide protective layer 7 having a lateral width larger than that of the P + silicon carbide protective layer 7 shown in fig. 2, where the width is about 0.4-0.7 μm, and the P + silicon carbide protective layers 7 on the two sides are not in contact with each other, as shown in fig. 7.

Further, after the P + semiconductor protection layer 7 is formed in the step 3, a through hole is etched in the P + semiconductor protection layer 7, and the first polysilicon 2 is deposited and filled in the through hole, so that the first polysilicon 2 contacts the N-semiconductor drift region 4 at the bottom of the trench, as shown in fig. 10. The same area of the conventional structure is shown in fig. 12.

Further, after the P + semiconductor protection layer 7 is formed in the step 3, a through hole is etched in the P + semiconductor protection layer 7, and the first polysilicon 2 and the N-semiconductor drift region 4 are deposited and filled in the through hole, so that the first polysilicon 2 contacts the N-semiconductor drift region 4 at the bottom of the trench, as shown in fig. 14.

Further, the steps 5 to 7 may not be required, i.e., the dielectric layer 3 is not provided, as shown in fig. 8.

Further, the step 4-7 is not needed, namely the first polysilicon 2 and dielectric layer 3 structure is not arranged, and the anode metal 1 is directly deposited in the groove.

Further, by controlling the process, the continuous first polysilicon 2 can be formed, as shown in fig. 2, and the discontinuous first polysilicon 2 and the discontinuous second polysilicon 8 can be formed by isolating the dielectric layer 3, as shown in fig. 12.

Further, when the Trench is formed by etching using the Trench mask in step 2, the etching depth can be increased, the P pillars and the N-type epitaxial layer formed by multiple times of epitaxy, thermal diffusion and etching are distributed alternately, and appropriate doping concentrations and widths of the N pillars 4a and the P pillars 7a are formed by process control, so that the charge numbers of the N pillars 4a and the P pillars 7a are the same, that is, a super junction structure is formed, as shown in fig. 13.

Further, ion implantation is performed once in the top end region of the P column 7a after the super junction structure is formed, and a more highly doped P + + silicon carbide protective layer 7b is formed, as shown in fig. 14.

Further, the first polysilicon 2 deposited in the

steps

4 and 7 may be either N-type polysilicon or P-type polysilicon.

Further, when the dielectric layer 3 and the first polysilicon 2 are formed in the 5 th to 7 th steps, a layer of silicon nitride may be deposited, then thermal oxidation is performed, then the silicon nitride is etched by using hot phosphoric acid, and finally the first polysilicon 2 is deposited in the trench by deposition and etching processes, as shown in fig. 21.

Further, the wide and narrow bandgap materials used in the power diode device are not limited to silicon carbide and silicon materials, and the wide and narrow bandgap materials can be combined with other materials to form the power diode device.

It should also be claimed that: as known to those skilled in the art based on the basic knowledge in the art, in the structure and process of the power diode device of the present invention, the N-type polysilicon may also be implemented by P-type polysilicon, P-type single crystal silicon, or N-type single crystal silicon; the dielectric material used can be silicon dioxide (SiO)₂) This can also be achieved by using silicon nitride (Si)₃N₄) Hafnium oxide (HfO)₂) Aluminum oxide (Al)₂O₃) And the high-K dielectric materials are realized. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.

Claims

1. A power diode device is characterized in that a cell structure of the power diode device comprises a cathode metal (6), an N + semiconductor substrate (5) and an N-semiconductor drift region (4) which are sequentially arranged from bottom to top, wherein two sides of the top layer of the N-semiconductor drift region (4) are symmetrically provided with a groove structure, the groove structure comprises a P + semiconductor protective layer (7) and first polycrystalline silicon (2) which are arranged from bottom to top, and an anode metal (1) is arranged on the upper surface of the N-semiconductor drift region (4) between the groove structure and the groove structure; the cathode metal (6) forms an ohmic contact with the N + semiconductor substrate (5), the anode metal (1) forms an ohmic contact with the first polysilicon (2), the anode metal (1) forms a Schottky contact with the N-semiconductor drift region (4), and the first polysilicon (2) forms a heterojunction with the N-semiconductor drift region (4);

a dielectric layer (3) is arranged at the contact position of the upper side face of the first polycrystalline silicon (2) and the N-semiconductor drift region (4), so that the first polycrystalline silicon (2), the dielectric layer (3) and the N-semiconductor drift region (4) form a metal-insulator-semiconductor MIS structure; the side face of the lower part of the first polycrystalline silicon (2) is contacted with the N-semiconductor drift region (4) to form a heterojunction.

2. The power diode device according to claim 1, wherein the two P + semiconductor protection layers (7) extend towards the other side respectively, but the two P + semiconductor protection layers (7) do not contact each other, so that the width dimension of the P + semiconductor protection layer (7) in the trench structure along the device transverse direction is larger than the width dimension of the first polysilicon (2) along the device transverse direction.

3. The power diode device according to claim 1, wherein a via is provided in the P + semiconductor protection layer (7), and the via is filled with the first polysilicon (2), so that the bottom of the first polysilicon (2) can contact the N-semiconductor drift region (4) through the via provided in the P + semiconductor protection layer (7).

4. The power diode device according to claim 1, wherein a via is provided in the P + semiconductor protection layer (7), and the via is filled with an N-semiconductor material, so that the bottom of the first polysilicon (2) can contact the N-semiconductor drift region (4) through the via provided in the P + semiconductor protection layer (7).

5. The power diode device according to claim 1, wherein a dielectric layer (3) is provided on the upper surface of the P + semiconductor protection layer (7) so that the P + semiconductor protection layer (7) is isolated from the first polysilicon (2); meanwhile, a dielectric layer (3) is arranged at the contact position of the first polycrystalline silicon (2) and the N-semiconductor drift region (4), so that the first polycrystalline silicon (2) is isolated from the N-semiconductor drift region (4); and a second polysilicon (8) is arranged between the dielectric layer (3) and the P + semiconductor protection layer (7), and the second polysilicon (8) is in short circuit with the anode metal (1).

6. The power diode device according to claim 1, wherein the first polysilicon (2) and the N + semiconductor substrate (5) have a super junction structure therebetween, the super junction structure comprises N pillars (4a) and P pillars (7a) arranged alternately, the P pillars (7a) have a doping concentration lower than that of the P + semiconductor protection layer (7) and replace the P + semiconductor protection layer (7), and the N pillars (4a) have a doping concentration higher than that of the N-semiconductor drift region (4).

7. The power diode device according to claim 6, wherein a semiconductor P + + doped region (7b) is further disposed between the P pillar (7a) and the first polysilicon (2), and a doping concentration of the semiconductor P + + doped region (7b) is higher than a doping concentration of the P pillar (7 a).

8. The power diode device of any of claims 1 to 7, wherein the wide and narrow bandgap materials in the heterojunction are silicon carbide and silicon material, respectively.