CN114762108A

CN114762108A - Integrated circuit

Info

Publication number: CN114762108A
Application number: CN201980102524.2A
Authority: CN
Inventors: 黄继超; 闵卿
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2022-07-15
Also published as: WO2021102940A1

Abstract

An integrated circuit, wherein the integrated circuit comprises: a chip (102) and an encapsulation layer (101) for encapsulating the chip (102). The chip (102) comprises a substrate (1022) and an inductor (1021) arranged on the substrate (1022), the packaging layer (101) comprises a first pattern ground shielding structure (1011), the first pattern ground shielding structure (1011) is located on a metal layer in the packaging layer (101), the first pattern ground shielding structure (1011) is formed by etching metal of the metal layer, the first pattern ground shielding structure (1011) is located on the inductor (1021), and the first pattern ground shielding structure (1011) is used for reducing induction current caused by the inductor (1021) in the metal layer. When the inductor (1021) is in a working state, due to the existence of the first pattern ground shielding structure (1011), an induced current generated by a current changing on the inductor (1021) in the first pattern ground shielding structure (1011) is small, so that the eddy current effect of the electronic element can be reduced, and the performance of the electronic element can be improved.

Description

Integrated circuit

Technical Field

The embodiment of the application relates to the field of electronic circuits, in particular to an integrated circuit.

Background

The integrated circuit with the characteristics of miniature volume and low power consumption can integrate various module circuits of electronic elements, such as a capacitor, an inductor, a resistor and the like, so as to achieve the purposes of reducing cost and the like, and can be widely applied to wireless communication modules, portable communication equipment and the like.

Fig. 1 is a schematic structural diagram of a conventional integrated circuit, which includes an encapsulation layer and a chip, as shown in fig. 1, wherein the chip includes a substrate and an inductor disposed on the substrate. When the inductor is in an operating state, a large induced current (i.e., eddy current) is generated in the metal conductor in the encapsulation layer due to a change in current in the inductor, which further affects the inductance and quality factor of the inductor, resulting in a decrease in the performance of the inductor.

Disclosure of Invention

The embodiment of the application provides an integrated circuit, which can reduce the eddy current effect of an inductor and improve the performance of the inductor.

A first aspect of embodiments of the present application provides an integrated circuit, including: the chip comprises a chip and an encapsulation layer for encapsulating the chip. The chip comprises a substrate and an inductor arranged on the substrate, the packaging layer comprises a first Pattern Ground Shield (PGS), the first PGS is located on a metal layer in the packaging layer and formed by etching metal on the metal layer, the first PGS is located on the inductor, and the first PGS is used for reducing induction current caused by the inductor in the metal layer.

In the integrated circuit, the package layer includes package metal, wherein a portion of the package metal is etched into a first PGS, and the first PGS is located above the inductor. When the inductor in the chip is in a working state, the first PGS can reduce induced current caused by the inductor in the packaging layer, reduce the eddy current effect of the inductor and improve the performance of the inductor.

In combination with the first aspect of the embodiment of the present application, in a first implementation manner of the first aspect of the embodiment of the present application, the first PGS may be etched to have a shape with a plurality of cutouts, and each cutout may be configured to break a path of the induced current, so that the first PGS can reduce the induced current caused by the inductor in the encapsulation layer.

With reference to the first aspect of the embodiment of the present application or the first implementation manner of the first aspect of the embodiment of the present application, in a second implementation manner of the first aspect of the embodiment of the present application, the first PGS in the encapsulation layer directly faces the inductor, and by setting a relative position between the first PGS and the inductor, an eddy current effect of the inductor may be further reduced.

With reference to the first aspect of the embodiment of the present application, the first implementation manner of the first aspect of the embodiment of the present application or the second implementation manner of the first aspect of the embodiment of the present application, in a third implementation manner of the first aspect of the embodiment of the present application, a second PGS is disposed between the inductor and the substrate, and the second PGS is configured to reduce an induced current caused by the inductor in the substrate, so that performance of the inductor can be further improved.

With reference to the third implementation manner of the first aspect of the embodiment of the present application, in a fourth implementation manner of the first aspect of the embodiment of the present application, the second PGS is made of polysilicon.

With reference to the fourth implementation manner of the first aspect of the embodiment of the present application, in a fifth implementation manner of the first aspect of the embodiment of the present application, the encapsulation layer further includes a first dielectric layer, and the first dielectric layer is used to cover the encapsulation metal, that is, to cover the first PGS.

With reference to the fifth implementation manner of the first aspect of the embodiment of the present application, in a sixth implementation manner of the first aspect of the embodiment of the present application, the chip further includes a second dielectric layer, and the second dielectric layer is used to cover the inductor and the second PGS.

With reference to the sixth implementation manner of the first aspect of the embodiment of the present application, in a seventh implementation manner of the first aspect of the embodiment of the present application, the first dielectric layer is made of a first insulating material, so that the encapsulation layer has a good encapsulation function.

With reference to the seventh implementation manner of the first aspect of the embodiment of the present application, in an eighth implementation manner of the first aspect of the embodiment of the present application, the second dielectric layer is made of a second insulating material, and since the second insulating material is different from the first insulating material, the first dielectric layer and the second dielectric layer have a certain degree of difference, so that the entire integrated circuit is well-graded.

With reference to the first aspect of the embodiment of the present application, in a ninth implementation manner of the first aspect of the embodiment of the present application, the size of the encapsulation layer is generally greater than or equal to the size of the chip, so that the structure of the entire integrated circuit is more compact.

A second aspect of embodiments of the present application provides an integrated circuit, which includes a chip and an encapsulation layer for encapsulating the chip, the chip including a voltage-controlled oscillator, the voltage-controlled oscillator including: the circuit comprises an inductor, a variable capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor.

The first end of the first transistor is connected with the first end of the variable capacitor, the first end of the second transistor is connected with the second end of the variable capacitor, the second end of the first transistor and the second end of the second transistor are both connected with the power supply, the third end of the first transistor is connected with the second end of the variable capacitor, the third end of the second transistor is connected with the first end of the variable capacitor, the variable capacitor and the capacitor are connected with the inductor in parallel, the first end of the third transistor is connected with the first end of the inductor, the first end of the fourth transistor is connected with the second end of the inductor, the second end of the third transistor and the second end of the fourth transistor are both grounded, the third end of the third transistor is connected with the second end of the inductor, and the third end of the fourth transistor is connected with the first end of the inductor;

The packaging layer comprises a first PGS, the first PGS is formed by etching packaging metal in the packaging layer, the first PGS is opposite to the inductor, and the first PGS is used for reducing induction current caused by the inductor in the packaging layer.

In the voltage-controlled oscillator, due to the existence of the first PGS in the packaging layer, the performance of the inductor can be improved, the frequency offset of the voltage-controlled oscillator can be reduced, and the noise performance of the voltage-controlled oscillator can be improved.

In combination with the second aspect of the embodiment of the present application, in the first implementation manner of the second aspect of the embodiment of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor are all metal-oxide-semiconductor field-effect transistors (MOSFETs) or Bipolar Junction Transistors (BJTs), so that flexibility and selectivity of the scheme are improved.

The integrated circuit provided by the embodiment of the application comprises: the chip comprises a chip and an encapsulation layer for encapsulating the chip. The chip comprises a substrate and an inductor arranged on the substrate, the packaging layer comprises a first PGS, the first PGS is located on a metal layer in the packaging layer and formed by etching metal on the metal layer, the first PGS is located on the inductor, and the first PGS is used for reducing induction current caused by the inductor in the metal layer. When the inductor is in a working state, due to the existence of the first PGS, the induced current generated in the first PGS by the current changing on the inductor is very small, so that the eddy current effect of the electronic element can be reduced, and the performance of the electronic element can be improved.

Drawings

FIG. 1 is a schematic diagram of a conventional integrated circuit;

FIG. 2 is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure;

FIG. 3 is another schematic diagram of an integrated circuit provided by an embodiment of the present application;

fig. 4 is a schematic diagram of a first PGS according to an embodiment of the present application;

FIG. 5 is another schematic diagram of an integrated circuit provided by an embodiment of the present application;

FIG. 6 is a graph showing simulation results of inductance values provided in the present embodiment;

fig. 7 is a diagram illustrating a simulation result of the inductance quality factor according to an embodiment of the present disclosure.

Detailed Description

The following describes technical solutions in the embodiments of the present application in detail with reference to the drawings in the embodiments of the present application.

Fig. 2 is a schematic structural diagram of an integrated circuit according to an embodiment of the present disclosure, referring to fig. 2, the integrated circuit includes: chip 102 and encapsulation layer 101, encapsulation layer 101 is used to encapsulate chip 102. The chip 102 includes a substrate 1022 and an inductor 1021 arranged on the substrate 1022, the package layer 101 includes a metal layer, a portion of the metal is etched into a first PGS1011, the first PGS1011 is located on the inductor 1021, and the first PGS1011 is configured to reduce an induced current caused by the inductor 1021 in the package layer 101.

It is noted that the first PGS1011 is generally disposed above the inductor 1021, that is, the first PGS1011 is disposed opposite to the inductor 1021, specifically, the first PGS1011 may cover the inductor 1021, or slightly deviate from the inductor 1021, and the first PGS1011 and the inductor 1021 have a certain overlapping area, and in order to make the function of the first PGS1011 better, the first PGS1011 in the package layer 101 may be directly opposite to the inductor 1021, that is, the first PGS1011 is located directly above the inductor 1021, and when the inductor 1021 is in a working state, due to the existence of the first PGS1011, an induced current generated in the first PGS1011 by a current changing on the inductor 1021 is small, so that the first PGS1011 can reduce an eddy current effect of the inductor 103, and improve the performance of the inductor 1021.

The first PGS1011 is formed by etching based on the packaging metal in the packaging layer 101, for example, a portion of the metal conductor opposite to the inductor 1021 may be selected from the packaging metal to be etched, so as to obtain the first PGS1011 with a specific shape. In addition, the first PGS1011 is usually etched to have a fence-like shape, that is, the first PGS1011 has a plurality of slits, and each slit of the first PGS1011 can be used to break a path of an induced current, that is, cut off a path of the induced current, compared with a metal conductor having a complete area, so that the first PGS1011 can reduce the induced current caused by the inductor 1021 in the package layer 101.

Further, the first PGS1011 may also be etched to form a symmetrical fence-like shape or an asymmetrical fence-like shape, and the corresponding arrangement may be performed according to the actual shape of the inductor 1021. To facilitate understanding, the shape of the first PGS1011 is further described with reference to fig. 3, and fig. 3 is another schematic diagram of an integrated circuit provided in an embodiment of the present application, as shown in fig. 3, in the integrated circuit, the inductor 1021 has a meandering and axisymmetric strip shape, so that the first PGS1011 can also be arranged in an axisymmetric fence-like shape, in the fence-like first PGS1011, the main structure is formed by one first metal strip 10111 and three parallel second metal strips 10112, the first metal strip 10111 is perpendicular to the three second metal strips 10112, so that the main structure has four right-angle extensions, each right-angle extension is provided with a secondary structure, each secondary structure is formed by one obliquely arranged third metal strip 10113 and a fourth metal strip 10114 extending outwards on the basis of the third metal strip 10113, therefore, the first PGS1011 has a plurality of cutouts 1013, and due to the presence of the cutouts 1013, since only the central portion of the first PGS1011 has a complete and continuous area, the inductor 1021 can generate only a small induced current in the central portion of the first PGS1011, which is almost negligible, so that the first PGS1011 can reduce the eddy current effect of the inductor and improve the inductance and the quality factor of the inductor. For further understanding, the shape of the first PGS1011 is further described below with reference to fig. 4, fig. 4 is a schematic diagram of the first PGS provided in the embodiment of the present application, as shown in fig. 4, the first PGS1011 may also be configured as a fence-like structure with central symmetry, in the fence-like first PGS1011, the main structure thereof is formed by two perpendicular first metal strips 10111, for convenience of description, a left side portion of one of the first metal strips 10111 is introduced, on the left side portion of the first metal strip 10111, three parallel second metal strips 10112 extend outwards, on the second metal strip 10112, a third metal strip 10113 extends outwards, and the third metal strip 10113 is perpendicular to the second metal strips 10112. Similarly, the right portion of the first metal strip 10111 and the other first metal strip 10111 have the same structure, and are not described in detail herein. Therefore, the first PGS1011 has a plurality of cutouts 1013, and the presence of the cutouts 1013 reduces the induced current generated by the inductor, thereby improving the inductance and the quality factor of the inductor.

It should be understood that the axisymmetric shapes of the inductor 1021 and the first PGS1011 illustrated in fig. 3 are only for illustrative purposes, and do not limit the shapes of the inductor 1021 and the first PGS1011 in the embodiment of the present application.

Between the inductor 1021 and the substrate 1022, a second PGS (not shown in fig. 2) is further disposed, and the second PGS may be made of polysilicon or the like, and may be configured to reduce an induced current caused by the inductor 1021 in the substrate 1022.

The package layer 101 further includes a first dielectric layer 1012 of package metal, and the chip 102 further includes a second dielectric layer 1023 covering the inductor 1021 and the second PGS. Specifically, the first dielectric layer 1012 is made of a first insulating material, and the second dielectric layer 1023 is made of a second insulating material, which is different from the first insulating material. For example, the first dielectric layer 1012 may be formed by epoxy and the second dielectric layer 1023 may be formed by silicon dioxide, so that the first dielectric layer 1012 and the second dielectric layer 1023 have a certain degree of distinction, thereby making the whole integrated circuit well-defined.

To make the structure of the whole integrated circuit more compact, the size of the packaging layer 101 is usually larger than or equal to the size of the chip 102.

In this embodiment, the first PGS1011 can not only reduce the induced current caused by the inductor 1021 in the package layer 101, but also make the package layer 101 become an effective grounded shielding layer when the first PGS1011 is grounded, so as to reduce the electromagnetic interference of the inductor 1021 to the external circuit, and also reduce the interference of the external circuit to the inductor 1021.

The foregoing is a detailed description of an integrated circuit provided in an embodiment of the present application, and the following describes a structure and a connection relationship of another integrated circuit provided in the embodiment of the present application, and fig. 5 is another schematic diagram of the integrated circuit provided in the embodiment of the present application, and as shown in fig. 5, the integrated circuit includes: the chip comprises an inductor, a variable capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. For convenience of explanation, fig. 5 shows only electronic devices such as an inductor, a variable capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor, and their connection relationships.

The packaging layer comprises packaging metal and a first dielectric layer, and the first dielectric layer is used for covering the packaging metal. The part of the metal conductor of the packaging metal opposite to the inductor is etched into a first PGS for reducing the induced current caused by the inductor in the packaging layer, and the rest of the technical conductor of the packaging metal can be etched into a certain-shaped wire for connecting the electronic devices.

Specifically, in the electronic device, a first end of the first transistor is connected to a first end of the variable capacitor, a first end of the second transistor is connected to a second end of the variable capacitor, a second end of the first transistor and a second end of the second transistor are both connected to the power supply, a third end of the first transistor is connected to a second end of the variable capacitor, a third end of the second transistor is connected to a first end of the variable capacitor, the variable capacitor and the capacitor are connected in parallel to the inductor, a first end of the third transistor is connected to a first end of the inductor, a first end of the fourth transistor is connected to a second end of the inductor, a second end of the third transistor and a second end of the fourth transistor are both grounded, a third end of the third transistor is connected to a second end of the inductor, and a third end of the fourth transistor is connected to a first end of the inductor. It should be noted that, in fig. 5, the left end of the variable capacitor is the second end, and the right end is the first end, and similarly, the left end of the inductor is the second end, and the right end is the first end.

Furthermore, the chip further comprises a second dielectric layer, wherein the second dielectric layer is used for covering the electronic devices such as the inductor, the variable capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor and the like, so that the electronic devices such as the inductor, the variable capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor and the like are arranged on the substrate of the chip.

Furthermore, a second PGS is disposed between the inductor and the substrate, the second PGS is used for reducing an induced current caused by the inductor in the substrate, and the second PGS is also covered by the second dielectric layer.

Furthermore, the first dielectric layer is made of a first insulating material, the second dielectric layer is made of a second insulating material, and the second insulating material is different from the first insulating material. For example, the first dielectric layer may be constructed from epoxy and the second dielectric layer may be constructed from silicon dioxide such that there is some degree of distinction between the first and second dielectric layers.

Further, the size of the encapsulation layer is typically larger than or equal to the size of the chip.

In this embodiment, when the voltage controlled oscillator is in an operating state, if the current in the inductor changes, due to the presence of the first PGS in the encapsulation layer, the induced current caused by the inductor in the encapsulation layer can be reduced, the eddy current effect of the inductor can be reduced, and the performance of the inductor can be improved.

For convenience of understanding, the voltage-controlled oscillator provided in the embodiments of the present application is further described below with reference to an application example, where the application example includes: the voltage-controlled oscillator provided by the embodiment of the application is a voltage-controlled oscillator a, the voltage-controlled oscillator constructed based on the integrated circuit provided in fig. 1 is a voltage-controlled oscillator B (that is, the voltage-controlled oscillator B is not provided with the first PGS), and the voltage-controlled oscillator a and the voltage-controlled oscillator B are subjected to simulation operation to obtain simulation results corresponding to the two voltage-controlled oscillators.

Fig. 6 is a graph of simulation results of inductance values provided in the examples of the present application, wherein in the coordinate system shown in fig. 6, the abscissa represents frequency in GHz, and the ordinate represents inductance values in pH. Fig. 7 is a graph of simulation results of inductance quality factor provided in the embodiment of the present application, and it should be noted that, in the coordinate system shown in fig. 7, the abscissa is frequency, the unit is GHz, and the ordinate is quality factor. As shown in fig. 6, curve 1 is the simulation curve of the inductance value of the vco a, and curve 2 is the simulation curve of the inductance value of the vco B. As shown in fig. 7, a curve 3 is an inductance quality factor simulation curve of the vco a, and a curve 4 is an inductance quality factor simulation curve of the vco B.

By comparing the simulation results, it can be known that the inductance value and the inductance quality factor of the inductor in the voltage-controlled oscillator a are better than those of the inductor in the voltage-controlled oscillator B because the first PGS is arranged in the voltage-controlled oscillator a. Based on the above simulation results, the frequency of the vco a is shifted by only about 2%, while the frequency of the vco B is shifted by 20% or more, and the noise performance of the vco a is better than that of the vco B because of the high quality factor of the inductor in the vco a.

Claims

An integrated circuit, comprising: a chip and an encapsulation layer for encapsulating the chip;

the chip comprises a substrate and an inductor arranged on the substrate;

the packaging layer comprises a first pattern ground shielding structure PGS, the first PGS is located on a metal layer in the packaging layer and formed by etching metal on the metal layer, the first PGS is located above the inductor, and the first PGS is used for reducing induced current of the inductor in the metal layer.
The integrated circuit of claim 1, wherein the first PGS has a notch, the notch configured to reduce the induced current.
The integrated circuit of claim 1 or 2, wherein the first PGS is directly opposite to the inductor.
The integrated circuit of any of claims 1-3, wherein a second PGS is disposed between the inductor and the substrate, the second PGS configured to reduce the induced current induced in the substrate by the inductor.
The integrated circuit of claim 4, wherein the second PGS is comprised of polysilicon.
The integrated circuit of claim 5, wherein the encapsulation layer further comprises a first dielectric layer overlying the first PGS.
The integrated circuit of claim 6, wherein the chip further comprises a second dielectric layer covering the inductor and the second PGS.
The integrated circuit of claim 7, wherein the first dielectric layer is comprised of a first insulating material.
The integrated circuit of claim 8, wherein the second dielectric layer is comprised of a second insulating material that is a different insulating material than the first insulating material.
The integrated circuit of any of claims 1-9, wherein the size of the encapsulation layer is greater than or equal to the size of the chip.
An integrated circuit, comprising: the chip comprises a chip and an encapsulation layer for encapsulating the chip;

the chip comprises a voltage-controlled oscillator, wherein the voltage-controlled oscillator comprises an inductor, a variable capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor;

a first terminal of the first transistor is connected to a first terminal of the variable capacitor, a first terminal of the second transistor is connected to a second terminal of the variable capacitor, the second end of the first transistor and the second end of the second transistor are both connected with a power supply, the third end of the first transistor is connected with the second end of the variable capacitor, the third end of the second transistor is connected with the first end of the variable capacitor, the variable capacitor and the capacitor are connected with the inductor in parallel, a first terminal of the third transistor is connected to a first terminal of the inductor, a first terminal of the fourth transistor is connected to a second terminal of the inductor, a second end of the third transistor and a second end of the fourth transistor are both grounded, a third end of the third transistor is connected with a second end of the inductor, and a third end of the fourth transistor is connected with a first end of the inductor;

The packaging layer comprises a first PGS, the first PGS is formed by etching packaging metal in the packaging layer, and the first PGS is used for reducing induction current caused by the inductor in the packaging layer.
The integrated circuit of claim 11, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all metal-oxide semiconductor field effect transistors (MOSFETs) or Bipolar Junction Transistors (BJTs).