WO2021102940A1 - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
WO2021102940A1
WO2021102940A1 PCT/CN2019/122063 CN2019122063W WO2021102940A1 WO 2021102940 A1 WO2021102940 A1 WO 2021102940A1 CN 2019122063 W CN2019122063 W CN 2019122063W WO 2021102940 A1 WO2021102940 A1 WO 2021102940A1
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Prior art keywords
transistor
inductor
pgs
integrated circuit
terminal
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PCT/CN2019/122063
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French (fr)
Chinese (zh)
Inventor
黄继超
闵卿
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980102524.2A priority Critical patent/CN114762108A/en
Priority to PCT/CN2019/122063 priority patent/WO2021102940A1/en
Publication of WO2021102940A1 publication Critical patent/WO2021102940A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • the embodiments of the present application relate to the field of electronic circuits, and in particular to an integrated circuit.
  • Integrated circuits with miniature size and low power consumption can integrate electronic components, such as capacitors, inductors, resistors and other module circuits to achieve the purpose of reducing costs, and can be widely used in wireless communication modules, portable communication equipment, etc. .
  • Fig. 1 is a schematic structural diagram of a traditional integrated circuit.
  • the integrated circuit includes a packaging layer and a chip, wherein the chip includes a substrate and an inductor provided on the substrate.
  • the inductor When the inductor is in working condition, due to the change of the current in the inductor, a large induced current (ie eddy current) will be generated in the metal conductor in the package layer, which will affect the inductance value and quality factor of the inductor, and cause the performance of the inductor to decrease.
  • the embodiment of the present application provides an integrated circuit, which can reduce the eddy current effect of the inductor and improve the performance of the inductor.
  • the first aspect of the embodiments of the present application provides an integrated circuit, which includes: a chip and a packaging layer for packaging the chip.
  • the chip includes a substrate and an inductor provided on the substrate
  • the packaging layer includes a first patterned ground shield (PGS)
  • the first PGS is located in the metal layer in the packaging layer
  • the first PGS is made of metal
  • the metal on the layer is etched
  • the first PGS is located on the inductor.
  • the first PGS is used to reduce the induced current caused by the inductor in the metal layer.
  • the packaging layer includes packaging metal, and a part of the packaging metal is etched into the first PGS, and the first PGS is located on the inductor.
  • the first PGS in the first implementation of the first aspect of the embodiments of the present application, can be etched into a shape with multiple cuts, and each cut can be used to destroy the induced current.
  • the path of the first PGS can reduce the induced current caused by the inductance in the packaging layer.
  • the first PGS in the encapsulation layer is positive
  • the eddy current effect of the inductor can be further reduced.
  • a second PGS is provided between the inductor and the substrate, and the second PGS is used to reduce the induced current caused by the inductor in the substrate, and can further improve the performance of the inductor.
  • the second PGS is composed of polysilicon.
  • the encapsulation layer further includes a first dielectric layer, and the first dielectric layer is used to cover The packaging metal is equivalent to covering the first PGS.
  • the chip further includes a second dielectric layer, and the second dielectric layer is used to cover the inductor And the second PGS.
  • the first dielectric layer is composed of a first insulating material, so that the packaging layer has a good Package function.
  • the second dielectric layer is composed of a second insulating material.
  • the first insulating material is a different insulating material, so there is a certain degree of difference between the first dielectric layer and the second dielectric layer, which further makes the entire integrated circuit level distinct.
  • the size of the packaging layer is generally greater than or equal to the size of the chip, so that the structure of the entire integrated circuit is more compact.
  • a second aspect of the embodiments of the present application provides an integrated circuit.
  • the integrated circuit includes a chip and a packaging layer for packaging the chip.
  • the chip includes a voltage-controlled oscillator.
  • the voltage-controlled oscillator includes an inductor, a variable capacitor, and a capacitor. , The first transistor, the second transistor, the third transistor and the fourth transistor.
  • the first end of the first transistor is connected to the first end of the variable capacitor, the first end of the second transistor is connected to the second end of the variable capacitor, and the second end of the first transistor and the second end of the second transistor are both Connected to the power supply, the third terminal of the first transistor is connected to the second terminal of the variable capacitor, the third terminal of the second transistor is connected to the first terminal of the variable capacitor, the variable capacitor, the capacitor and the inductor are connected in parallel, and the third transistor
  • the first end of the fourth transistor is connected to the first end of the inductor, the first end of the fourth transistor is connected to the second end of the inductor, the second end of the third transistor and the second end of the fourth transistor are both grounded, and the first end of the third transistor The three ends are connected to the second end of the inductor, and the third end of the fourth transistor is connected to the first end of the inductor;
  • the packaging layer includes a first PGS.
  • the first PGS is etched based on the packaging metal in the packaging layer, and the first PGS faces the inductor, and the first PGS is used to reduce the induced current caused by the inductor in the packaging layer.
  • the performance of the inductor can be improved, thereby reducing the frequency offset of the voltage-controlled oscillator and improving the noise performance of the voltage-controlled oscillator.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all metal-oxide semiconductor fields.
  • the metal-oxide-semiconductor field-effect transistor (MOSFET) or bipolar junction transistor (BJT) improves the flexibility and selectivity of the solution.
  • the integrated circuit provided by the embodiment of the present application includes: a chip and a packaging layer for packaging the chip.
  • the chip includes a substrate and an inductor provided on the substrate
  • the packaging layer includes a first PGS
  • the first PGS is located in the metal layer in the packaging layer
  • the first PGS is formed by etching the metal on the metal layer
  • the first PGS is formed by etching the metal on the metal layer.
  • a PGS is located above the inductor, and the first PGS is used to reduce the induced current in the metal layer caused by the inductor.
  • the induced current generated by the changing current in the inductance in the first PGS is very small, which can reduce the eddy current effect of the electronic component and improve the performance of the electronic component.
  • Figure 1 is a schematic diagram of the structure of a traditional integrated circuit
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application.
  • FIG. 3 is another schematic diagram of an integrated circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the first PGS provided by an embodiment of the application.
  • FIG. 5 is another schematic diagram of an integrated circuit provided by an embodiment of the application.
  • FIG. 6 is a simulation result diagram of the inductance value provided by an embodiment of the application.
  • FIG. 7 is a simulation result diagram of the inductor quality factor provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application. Please refer to FIG. 2.
  • the integrated circuit includes: a chip 102 and an encapsulation layer 101, and the encapsulation layer 101 is used to encapsulate the chip 102.
  • the chip 102 includes a substrate 1022 and an inductor 1021 disposed on the substrate 1022.
  • the packaging layer 101 includes a metal layer. A part of the metal is etched into the first PGS 1011, and the first PGS 1011 is located on the inductor 1021. The PGS1011 is used to reduce the induced current caused by the inductor 1021 in the packaging layer 101.
  • the first PGS1011 is usually set above the inductor 1021, that is, the first PGS1011 and the inductor 1021 are set in an opposite state. Specifically, the first PGS1011 can cover the inductor 1021, or it can slightly deviate from the inductor 1021. In order to make the function of the first PGS1011 better, the first PGS1011 in the packaging layer 101 can be made to face the inductor 1021, that is, the first PGS1011 is located directly above the inductor 1021, and when the inductor 1021 is in operation In the state, due to the existence of the first PGS 1011, the induced current in the first PGS 1011 generated by the changing current on the inductor 1021 is small. Therefore, the first PGS 1011 can reduce the eddy current effect of the inductor 103 and improve the performance of the inductor 1021.
  • the first PGS 1011 is etched based on the packaging metal in the packaging layer 101.
  • the part of the metal conductor facing the inductor 1021 can be selected from the packaging metal to be etched to obtain the first PGS 1011 of a specific shape.
  • the shape of the first PGS1011 is usually etched into a fence-like shape, that is, the first PGS1011 has multiple cuts. Compared with a metal conductor with a complete area, each cut provided by the first PGS1011 can be used to destroy the induced current.
  • the path that is, the path that generates the induced current is cut off, so the first PGS 1011 can reduce the induced current caused by the inductor 1021 in the packaging layer 101.
  • the first PGS 1011 can also be etched into a symmetrical fence-like shape or an asymmetrical fence-like shape, which can be set according to the actual shape of the inductor 1021.
  • the shape of the first PGS 1011 will be further described below in conjunction with FIG. 3.
  • FIG. 3 is another schematic diagram of an integrated circuit provided by an embodiment of the application. As shown in FIG. The shape is a zigzag and axisymmetric strip shape, so the first PGS1011 can also be set in an axisymmetrical fence-like shape.
  • the main structure consists of a first metal strip 10111 and three parallel bars.
  • the second metal strip 10112 is composed of the first metal strip 10111 and the three second metal strips 10112 perpendicular to each other. Therefore, the main structure has four right-angle extensions, and each right-angle extension is provided with a secondary structure.
  • the third metal strip 10113 is provided with the fourth metal strip 10114 extending outward based on the third metal strip 10113. Therefore, the first PGS 1011 has a plurality of cutouts 1013. Due to the existence of these cutouts 1013, the first PGS1011 has only the central part of the area which is complete and continuous. Therefore, the inductor 1021 can only generate a small induced current in the central part of the first PGS1011, which is almost negligible.
  • FIG. 4 is a schematic diagram of the first PGS provided by an embodiment of the application. As shown in FIG. 4, the first PGS 1011 can also be set as A centrally symmetrical fence-like shape. In the first PGS1011 of this kind of fence-like shape, the main structure is composed of two first metal strips 10111 perpendicular to each other.
  • the first PGS 1011 has a plurality of cutouts 1013. Due to the existence of these cutouts 1013, the induced current generated by the inductor can be reduced, and the inductance value and quality factor of the inductor can be improved.
  • the axisymmetric shapes of the inductor 1021 and the first PGS 1011 shown in FIG. 3 are merely illustrative, and do not limit the shapes of the inductor 1021 and the first PGS 1011 in the embodiment of the present application.
  • the second PGS can be made of polysilicon and other materials, which can be used to reduce the induced current caused by the inductor 1021 in the substrate 1022. .
  • the packaging layer 101 further includes a first dielectric layer 1012 of packaging metal
  • the chip 102 further includes a second dielectric layer 1023 covering the inductor 1021 and the second PGS.
  • the first dielectric layer 1012 is made of a first insulating material
  • the second dielectric layer 1023 is made of a second insulating material
  • the second insulating material and the first insulating material are different insulating materials.
  • the first dielectric layer 1012 can be constructed by epoxy resin
  • the second dielectric layer 1023 can be constructed by silicon dioxide, so that the first dielectric layer 1012 and the second dielectric layer 1023 have a certain degree of difference, and the entire integrated circuit level distinct.
  • the size of the packaging layer 101 is generally greater than or equal to the size of the chip 102.
  • the first PGS1011 can not only reduce the induced current caused by the inductance 1021 in the packaging layer 101, when the first PGS1011 is grounded, it can also make the packaging layer 101 an effective grounding shielding layer, which can reduce the inductance 1021.
  • the electromagnetic interference of the external circuit can also reduce the interference of the external circuit to the inductor 1021.
  • FIG. 5 is a schematic diagram of the integrated circuit provided in an embodiment of the application.
  • the integrated circuit includes: a chip and a packaging layer for packaging the chip, wherein the chip includes a voltage-controlled oscillator, the voltage-controlled oscillator includes an inductor, a variable capacitor, a capacitor, a first Transistor, second transistor, third transistor, and fourth transistor.
  • the voltage-controlled oscillator includes an inductor, a variable capacitor, a capacitor, a first Transistor, second transistor, third transistor, and fourth transistor.
  • FIG. 5 only shows electronic devices such as inductors, variable capacitors, capacitors, first transistors, second transistors, third transistors, and fourth transistors, and their connection relationships.
  • the packaging layer includes a packaging metal and a first dielectric layer, and the first dielectric layer is used to cover the packaging metal.
  • the packaging metal is etched into the first PGS for this part of the metal conductor of the inductor, which is used to reduce the induced current caused by the inductor in the packaging layer.
  • the remaining part of the technical conductor of the packaging metal can be etched into a trace with a certain shape. Used to connect the above-mentioned electronic devices.
  • the first terminal of the first transistor is connected to the first terminal of the variable capacitor
  • the first terminal of the second transistor is connected to the second terminal of the variable capacitor
  • the second terminal of the first transistor The second end of the second transistor is connected to the power supply
  • the third end of the first transistor is connected to the second end of the variable capacitor
  • the third end of the second transistor is connected to the first end of the variable capacitor.
  • the variable capacitor The capacitor is connected in parallel with the inductor, the first end of the third transistor is connected to the first end of the inductor, the first end of the fourth transistor is connected to the second end of the inductor, the second end of the third transistor, the second end of the fourth transistor The terminals are all grounded, the third terminal of the third transistor is connected to the second terminal of the inductor, and the third terminal of the fourth transistor is connected to the first terminal of the inductor. It should be noted that in FIG. 5, the left end of the variable capacitor is the second end, and the right end is the first end. Similarly, the left end of the inductor is the second end, and the right end is the first end.
  • the chip also includes a second dielectric layer, and the second dielectric layer is used to cover electronic devices such as inductors, variable capacitors, capacitors, first transistors, second transistors, third transistors, and fourth transistors, so that the Electronic devices such as capacitors, capacitors, first transistors, second transistors, third transistors and fourth transistors are arranged on the substrate of the chip.
  • electronic devices such as inductors, variable capacitors, capacitors, first transistors, second transistors, third transistors, and fourth transistors, so that the Electronic devices such as capacitors, capacitors, first transistors, second transistors, third transistors and fourth transistors are arranged on the substrate of the chip.
  • a second PGS is provided between the inductor and the substrate, and the second PGS is used to reduce the induced current caused by the inductor in the substrate, and the second PGS is also covered by the second dielectric layer.
  • the first dielectric layer is composed of a first insulating material
  • the second dielectric layer is composed of a second insulating material
  • the second insulating material and the first insulating material are different insulating materials.
  • the first dielectric layer can be constructed by epoxy resin
  • the second dielectric layer can be constructed by silica, so that there is a certain degree of difference between the first dielectric layer and the second dielectric layer.
  • the size of the encapsulation layer is generally greater than or equal to the size of the chip.
  • the induced current caused by the inductor in the packaging layer can be reduced, and the inductance can be reduced.
  • the eddy current effect improves the performance of the inductor.
  • the application example includes: suppose the voltage-controlled oscillator provided by the embodiment of the present application is a voltage-controlled oscillator A, based on FIG. 1
  • the voltage-controlled oscillator constructed by the provided integrated circuit is the voltage-controlled oscillator B (that is, the voltage-controlled oscillator B is not set with the first PGS), and the voltage-controlled oscillator A and the voltage-controlled oscillator B are simulated to run The simulation results corresponding to the two voltage-controlled oscillators are obtained.
  • Fig. 6 is a simulation result diagram of the inductance value provided by the embodiment of the application. It should be noted that, in the coordinate system shown in Fig. 6, the abscissa is frequency and the unit is GHz, and the ordinate is the inductance value and the unit is pH.
  • FIG. 7 is a graph of simulation results of the inductor quality factor provided by an embodiment of the application. It should be noted that, in the coordinate system shown in FIG. 7, the abscissa is frequency, the unit is GHz, and the ordinate is the quality factor. As shown in Fig. 6, curve 1 is the simulation curve of the inductance value of the voltage-controlled oscillator A, and curve 2 is the simulation curve of the inductance value of the voltage-controlled oscillator B. As shown in FIG. 7, curve 3 is a simulation curve of the inductance quality factor of the voltage-controlled oscillator A, and curve 4 is a simulation curve of the inductance quality factor of the voltage-controlled oscillator B.
  • the inductance value and the inductance quality factor of the inductor in the voltage-controlled oscillator A are better than the inductance value and inductance of the inductor in the voltage-controlled oscillator B Quality factor.
  • the frequency of the voltage-controlled oscillator A only shifts by approximately 2%, while the frequency of the voltage-controlled oscillator B will shift by more than 20%.
  • the quality factor of the inductance of the voltage-controlled oscillator A Higher so the noise performance of voltage controlled oscillator A is also better than that of voltage controlled oscillator B.

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Abstract

An integrated circuit comprises a chip (102) and a packaging layer (101) for packaging the chip (102). The chip (102) comprises a substrate (1022) and an inductor (1021) provided on the substrate (1022). The packaging layer (101) comprises a first patterned ground shield structure (1011) located on a metal layer in the packaging layer (101). The first patterned ground shield structure (1011) is formed by etching metal the metal layer, and is located above the inductor (1021). The first patterned ground shield structure (1011) is used to reduce an induced current in the metal layer caused by the inductor (1021). When the inductor (1021) is in an operating state, the first patterned ground shield structure (1011) enables a small induced current in the first patterned ground shield structure (1011) generated by a changing current on the inductor (1021), thereby reducing the eddy current effect of an electronic element, and improving the performance thereof.

Description

一种集成电路An integrated circuit 技术领域Technical field
本申请实施例涉及电子电路领域，尤其涉及一种集成电路。The embodiments of the present application relate to the field of electronic circuits, and in particular to an integrated circuit.
背景技术Background technique
具备微型体积、低耗电特点的集成电路，可将电子元件，例如电容、电感、电阻等各种模块电路集成，以达到降低成本等目的，可广泛应用于无线通信模块、便携式通讯设备等等。Integrated circuits with miniature size and low power consumption can integrate electronic components, such as capacitors, inductors, resistors and other module circuits to achieve the purpose of reducing costs, and can be widely used in wireless communication modules, portable communication equipment, etc. .
图1为传统集成电路的一个结构示意图，如图1所示，该集成电路包括封装层和芯片，其中，芯片包括衬底和设于衬底之上的电感。当电感处于工作状态时，由于电感中的电流发生变化，会在封装层中的金属导体产生较大的感应电流(即涡流)，进而影响电感的电感值和品质因数，导致电感的性能下降。Fig. 1 is a schematic structural diagram of a traditional integrated circuit. As shown in Fig. 1, the integrated circuit includes a packaging layer and a chip, wherein the chip includes a substrate and an inductor provided on the substrate. When the inductor is in working condition, due to the change of the current in the inductor, a large induced current (ie eddy current) will be generated in the metal conductor in the package layer, which will affect the inductance value and quality factor of the inductor, and cause the performance of the inductor to decrease.
发明内容Summary of the invention
本申请实施例提供了一种集成电路，能够减小电感的涡流效应，提高电感的性能。The embodiment of the present application provides an integrated circuit, which can reduce the eddy current effect of the inductor and improve the performance of the inductor.
本申请实施例的第一方面提供一种集成电路，该集成电路包括：芯片和用于封装所述芯片的封装层。其中，芯片包括衬底和设于衬底之上的电感，封装层包括第一图案接地屏蔽结构(patterned ground shield，PGS)，第一PGS位于封装层内的金属层，第一PGS为由金属层上的金属刻蚀而成，且第一PGS位于电感之上，第一PGS用于减少电感在金属层中引起的感应电流。The first aspect of the embodiments of the present application provides an integrated circuit, which includes: a chip and a packaging layer for packaging the chip. Wherein, the chip includes a substrate and an inductor provided on the substrate, the packaging layer includes a first patterned ground shield (PGS), the first PGS is located in the metal layer in the packaging layer, and the first PGS is made of metal The metal on the layer is etched, and the first PGS is located on the inductor. The first PGS is used to reduce the induced current caused by the inductor in the metal layer.
在上述集成电路中，封装层中包括封装金属，其中一部分封装金属被刻蚀成第一PGS，且该第一PGS位于电感之上。当芯片中的电感处于工作状态时，由于第一PGS的存在，能够减少电感在封装层中引起的感应电流，可以减小电感的涡流效应，提高电感的性能。In the above-mentioned integrated circuit, the packaging layer includes packaging metal, and a part of the packaging metal is etched into the first PGS, and the first PGS is located on the inductor. When the inductor in the chip is in the working state, due to the existence of the first PGS, the induced current caused by the inductor in the packaging layer can be reduced, the eddy current effect of the inductor can be reduced, and the performance of the inductor can be improved.
结合本申请实施例的第一方面，在本申请实施例的第一方面的第一种实现方式中，第一PGS可被刻蚀成具有多个切口的形状，每一个切口可用于破坏感应电流的路径，使得第一PGS能够减少电感在封装层中引起的感应电流。In combination with the first aspect of the embodiments of the present application, in the first implementation of the first aspect of the embodiments of the present application, the first PGS can be etched into a shape with multiple cuts, and each cut can be used to destroy the induced current. The path of the first PGS can reduce the induced current caused by the inductance in the packaging layer.
结合本申请实施例的第一方面或本申请实施例的第一方面的第一种实现方式，在本申请实施例的第一方面的第二种实现方式中，封装层中的第一PGS正对电感，通过设置第一PGS与电感之间的相对位置，可以进一步减小电感的涡流效应。In combination with the first aspect of the embodiments of the present application or the first implementation of the first aspect of the embodiments of the present application, in the second implementation of the first aspect of the embodiments of the present application, the first PGS in the encapsulation layer is positive For the inductor, by setting the relative position between the first PGS and the inductor, the eddy current effect of the inductor can be further reduced.
结合本申请实施例的第一方面，本申请实施例的第一方面的第一种实现方式或本申请实施例第一方面的第二种实现方式，在本申请实施例的第一方面的第三种实现方式中，电感与衬底之间设置有第二PGS，第二PGS用于减少电感在所述衬底中引起的感应电流，能够进一步提高电感的性能。With reference to the first aspect of the embodiments of the present application, the first implementation of the first aspect of the embodiments of the present application or the second implementation of the first aspect of the embodiments of the present application, in the first aspect of the first aspect of the embodiments of the present application In the three implementation manners, a second PGS is provided between the inductor and the substrate, and the second PGS is used to reduce the induced current caused by the inductor in the substrate, and can further improve the performance of the inductor.
结合本申请实施例的第一方面的第三种实现方式，在本申请实施例的第一方面的第四种实现方式中，第二PGS由多晶硅构成。With reference to the third implementation manner of the first aspect of the embodiments of the present application, in the fourth implementation manner of the first aspect of the embodiments of the present application, the second PGS is composed of polysilicon.
结合本申请实施例的第一方面的第四种实现方式，在本申请实施例的第一方面的第五种实现方式中，封装层还包括第一介质层，该第一介质层用于覆盖封装金属，即相当于覆盖第一PGS。With reference to the fourth implementation manner of the first aspect of the embodiments of the present application, in the fifth implementation manner of the first aspect of the embodiments of the present application, the encapsulation layer further includes a first dielectric layer, and the first dielectric layer is used to cover The packaging metal is equivalent to covering the first PGS.
结合本申请实施例的第一方面的第五种实现方式，在本申请实施例的第一方面的第六种实现方式中，芯片还包括第二介质层，该第二介质层用于覆盖电感和第二PGS。With reference to the fifth implementation manner of the first aspect of the embodiments of the present application, in the sixth implementation manner of the first aspect of the embodiments of the present application, the chip further includes a second dielectric layer, and the second dielectric layer is used to cover the inductor And the second PGS.
结合本申请实施例的第一方面的第六种实现方式，在本申请实施例的第一方面的第七种实现方式中，第一介质层由第一绝缘材料构成，使得封装层具备良好的封装功能。In combination with the sixth implementation manner of the first aspect of the embodiments of the present application, in the seventh implementation manner of the first aspect of the embodiments of the present application, the first dielectric layer is composed of a first insulating material, so that the packaging layer has a good Package function.
结合本申请实施例的第一方面的第七种实现方式，在本申请实施例的第一方面的第八种实现方式中，第二介质层由第二绝缘材料构成，由于第二绝缘材料与第一绝缘材料为不同的绝缘材料，故第一介质层和第二介质层存在一定的区别度，进而令整个集成电路层次分明。With reference to the seventh implementation manner of the first aspect of the embodiments of the present application, in the eighth implementation manner of the first aspect of the embodiments of the present application, the second dielectric layer is composed of a second insulating material. The first insulating material is a different insulating material, so there is a certain degree of difference between the first dielectric layer and the second dielectric layer, which further makes the entire integrated circuit level distinct.
结合本申请实施例的第一方面，本申请实施例的第一方面的第一种实现方式至本申请实施例的第一方面的第八种实现方式中的任意一种，在本申请实施例的第一方面的第九种实现方式中，封装层的尺寸通常大于或等于芯片的尺寸，以使得整个集成电路的结构更加紧凑。With reference to the first aspect of the embodiments of the present application, any one of the first implementation manner of the first aspect of the embodiments of the present application to the eighth implementation manner of the first aspect of the embodiments of the present application is described in the embodiments of the present application. In the ninth implementation manner of the first aspect, the size of the packaging layer is generally greater than or equal to the size of the chip, so that the structure of the entire integrated circuit is more compact.
本申请实施例第二方面提供了一种集成电路，该集成电路包括芯片和用于封装芯片的封装层，该芯片包括压控振荡器，该压控振荡器包括：电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管。A second aspect of the embodiments of the present application provides an integrated circuit. The integrated circuit includes a chip and a packaging layer for packaging the chip. The chip includes a voltage-controlled oscillator. The voltage-controlled oscillator includes an inductor, a variable capacitor, and a capacitor. , The first transistor, the second transistor, the third transistor and the fourth transistor.
第一晶体管的第一端与可变电容的第一端连接，第二晶体管的第一端与可变电容的第二端连接，第一晶体管的第二端、第二晶体管的第二端均与电源连接，第一晶体管的第三端与可变电容的第二端连接，第二晶体管的第三端与可变电容的第一端连接，可变电容、电容与电感并联，第三晶体管的第一端与电感的第一端连接，第四晶体管的第一端与电感的第二端连接，第三晶体管的第二端、第四晶体管的第二端均接地，第三晶体管的第三端与电感的第二端连接，第四晶体管的第三端与电感的第一端连接；The first end of the first transistor is connected to the first end of the variable capacitor, the first end of the second transistor is connected to the second end of the variable capacitor, and the second end of the first transistor and the second end of the second transistor are both Connected to the power supply, the third terminal of the first transistor is connected to the second terminal of the variable capacitor, the third terminal of the second transistor is connected to the first terminal of the variable capacitor, the variable capacitor, the capacitor and the inductor are connected in parallel, and the third transistor The first end of the fourth transistor is connected to the first end of the inductor, the first end of the fourth transistor is connected to the second end of the inductor, the second end of the third transistor and the second end of the fourth transistor are both grounded, and the first end of the third transistor The three ends are connected to the second end of the inductor, and the third end of the fourth transistor is connected to the first end of the inductor;
封装层包括第一PGS，第一PGS为基于封装层内的封装金属刻蚀而成的，且第一PGS正对电感，第一PGS用于减少电感在封装层中引起的感应电流。The packaging layer includes a first PGS. The first PGS is etched based on the packaging metal in the packaging layer, and the first PGS faces the inductor, and the first PGS is used to reduce the induced current caused by the inductor in the packaging layer.
在上述压控振荡器中，由于封装层中第一PGS的存在，可以提高电感的性能，进而能够降低压控振荡器的频率偏移，并且提高压控振荡器的噪声性能。In the above-mentioned voltage-controlled oscillator, due to the existence of the first PGS in the packaging layer, the performance of the inductor can be improved, thereby reducing the frequency offset of the voltage-controlled oscillator and improving the noise performance of the voltage-controlled oscillator.
结合本申请实施例的第二方面，在本申请实施例的第二方面的第一种实现方式中，第一晶体管、第二晶体管、第三晶体管和第四晶体管均为金属-氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistor，MOSFET)或双极结型晶体管(bipolar junction transistor，BJT),提高了方案的灵活度和可选择性。With reference to the second aspect of the embodiments of the present application, in the first implementation of the second aspect of the embodiments of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor are all metal-oxide semiconductor fields. The metal-oxide-semiconductor field-effect transistor (MOSFET) or bipolar junction transistor (BJT) improves the flexibility and selectivity of the solution.
本申请实施例提供的集成电路包括：芯片和用于封装所述芯片的封装层。其中，芯片包括衬底和设于衬底之上的电感，封装层包括第一PGS，第一PGS位于封装层内的金属层，第一PGS由金属层上的金属刻蚀而成，且第一PGS位于电感之上，第一PGS用于减少电感在金属层中引起的感应电流。当电感处于工作状态时，由于第一PGS的存在，电感上变化的电流在第一PGS中所产生的感应电流很小，能够减小电子元件的涡流效应，提高电子元件的性能。The integrated circuit provided by the embodiment of the present application includes: a chip and a packaging layer for packaging the chip. Wherein, the chip includes a substrate and an inductor provided on the substrate, the packaging layer includes a first PGS, the first PGS is located in the metal layer in the packaging layer, the first PGS is formed by etching the metal on the metal layer, and the first PGS is formed by etching the metal on the metal layer. A PGS is located above the inductor, and the first PGS is used to reduce the induced current in the metal layer caused by the inductor. When the inductor is in the working state, due to the existence of the first PGS, the induced current generated by the changing current in the inductance in the first PGS is very small, which can reduce the eddy current effect of the electronic component and improve the performance of the electronic component.
附图说明Description of the drawings
图1为为传统集成电路的一个结构示意图；Figure 1 is a schematic diagram of the structure of a traditional integrated circuit;
图2为本申请实施例提供的集成电路的一个结构示意图；FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application;
图3为本申请实施例提供的集成电路的另一个示意图；FIG. 3 is another schematic diagram of an integrated circuit provided by an embodiment of the application;
图4为本申请实施例提供的第一PGS的一个示意图；FIG. 4 is a schematic diagram of the first PGS provided by an embodiment of the application;
图5为本申请实施例提供的集成电路的另一个示意图；FIG. 5 is another schematic diagram of an integrated circuit provided by an embodiment of the application;
图6为本申请实施例提供的电感值的仿真结果图；FIG. 6 is a simulation result diagram of the inductance value provided by an embodiment of the application;
图7为本申请实施例提供的电感品质因数的仿真结果图。FIG. 7 is a simulation result diagram of the inductor quality factor provided by an embodiment of the application.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行详细描述。The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.
图2为本申请实施例提供的集成电路的一个结构示意图，请参阅图2，该集成电路包括：芯片102和封装层101，封装层101用于封装芯片102。其中，芯片102包括衬底1022和设于衬底1022之上的电感1021，封装层101包括金属层，其中一部分金属被刻蚀成第一PGS1011，且第一PGS1011位于电感1021之上，第一PGS1011用于减少电感1021在封装层101中引起的感应电流。FIG. 2 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application. Please refer to FIG. 2. The integrated circuit includes: a chip 102 and an encapsulation layer 101, and the encapsulation layer 101 is used to encapsulate the chip 102. Wherein, the chip 102 includes a substrate 1022 and an inductor 1021 disposed on the substrate 1022. The packaging layer 101 includes a metal layer. A part of the metal is etched into the first PGS 1011, and the first PGS 1011 is located on the inductor 1021. The PGS1011 is used to reduce the induced current caused by the inductor 1021 in the packaging layer 101.
值得注意的是，第一PGS1011通常设在电感1021的上方，即第一PGS1011与电感1021呈相对的状态进行设置，具体的，第一PGS1011可以覆盖电感1021，也可以稍微偏离电感1021，且二者具有一定的重叠面积等等，为了使第一PGS1011的功能更优，可以令封装层101中的第一PGS1011正对电感1021，即第一PGS1011位于电感1021的正上方，当电感1021处于工作状态时，由于第一PGS1011的存在，电感1021上变化的电流在第一PGS1011中所产生的感应电流很小，因此，第一PGS1011能够减小电感103的涡流效应，提高电感1021的性能。It is worth noting that the first PGS1011 is usually set above the inductor 1021, that is, the first PGS1011 and the inductor 1021 are set in an opposite state. Specifically, the first PGS1011 can cover the inductor 1021, or it can slightly deviate from the inductor 1021. In order to make the function of the first PGS1011 better, the first PGS1011 in the packaging layer 101 can be made to face the inductor 1021, that is, the first PGS1011 is located directly above the inductor 1021, and when the inductor 1021 is in operation In the state, due to the existence of the first PGS 1011, the induced current in the first PGS 1011 generated by the changing current on the inductor 1021 is small. Therefore, the first PGS 1011 can reduce the eddy current effect of the inductor 103 and improve the performance of the inductor 1021.
第一PGS1011为基于封装层101中的封装金属所刻蚀而成的，例如，可从封装金属中，选择正对电感1021的这一部分金属导体进行刻蚀，进而得到特定形状的第一PGS1011。此外，第一PGS1011的形状通常被刻蚀成类栅栏状，即第一PGS1011具有多个切口，相较于具有完整面积的金属导体，第一PGS1011所具备的每个切口可用于破坏感应电流的路径，即切断产生感应电流的路径，故第一PGS1011能够减少电感1021在封装层101中引起的感应电流。The first PGS 1011 is etched based on the packaging metal in the packaging layer 101. For example, the part of the metal conductor facing the inductor 1021 can be selected from the packaging metal to be etched to obtain the first PGS 1011 of a specific shape. In addition, the shape of the first PGS1011 is usually etched into a fence-like shape, that is, the first PGS1011 has multiple cuts. Compared with a metal conductor with a complete area, each cut provided by the first PGS1011 can be used to destroy the induced current. The path, that is, the path that generates the induced current is cut off, so the first PGS 1011 can reduce the induced current caused by the inductor 1021 in the packaging layer 101.
进一步地，第一PGS1011还可以被刻蚀成对称的类栅栏状或非对称的类栅栏状，可以根据电感1021的实际形状进行相应的设置。为了便于理解，以下结合图3对第一PGS1011的形状作进一步的说明，图3为本申请实施例提供的集成电路的另一个示意图，如图3所示，在该集成电路中，电感1021的形状为曲折且轴对称的条形状，故第一PGS1011也可以设置为轴对称的类栅栏状，该类栅栏状的第一PGS1011中，其主结构由一根第一金属条10111和三根平行的第二金属条10112构成，第一金属条10111与三根第二金属条10112垂直，故主结构具有四个直角延伸处，每个直角延伸处设置有一个次结构，每个次结构由一根倾斜设置的第三金属条10113，与以第三金属条10113为基础，向外延伸的第四金属条10114所构成，因此，第一PGS1011具有多个切口1013，由于这些切口1013的存在，第一PGS1011仅有中心部分的面积为完整且连续的，故电感1021仅能在第一PGS1011的中心部分产生很小的感应电流，几乎可以忽略不计，故第一PGS1011能够减小电感的涡流效 应，提高电感的电感值和品质因数。为了进一步的理解，以下结合图4对第一PGS1011的形状作更进一步的说明，图4为本申请实施例提供的第一PGS的一个示意图，如图4所示，第一PGS1011还可以设置为中心对称的类栅栏状，该类栅栏状的第一PGS1011中，其主结构由两根相垂直第一金属条10111构成，为方便说明，以其中一根第一金属条10111的左侧部分进行介绍，在该第一金属条10111的左侧部分上，向外延伸有三根平行的第二金属条10112，且在第二根第二金属条10112上，向外延伸有一根第三金属条10113，且第三金属条10113与第二金属条10112垂直。同理，该第一金属条10111的右侧部分以及另一根第一金属条10111具有相同的结构，此处不再赘述。因此，第一PGS1011具有多个切口1013，由于这些切口1013的存在，能够减少电感所产生的感应电流，提高电感的电感值和品质因数。Further, the first PGS 1011 can also be etched into a symmetrical fence-like shape or an asymmetrical fence-like shape, which can be set according to the actual shape of the inductor 1021. For ease of understanding, the shape of the first PGS 1011 will be further described below in conjunction with FIG. 3. FIG. 3 is another schematic diagram of an integrated circuit provided by an embodiment of the application. As shown in FIG. The shape is a zigzag and axisymmetric strip shape, so the first PGS1011 can also be set in an axisymmetrical fence-like shape. In this kind of fence-like first PGS1011, the main structure consists of a first metal strip 10111 and three parallel bars. The second metal strip 10112 is composed of the first metal strip 10111 and the three second metal strips 10112 perpendicular to each other. Therefore, the main structure has four right-angle extensions, and each right-angle extension is provided with a secondary structure. The third metal strip 10113 is provided with the fourth metal strip 10114 extending outward based on the third metal strip 10113. Therefore, the first PGS 1011 has a plurality of cutouts 1013. Due to the existence of these cutouts 1013, the first PGS1011 has only the central part of the area which is complete and continuous. Therefore, the inductor 1021 can only generate a small induced current in the central part of the first PGS1011, which is almost negligible. Therefore, the first PGS1011 can reduce the eddy current effect of the inductor and improve The inductance value and quality factor of the inductor. For further understanding, the shape of the first PGS 1011 will be further described below in conjunction with FIG. 4. FIG. 4 is a schematic diagram of the first PGS provided by an embodiment of the application. As shown in FIG. 4, the first PGS 1011 can also be set as A centrally symmetrical fence-like shape. In the first PGS1011 of this kind of fence-like shape, the main structure is composed of two first metal strips 10111 perpendicular to each other. For the convenience of description, take the left part of one of the first metal strips 10111 It is introduced that on the left part of the first metal strip 10111, there are three parallel second metal strips 10112 extending outward, and on the second second metal strip 10112, there is a third metal strip 10113 extending outward. , And the third metal strip 10113 is perpendicular to the second metal strip 10112. In the same way, the right part of the first metal strip 10111 and the other first metal strip 10111 have the same structure, and will not be repeated here. Therefore, the first PGS 1011 has a plurality of cutouts 1013. Due to the existence of these cutouts 1013, the induced current generated by the inductor can be reduced, and the inductance value and quality factor of the inductor can be improved.
应理解，图3所示出的电感1021和第一PGS1011的轴对称形状仅起示意性说明的作用，并不对本申请实施例中的电感1021和第一PGS1011的形状构成限制。It should be understood that the axisymmetric shapes of the inductor 1021 and the first PGS 1011 shown in FIG. 3 are merely illustrative, and do not limit the shapes of the inductor 1021 and the first PGS 1011 in the embodiment of the present application.
在电感1021和衬底1022之间，还设置有第二PGS(图2中未示出)，第二PGS可以由多晶硅等材料构成，可用于减小电感1021在衬底1022中引起的感应电流。Between the inductor 1021 and the substrate 1022, there is also a second PGS (not shown in FIG. 2). The second PGS can be made of polysilicon and other materials, which can be used to reduce the induced current caused by the inductor 1021 in the substrate 1022. .
封装层101还包括封装金属的第一介质层1012，芯片102还包括覆盖电感1021和第二PGS的第二介质层1023。具体的，第一介质层1012由第一绝缘材料构成，第二介质层1023由第二绝缘材料构成，第二绝缘材料与第一绝缘材料为不同的绝缘材料。例如，可通过环氧树脂构造第一介质层1012，并通过二氧化硅构造第二介质层1023，使得第一介质层1012和第二介质层1023存在一定的区别度，进而令整个集成电路层次分明。The packaging layer 101 further includes a first dielectric layer 1012 of packaging metal, and the chip 102 further includes a second dielectric layer 1023 covering the inductor 1021 and the second PGS. Specifically, the first dielectric layer 1012 is made of a first insulating material, the second dielectric layer 1023 is made of a second insulating material, and the second insulating material and the first insulating material are different insulating materials. For example, the first dielectric layer 1012 can be constructed by epoxy resin, and the second dielectric layer 1023 can be constructed by silicon dioxide, so that the first dielectric layer 1012 and the second dielectric layer 1023 have a certain degree of difference, and the entire integrated circuit level distinct.
为了使得整个集成电路的结构更加紧凑，封装层101的尺寸通常大于或等于芯片102的尺寸。In order to make the structure of the entire integrated circuit more compact, the size of the packaging layer 101 is generally greater than or equal to the size of the chip 102.
本实施例中，第一PGS1011不仅能够减少电感1021在封装层101中引起的感应电流，当第一PGS1011接地时，还可以令封装层101成为一个有效接地的屏蔽层，既可以降低电感1021对外界电路的电磁干扰，也可以减小外界电路对电感1021的干扰。In this embodiment, the first PGS1011 can not only reduce the induced current caused by the inductance 1021 in the packaging layer 101, when the first PGS1011 is grounded, it can also make the packaging layer 101 an effective grounding shielding layer, which can reduce the inductance 1021. The electromagnetic interference of the external circuit can also reduce the interference of the external circuit to the inductor 1021.
以上是对本申请实施例提供的一种集成电路进行的详细说明，以下将对本申请实施例提供的另一种集成电路的结构和连接关系进行介绍，图5为本申请实施例提供的集成电路的另一个示意图，如图5所示，该集成电路包括：芯片和用于封装芯片的封装层，其中，芯片包括压控振荡器，该压控振荡器包括电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管。为了便于说明，图5仅示出了电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管等电子器件及其连接关系。The above is a detailed description of an integrated circuit provided in an embodiment of the application. The structure and connection relationship of another integrated circuit provided in an embodiment of the application will be introduced below. FIG. 5 is a schematic diagram of the integrated circuit provided in an embodiment of the application. Another schematic diagram, as shown in Figure 5, the integrated circuit includes: a chip and a packaging layer for packaging the chip, wherein the chip includes a voltage-controlled oscillator, the voltage-controlled oscillator includes an inductor, a variable capacitor, a capacitor, a first Transistor, second transistor, third transistor, and fourth transistor. For ease of description, FIG. 5 only shows electronic devices such as inductors, variable capacitors, capacitors, first transistors, second transistors, third transistors, and fourth transistors, and their connection relationships.
封装层包括封装金属和第一介质层，第一介质层用于覆盖封装金属。封装金属正对于电感的这一部分金属导体被刻蚀成第一PGS，用于减少电感在封装层中引起的感应电流，封装金属的其余部分技术导体可被刻蚀成具备一定形状的走线，用于连接上述各个电子器件。The packaging layer includes a packaging metal and a first dielectric layer, and the first dielectric layer is used to cover the packaging metal. The packaging metal is etched into the first PGS for this part of the metal conductor of the inductor, which is used to reduce the induced current caused by the inductor in the packaging layer. The remaining part of the technical conductor of the packaging metal can be etched into a trace with a certain shape. Used to connect the above-mentioned electronic devices.
具体的，在上述电子器件中，第一晶体管的第一端与可变电容的第一端连接，第二晶体管的第一端与可变电容的第二端连接，第一晶体管的第二端、第二晶体管的第二端均与电源连接，第一晶体管的第三端与可变电容的第二端连接，第二晶体管的第三端与可变电 容的第一端连接，可变电容、电容与电感并联，第三晶体管的第一端与电感的第一端连接，第四晶体管的第一端与电感的第二端连接，第三晶体管的第二端、第四晶体管的第二端均接地，第三晶体管的第三端与电感的第二端连接，第四晶体管的第三端与电感的第一端连接。需要说明的是，在图5中，可变电容左侧一端为第二端，右侧一端为第一端，同理，电感左侧一端为第二端，右侧一端为第一端。Specifically, in the above electronic device, the first terminal of the first transistor is connected to the first terminal of the variable capacitor, the first terminal of the second transistor is connected to the second terminal of the variable capacitor, and the second terminal of the first transistor , The second end of the second transistor is connected to the power supply, the third end of the first transistor is connected to the second end of the variable capacitor, and the third end of the second transistor is connected to the first end of the variable capacitor. The variable capacitor , The capacitor is connected in parallel with the inductor, the first end of the third transistor is connected to the first end of the inductor, the first end of the fourth transistor is connected to the second end of the inductor, the second end of the third transistor, the second end of the fourth transistor The terminals are all grounded, the third terminal of the third transistor is connected to the second terminal of the inductor, and the third terminal of the fourth transistor is connected to the first terminal of the inductor. It should be noted that in FIG. 5, the left end of the variable capacitor is the second end, and the right end is the first end. Similarly, the left end of the inductor is the second end, and the right end is the first end.
进一步地，芯片还包括第二介质层，第二介质层用于覆盖电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管等电子器件，使得电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管等电子器件设于芯片的衬底之上。Further, the chip also includes a second dielectric layer, and the second dielectric layer is used to cover electronic devices such as inductors, variable capacitors, capacitors, first transistors, second transistors, third transistors, and fourth transistors, so that the Electronic devices such as capacitors, capacitors, first transistors, second transistors, third transistors and fourth transistors are arranged on the substrate of the chip.
更进一步地，电感与衬底之间还设置有第二PGS，第二PGS用于减少电感在衬底中引起的感应电流，且该第二PGS也被第二介质层所覆盖。Furthermore, a second PGS is provided between the inductor and the substrate, and the second PGS is used to reduce the induced current caused by the inductor in the substrate, and the second PGS is also covered by the second dielectric layer.
更进一步地，第一介质层由第一绝缘材料构成，第二介质层由第二绝缘材料构成，第二绝缘材料与第一绝缘材料为不同的绝缘材料。例如，可通过环氧树脂构造第一介质层，并通过二氧化硅构造第二介质层，使得第一介质层和第二介质层存在一定的区别度。Furthermore, the first dielectric layer is composed of a first insulating material, the second dielectric layer is composed of a second insulating material, and the second insulating material and the first insulating material are different insulating materials. For example, the first dielectric layer can be constructed by epoxy resin, and the second dielectric layer can be constructed by silica, so that there is a certain degree of difference between the first dielectric layer and the second dielectric layer.
更进一步地，封装层的尺寸通常大于或等于芯片的尺寸。Furthermore, the size of the encapsulation layer is generally greater than or equal to the size of the chip.
本实施例中，当压控振荡器处于工作状态时，若电感中的电流发生变化，由于封装层中第一PGS的存在，能够减少电感在封装层中引起的感应电流，可以减小电感的涡流效应，提高电感的性能。In this embodiment, when the voltage-controlled oscillator is in the working state, if the current in the inductor changes, due to the existence of the first PGS in the packaging layer, the induced current caused by the inductor in the packaging layer can be reduced, and the inductance can be reduced. The eddy current effect improves the performance of the inductor.
为了便于理解，以下结合一个应用例对本申请实施例提供的压控振荡器作进一步的介绍，该应用例包括：设本申请实施例提供的压控振荡器为压控振荡器A，基于图1所提供的集成电路所构建的压控振荡器为压控振荡器B(即压控振荡器B未设置第一PGS)，并对压控振荡器A和压控振荡器B进行仿真运行，以得到两种压控振荡器所对应的仿真结果。For ease of understanding, the following will further introduce the voltage-controlled oscillator provided by the embodiment of the present application in conjunction with an application example. The application example includes: suppose the voltage-controlled oscillator provided by the embodiment of the present application is a voltage-controlled oscillator A, based on FIG. 1 The voltage-controlled oscillator constructed by the provided integrated circuit is the voltage-controlled oscillator B (that is, the voltage-controlled oscillator B is not set with the first PGS), and the voltage-controlled oscillator A and the voltage-controlled oscillator B are simulated to run The simulation results corresponding to the two voltage-controlled oscillators are obtained.
图6为本申请实施例提供的电感值的仿真结果图，需要说明的是，图6所示坐标系中，横坐标为频率，单位为GHz，纵坐标为电感值，单位为pH。图7为本申请实施例提供的电感品质因数的仿真结果图，需要说明的是，图7所示坐标系中，横坐标为频率，单位为GHz，纵坐标为品质因数。如图6所示，曲线1为压控振荡器A的电感值仿真曲线，曲线2为压控振荡器B的电感值仿真曲线。如图7所示，曲线3为压控振荡器A的电感品质因数仿真曲线，曲线4为压控振荡器B的电感品质因数仿真曲线。Fig. 6 is a simulation result diagram of the inductance value provided by the embodiment of the application. It should be noted that, in the coordinate system shown in Fig. 6, the abscissa is frequency and the unit is GHz, and the ordinate is the inductance value and the unit is pH. FIG. 7 is a graph of simulation results of the inductor quality factor provided by an embodiment of the application. It should be noted that, in the coordinate system shown in FIG. 7, the abscissa is frequency, the unit is GHz, and the ordinate is the quality factor. As shown in Fig. 6, curve 1 is the simulation curve of the inductance value of the voltage-controlled oscillator A, and curve 2 is the simulation curve of the inductance value of the voltage-controlled oscillator B. As shown in FIG. 7, curve 3 is a simulation curve of the inductance quality factor of the voltage-controlled oscillator A, and curve 4 is a simulation curve of the inductance quality factor of the voltage-controlled oscillator B.
经过比对以上的仿真结果可知，由于压控振荡器A中设有第一PGS，压控振荡器A中电感的电感值和电感品质因数优于压控振荡器B中电感的电感值和电感品质因数。基于以上的仿真结果，压控振荡器A的频率仅偏移大致2％，而压控振荡器若B的频率则会偏移20％以上，同时，由于压控振荡器A中电感的品质因数较高，故压控振荡器A的噪声性能也优于压控振荡器B的噪声性能。After comparing the above simulation results, it can be seen that since the voltage-controlled oscillator A is equipped with the first PGS, the inductance value and the inductance quality factor of the inductor in the voltage-controlled oscillator A are better than the inductance value and inductance of the inductor in the voltage-controlled oscillator B Quality factor. Based on the above simulation results, the frequency of the voltage-controlled oscillator A only shifts by approximately 2%, while the frequency of the voltage-controlled oscillator B will shift by more than 20%. At the same time, due to the quality factor of the inductance of the voltage-controlled oscillator A Higher, so the noise performance of voltage controlled oscillator A is also better than that of voltage controlled oscillator B.

Claims (12)

  1. 一种集成电路，其特征在于，包括：芯片和用于封装所述芯片的封装层；An integrated circuit, characterized by comprising: a chip and a packaging layer for packaging the chip;
    所述芯片包括衬底和设于所述衬底之上的电感；The chip includes a substrate and an inductor provided on the substrate;
    所述封装层包括第一图案接地屏蔽结构PGS，所述第一PGS位于所述封装层内的金属层，所述第一PGS为由所述金属层上的金属刻蚀而成，且所述第一PGS位于所述电感之上，所述第一PGS用于减少所述电感在所述金属层中的感应电流。The packaging layer includes a first pattern ground shielding structure PGS, the first PGS is located in a metal layer in the packaging layer, the first PGS is formed by etching metal on the metal layer, and the The first PGS is located above the inductor, and the first PGS is used to reduce the induced current of the inductor in the metal layer.
  2. 根据权利要求1所述的集成电路，其特征在于，所述第一PGS具有切口，所述切口用于减少所述感应电流。The integrated circuit of claim 1, wherein the first PGS has a cutout, and the cutout is used to reduce the induced current.
  3. 根据权利要求1或2所述的集成电路，其特征在于，所述第一PGS正对所述电感。3. The integrated circuit of claim 1 or 2, wherein the first PGS faces the inductor.
  4. 根据权利要求1至3任意一项所述的集成电路，其特征在于，所述电感与所述衬底之间设置有第二PGS，所述第二PGS用于减少所述电感在所述衬底中引起的所述感应电流。The integrated circuit according to any one of claims 1 to 3, wherein a second PGS is provided between the inductor and the substrate, and the second PGS is used to reduce the inductance on the substrate. The induced current caused in the bottom.
  5. 根据权利要求4所述的集成电路，其特征在于，所述第二PGS由多晶硅构成。The integrated circuit of claim 4, wherein the second PGS is made of polysilicon.
  6. 根据权利要求5所述的集成电路，其特征在于，所述封装层还包括覆盖所述第一PGS的第一介质层。The integrated circuit of claim 5, wherein the encapsulation layer further comprises a first dielectric layer covering the first PGS.
  7. 根据权利要求6所述的集成电路，其特征在于，所述芯片还包括覆盖所述电感和所述第二PGS的第二介质层。7. The integrated circuit of claim 6, wherein the chip further comprises a second dielectric layer covering the inductor and the second PGS.
  8. 根据权利要求7所述的集成电路，其特征在于，所述第一介质层由第一绝缘材料构成。8. The integrated circuit of claim 7, wherein the first dielectric layer is made of a first insulating material.
  9. 根据权利要求8所述的集成电路，其特征在于，所述第二介质层由第二绝缘材料构成，所述第二绝缘材料与所述第一绝缘材料为不同的绝缘材料。8. The integrated circuit of claim 8, wherein the second dielectric layer is composed of a second insulating material, and the second insulating material and the first insulating material are different insulating materials.
  10. 根据权利要求1至9任意一项所述的集成电路，其特征在于，所述封装层的尺寸大于或等于所述芯片的尺寸。The integrated circuit according to any one of claims 1 to 9, wherein the size of the packaging layer is greater than or equal to the size of the chip.
  11. 一种集成电路，其特征在于，包括：芯片和用于封装所述芯片的封装层；An integrated circuit, characterized by comprising: a chip and a packaging layer for packaging the chip;
    所述芯片包括压控振荡器，所述压控振荡器包括电感、可变电容、电容、第一晶体管、第二晶体管、第三晶体管和第四晶体管；The chip includes a voltage-controlled oscillator, and the voltage-controlled oscillator includes an inductor, a variable capacitor, a capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor;
    所述第一晶体管的第一端与所述可变电容的第一端连接，所述第二晶体管的第一端与所述可变电容的第二端连接，所述第一晶体管的第二端、所述第二晶体管的第二端均与电源连接，所述第一晶体管的第三端与所述可变电容的第二端连接，所述第二晶体管的第三端与所述可变电容的第一端连接，所述可变电容、所述电容与所述电感并联，所述第三晶体管的第一端与所述电感的第一端连接，所述第四晶体管的第一端与所述电感的第二端连接，所述第三晶体管的第二端、所述第四晶体管的第二端均接地，所述第三晶体管的第三端与所述电感的第二端连接，所述第四晶体管的第三端与所述电感的第一端连接；The first terminal of the first transistor is connected to the first terminal of the variable capacitor, the first terminal of the second transistor is connected to the second terminal of the variable capacitor, and the second terminal of the first transistor is connected to the The second end of the second transistor and the second end of the second transistor are both connected to the power supply, the third end of the first transistor is connected to the second end of the variable capacitor, and the third end of the second transistor is connected to the The first terminal of the variable capacitor is connected, the variable capacitor and the capacitor are connected in parallel with the inductor, the first terminal of the third transistor is connected to the first terminal of the inductor, and the first terminal of the fourth transistor is connected to the The terminal is connected to the second terminal of the inductor, the second terminal of the third transistor and the second terminal of the fourth transistor are both grounded, and the third terminal of the third transistor is connected to the second terminal of the inductor. Connected, the third end of the fourth transistor is connected to the first end of the inductor;
    所述封装层包括第一PGS，所述第一PGS为基于所述封装层内的封装金属刻蚀而成的，所述第一PGS用于减少所述电感在所述封装层中引起的感应电流。The packaging layer includes a first PGS, the first PGS is etched based on the packaging metal in the packaging layer, and the first PGS is used to reduce the induction caused by the inductance in the packaging layer Current.
  12. 根据权利要求11所述的集成电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均为金属-氧化物半导体场效应管MOSFET或双极结型晶体管BJT。The integrated circuit of claim 11, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all metal-oxide semiconductor field effect transistors MOSFET or dual Polar junction transistor BJT.
PCT/CN2019/122063 2019-11-29 2019-11-29 Integrated circuit WO2021102940A1 (en)

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