CN114758693B - Positioning method and positioning device for invalid word line of memory array - Google Patents

Positioning method and positioning device for invalid word line of memory array Download PDF

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Publication number
CN114758693B
CN114758693B CN202210519029.5A CN202210519029A CN114758693B CN 114758693 B CN114758693 B CN 114758693B CN 202210519029 A CN202210519029 A CN 202210519029A CN 114758693 B CN114758693 B CN 114758693B
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word line
logic data
word lines
memory cells
data
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CN114758693A (en
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安九华
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Xi'an Ziguang Guoxin Semiconductor Co ltd
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Xian Unilc Semiconductors Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

The application discloses a method and a device for positioning a storage array failure word line. The method for positioning the invalid word line of the memory array comprises the following steps: writing first logic data to memory cells of a memory array; traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result; in response to the read result of the memory cell being empty, the word line at the corresponding location fails, and the failure cause is determined as the word line cannot be activated. In this way, a failed word line in the memory array can be accurately located.

Description

Positioning method and positioning device for invalid word line of memory array
Technical Field
The present application relates to the field of memory chips, and in particular, to a method and an apparatus for positioning a failed word line of a memory array.
Background
Memory array failure is a common memory chip failure mode, and Word line WL (Word line) failure is one of the common modes of memory array failure, and the root cause of the failure is often caused by a memory chip manufacturing process defect (deviation), a memory chip design weakness or the like. And memory array failure can result in extremely high memory chip yield loss.
How to accurately locate the position, mechanism and reason of the failure of the memory array, then find and correct the defects (deviation) of the manufacturing process, optimize the design of the memory chip, finally improve the yield of the memory chip, enhance the use reliability of the memory chip, and have great significance.
Disclosure of Invention
The application mainly solves the technical problem of providing a positioning method and a positioning device for a storage array failure word line so as to accurately position the storage array failure and acquire the failure reason.
In order to solve the technical problems, the application adopts a technical scheme that: a method for locating a failed word line of a DRAM memory array is provided. The method for positioning the invalid word line of the memory array comprises the following steps: writing first logic data to memory cells of a memory array; traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result; in response to the read result of the memory cell being empty, the word line at the corresponding location fails, and the failure cause is determined as the word line cannot be activated.
In order to solve the technical problems, the application adopts a technical scheme that: a device for locating a failed word line of a memory array is provided. The positioning device for the failure word line of the memory array comprises: the first graphic vector generation module is connected with the storage array and used for generating a first graphic vector, writing first logic data to the storage array based on the first graphic vector, traversing at least part of word lines in the storage array, and performing data reading operation on corresponding storage units to obtain a reading result; and the address collection analysis module is connected with the storage array and is used for collecting the reading result of the data reading operation, and determining that the word line at the corresponding position is invalid in response to the reading result of the storage unit being empty, and determining that the failure is caused by the fact that the word line cannot be activated.
The beneficial effects of the application are as follows: compared with the prior art, the method comprises the steps of firstly writing first logic data into the memory cells of the memory array, then traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result; since the read result is empty when the corresponding memory cell is written with the first logic data if the word line cannot be activated, if the read result of the memory cell is empty, it can be determined that the word line at the corresponding position is invalid, and the failure cause is determined that the word line cannot be activated.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory array according to an embodiment of the present application;
FIG. 2 is a flow chart of an embodiment of a method for locating a failed word line of a memory array according to the present application;
FIG. 3 is a schematic diagram showing a specific flow of step S22 in the embodiment of FIG. 2;
FIG. 4 is a schematic flowchart of step S31 in the embodiment of FIG. 3;
FIG. 5 is a schematic diagram of a structure of logic data in a memory cell of the memory array corresponding to the positioning method of the embodiment of FIG. 2;
FIG. 6 is a flow chart of a partial process in an embodiment of a memory array according to the present application;
FIG. 7 is a schematic diagram of the structure of logic data in memory cells in the memory array corresponding to the method of FIG. 6;
FIG. 8 is a flow chart of a partial process in an embodiment of a memory array according to the present application;
FIG. 9 is a schematic diagram of a structure of logic data in memory cells of the memory array according to the method of FIG. 8;
FIG. 10 is a schematic diagram of a structure of logic data in memory cells of the memory array according to the method of FIG. 8;
FIG. 11 is a schematic diagram illustrating an embodiment of a device for locating a failed word line of a memory array according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The technical scheme of the application can be used for dynamic random access memories (Dynamic Random Access Memory, DRAM) or other memories, memory chips and the like. The following embodiments of the present application will be described with reference to a DRAM.
As shown in fig. 1, in the DRAM memory array, the intersection of each word line WL and each Bit line BL (Bit line) is a one-Bit memory cell, and all the memory cells form the memory array. The application provides a positioning method and a positioning device for a failed word line of a DRAM memory array, which can rapidly judge whether read data failure is related to a word line WL (whether the word line WL fails or not) by executing a corresponding simple operation method; in the case where one word line WL fails, the address and failure cause (failure mechanism) of the failed word line WL can be accurately and directly located.
The present application first proposes a method for locating a failed word line of a memory array, as shown in fig. 2, fig. 2 is a flow chart of an embodiment of the method for locating a failed word line of a memory array according to the present application. The positioning method of the storage array failure word line in this embodiment specifically includes the following steps:
step S21: first logic data is written to the memory array.
Background data, i.e., first logic data, which may be logic data "0", is written to the entire DRAM memory array.
Before step S21 is performed, the DRAM may be subjected to processing such as power-up and initialization configuration.
Step S22: traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result.
Alternatively, the method shown in fig. 3 may be used to implement step S22, where the method of the present embodiment includes step S31 and step S32.
Step S31: and writing second logic data into the memory cells corresponding to at least part of the word lines.
The second logic data may be logic data "1" as opposed to the first logic data.
Alternatively, the method shown in fig. 4 may be used to implement step S31, and the method of this embodiment includes step S41 and step S42.
Step S41: and performing data reading operation on the memory cells corresponding to at least part of the word lines.
Step S42: after the data reading operation, the second logic data is written into the corresponding memory cell. In one embodiment, traversing the word lines WL of the DRAM memory array in turn, for each word line WL, performs:
the word line is activated. The activated word line WL can write data from the corresponding memory cell and read data through the bit line BL, and the memory cell corresponding to the non-activated word line WL cannot perform the read/write operation of data.
The first logic data is read from the DRAM memory array. And reading the first logic data from the word line WL in the active state in the DRAM memory array through the address collection analysis module, and recording the reading result of the first logic data, wherein the reading result of the first logic data comprises whether the first logic data is successfully read or not and the address of the corresponding word line WL.
The second logic data is written to the activated word line, wherein the second logic data is opposite to the first logic data. The first logic data is "0", and the second logic data is "1".
The application scenario does not limit the traversal order of each word line WL, and for ease of recording and calculation, the traversal may be started from word line WL <0 >. Alternatively, the present embodiment may generate the first graphics vector by the graphics vector generating module, write the first logic data into the entire DRAM memory array through the first graphics vector, and then control each word line WL to perform the corresponding operation according to the above method.
In this embodiment, the DRAM may be used as a macro block, and the test vector of the macro block may be generated by using the scan path in the circuit, and then the test vector, that is, the first graphics vector, may be applied to the outside of the circuit by the graphics vector generating module.
Of course, in other embodiments, direct access testing or built-in subtest, etc. may also be used to control the DRAM memory array to perform the above steps.
Note that while traversing a word line WL, other word lines controlling the DRAM memory array are in an inactive state (inactive word lines WL cannot be activated or cannot be controlled to be in an inactive state).
Step S32: and performing data reading operation on the memory cells corresponding to the other part of word lines to obtain a reading result.
Step S23: in response to the read result of the memory cell being empty, the word line at the corresponding location is disabled, and it is determined that the failure is due to the word line being unable to be activated.
In the embodiment, first logic data is written into the memory cells of the memory array, then at least part of word lines in the memory array are traversed, and data reading operation is carried out on the corresponding memory cells to obtain a reading result; since the read result is empty when the corresponding memory cell is written with the first logic data if the word line cannot be activated, if the read result of the memory cell is empty, it can be determined that the word line at the corresponding position is invalid, and the failure cause is determined that the word line cannot be activated.
In the application scenario, after the traversing is completed, determining whether the DRAM memory array has a failed word line and a position of the failed word line in the DRAM memory array and a failure reason based on a read result of the first logic data.
And analyzing whether a failed word line exists in the DRAM storage array or not and the position and failure reason of the failed word line in the DRAM storage array based on the read results of all word lines WL on the first logic data, which are acquired by the address collection analysis module.
Because the failed word line WL is affected by its failure when activating and/or writing and reading data, the read data of the failed word line WL may fail or may cause the read data of other word lines to fail, so the embodiment traverses each word line WL sequentially, and by activating and reading and writing logic data with opposite logic, it can determine whether the DRAM memory array has the failed word line WL and accurately locate the position of the failed word line WL in the DRAM memory array and the failure cause (failure mechanism) according to the read result of the logic data.
Specifically, if all word lines in the DRAM memory array read the first logic data successfully, it is determined that no failed word lines exist in the DRAM memory array. If the address collection analysis module judges that all word lines WL in the DRAM storage array read the first logic data successfully, determining that no invalid word line WL exists in the DRAM storage array, namely the DRAM chip is good.
If only one word line in the DRAM memory array fails to read the first logic data, then one word line is determined to be the word line that failed to be activated.
If the address collection analysis module determines that only one word line WL in the DRAM memory array fails to read the first logic data, the word line WL is determined to be the failed word line WL, so that the address of the failed word line WL and the failure cause thereof can be located as the failed activation.
As shown in fig. 5, a first graphic vector is generated by the graphic vector generation module, first logic data, namely background "0", is written into the whole DRAM memory array by the first graphic vector, and the data is stored; then activating one word line WL, reading background '0' through an address collection analysis module, immediately writing second logic data '1' opposite to the first logic data to the activated word line WL (writing reverse topology), storing data, and traversing all word lines WL according to the data; the address collection analysis module collects the read result of each word line WL against background "0".
The address collection analysis module analyzes the reading result:
if all word lines WL read background "0" succeed, then it is determined that all word lines WL have not failed.
If only all bit lines BL corresponding to the word line WL < m > fail to read the background "0", the failure reason is that the word line WL < m > cannot be activated, i.e. the address of the failed word line WL is m, and the failure reason is that the failed word line WL cannot be activated.
If WL < m > is always in an activated state, after writing background "0", reading background "0" from WL <0> after activating WL <0>, and immediately writing anti-topology "1" to WL <0>, the word line WL < m > will also be written with second logic data "1"; when the word line WL <1> is activated and then the background "0" is read, the word line WL < m > is also activated and stores the second logic data "1", so that the read WL <1> fails; similarly, reading background "0" for other word lines WL will fail; if a large number of word lines WL fail to read the background "0", it is possible that a certain word line WL is always active (which can be further positioned based on the embodiments described below).
In other embodiments, the first logic data may also be logic data "1".
Alternatively, the failed word line WL includes a word line WL that is always in an active state, and in another embodiment, if it is determined that the first logic data fails to be read based on the read result, the failed word line exists in the remaining word lines, and the failure cause is determined that the word line is always in an active state.
In an application scenario, it may be determined that there is a word line WL in the memory array that is always active by the method shown in fig. 6.
Step S61: if the first logic data is failed to be read by a plurality of word lines in the DRAM memory array, the first logic data is written into the DRAM memory array.
From the analysis of the above embodiments, if all word lines WL read background "0" successfully, it is determined that all word lines WL have not failed; if only all bit lines BL corresponding to the word line WL < m > fail to read the background "0", determining that the word line WL < m > fails; if a large number of word lines WL fail to read the background "0", it may be that a certain word line WL is always activated.
For the last case, the graphics vector generation module generates a second graphics vector, first writing the first logical data "0" to the DRAM memory array.
Step S62: a first predetermined word line is activated.
The first preset word line WL < x > is activated based on the second pattern vector, and the activated first preset word line WL < x > may write data and read data from the corresponding memory cell through the bit line BL.
Step S63: the second logic data is written to the first preset word line.
And writing second logic data to the first preset word line WL < x > based on the second graphic vector, namely writing the reverse topology to the first preset word line WL < x > activated currently, wherein at the moment, the word line always in the activated state also writes the reverse topology, so that the reading of the first logic data to other subsequent word lines is influenced.
In other embodiments, the first logic data may be logic data "1" and the second logic data may be logic data "0".
Step S64: other word lines in the DRAM memory array are traversed, the word lines are activated first, and then the first logic data is read.
The first logic data "0" is read by the address collection analysis module based on the second pattern vector traversing other word lines WL in the DRAM memory array, first activated for each word line WL.
Step S65: after the traversing is completed, if all word lines of the DRAM memory array fail to read the first logic data, determining that the word lines in the DRAM memory array are always in an activated state.
If the address collection analysis module determines that all word lines of the DRAM memory array fail to read the first logic data "0", determining that there is a failed WL in the DRAM memory array, wherein the reason for the failure is always in an activated state.
As shown in fig. 7, a second graphic vector is generated by the graphic vector generation module, and first logic data, namely background "0", is written into the whole DRAM memory array through the second graphic vector, and the data is stored; then activating the first preset word line WL < x > through the second graphic vector, and writing second logic data to the first preset word line WL < x >; traversing all other word lines WL, activating the word lines WL first, and then reading background "0"; the address collection analysis module collects the read result of each word line WL against background "0".
The address collection analysis module analyzes the reading result:
if the word line WL < m > is always activated, as shown in FIG. 7, after writing background "0", when the word line WL < x > is activated to write anti-topology "1", the word line WL < m > will also be written with second logic data "1"; when the word line WL <0> is activated for reading background "0", the read word line WL <0> will fail because the read word line WL < m > is also in an activated state and stores the second logic data "1"; similarly, reading other word lines WL will fail; so if the read "0" fails for all but word line WL < x > within the DRAM memory array, then one of the word lines WL is always active for the reason that the read "0" fails for the remaining word lines.
To determine the location (address) of the word line WL always in the activated state, the address of the word line WL always in the activated state may be located using the method as shown in fig. 8. Each word line WL is traversed in sequence according to steps S81 to S611.
Step S81: first logic data is written to the memory array.
The graphics vector generation module generates a third graphics vector based on which the first logical data "0" is written to the DRAM memory array.
Step S82: and writing second logic data to the memory cells corresponding to the nth word line, and writing first logic data to the memory cells corresponding to the other word lines except the nth word line.
Specifically, a second preset word line is activated. Activating a second preset word line WL < n > based on the third graphic vector; and writing second logic data to a second preset word line.
The second logic data "1" is written to the second preset word line WL < n > based on the third graphic vector. In other embodiments, the first logic data may be logic data "1" and the second logic data may be logic data "0".
The first logic data is written to other word lines in the DRAM memory array. The first logic data "0" is written to the other word lines WL in the DRAM memory array based on the third graphics vector.
Step S83: the first logic data is read from the memory cell corresponding to the n+1th word line.
The first logic data is read for a next adjacent word line of the second preset word line. And reading the first logic data '0' for the next adjacent word line WL < n+1> of the second preset word line WL < n > based on the third graphic vector, and acquiring a reading result by the address collection analysis module.
Step S84: the position of the word line always in the activated state is determined based on the read result of the first logic data.
In response to a failure to read the first logic data, determining that the nth word line is a word line that is always in an active state; in response to successful reading of the first logic data, it is determined that the nth word line is not the word line that is always in an active state.
The location of the word line in the DRAM memory array that is always active is determined based on the read result of the next adjacent word line.
Specifically, if the next adjacent word line WL < n+1> fails to read the first logic data "0", determining that the second preset word line WL < n > is the word line always in the activated state; if the next adjacent word line WL < n+1> successfully reads the first logic data "0", it is determined that the second preset word line WL < n > is not the word line always in the active state.
As shown in fig. 9 and 10, the graphics vector generation module generates a third graphics vector, writes a background "0" to the entire DRAM memory array based on the third graphics vector, and stores data; then, randomly selecting one word line WL < n > to write second logic data '1', and storing data; then writing background "0" again to the other word lines WL except for the word line WL < n >, and storing data; finally, reading background '0' for word line WL < n+1 >; and traversing all the WL addresses of the word lines, and collecting addresses which fail to read by the address collecting and analyzing module.
Further, the above must be repeated completely for each word line WL, otherwise, a large number of word lines WL fail to read, and the word line WL always activated cannot be located.
The address collection analysis module analyzes the reading result:
if word line WL < n+1> successfully reads background "0", then n is not equal to m (provided that word line WL < m > is always active); as shown in fig. 9, after writing the background "0", an arbitrary selected word line WL < n > is activated and written with the second logic data "1", the word line WL < m > is also written with the second logic data "1", and then when writing "0" again to all other word lines WL except the word line WL < n >, the word line WL < m > is also written back with the background "0"; when the word line WL < n+1> is activated, the word line WL < m > stores the background "0" even though the word line W < m > is also activated, so that reading the background "0" for the word line WL < n+1> succeeds.
If WL < n+1> fails to read background "0", n is equal to m, and the word line WL < n > is the word line WL < m > in the active state all the time; as shown in fig. 10, after writing the background "0", the word line WL < m=n > is activated and the second logic data "1" is written, and then, the background "0" is written again for all other word lines WL except for the word line WL < m=n >, and when the word line WL < n+1> is activated, since the word line WL < m=n > is also in the activated state and the second logic data "1" is stored, reading the background "0" for the word line WL < n+1> fails.
In other embodiments, if it is determined that only one word line WL always activated exists in the DRAM memory array, the steps S81 to S83 described above may be performed on the second preset word line WL < n >, and if the next adjacent word line WL < n+1> fails to read the first logic data "0", it is determined that the second preset word line WL < n > is the word line always activated, without traversing the other word lines WL; if the next adjacent word line WL < n+1> successfully reads the first logic data "0", it is determined that the second preset word line WL < n > is not the word line in the active state all the time, and the next word line WL is traversed by continuing to use the steps S66 to S611 until the word line WL in the active state all the time is found.
It should be noted that, the read-write of each sub-line is independent, and the read-write of two or more word lines is not performed simultaneously. For example, when writing data to a word line, the word line is activated, and then the word line is turned off after writing data to the memory cell corresponding to the word line.
The application further provides a positioning device for the failed word line of the memory array, as shown in fig. 11, fig. 11 is a schematic structural diagram of an embodiment of the positioning device for the failed word line of the memory array. The positioning device (not shown) of the present embodiment includes: a first graphics vector generation module 91 and an address collection analysis module 92; the first graphics vector generation module 91 is connected to a memory array (e.g., a memory array of a DRAM) and is configured to generate a first graphics vector, write first logic data to the memory array based on the first graphics vector, traverse at least a portion of word lines in the memory array, and perform a data reading operation on corresponding memory cells to obtain a reading result; the address collection analysis module 92 is coupled to the memory array for collecting the read results of the data read operation and, in response to the read results of the memory cells being empty, determining that the word line at the corresponding location is inactive and determining that the source of the failure is that the word line cannot be activated.
The first graphics vector generation module 91 performs a data reading operation on the memory cells corresponding to at least part of the word lines after writing the first logic data on the memory cells of the memory array based on the first graphics vector, and writes the second logic data on the corresponding memory cells after the data reading operation, and performs a data reading operation on the memory cells corresponding to the rest of the word lines, thereby obtaining a reading result.
The failed word line includes a failed activation word line, and in an application scenario, if all word lines in the DRAM memory array read the first logic data successfully, the address collection analysis module 92 determines that no failed word line exists in the DRAM memory array; if only one word line in the DRAM memory array fails to read the first logic data, the address collection analysis module 92 determines that the word line is the word line that failed to be activated.
Optionally, the failed word line includes a word line that is always in an activated state, and the positioning device for a failed word line of the memory array of this embodiment further includes: a second graphics vector generation module 93, coupled to the storage array, for generating a second graphics vector, the second graphics vector generation module 93 performing based on the second graphics vector: writing first logic data into the memory cells of the memory array, writing second logic data into the memory cells corresponding to at least part of word lines, and performing data reading operation on the memory cells corresponding to the rest part of word lines to obtain a reading result; if the first logic data is determined to fail to be read based on the read result, the address collection analysis module determines that a failed word line exists in the rest word lines, and the failure reason is determined that the word line is always in an activated state.
In an application scenario, if the plurality of word lines in the DRAM memory array fail to read the first logic data, the second graphics vector generation module 93 writes the first logic data to the DRAM memory array based on the second graphics vector, and activates the first preset word line; the second graphics vector generation module 93 writes second logic data to the first preset word line based on the second graphics vector, and traverses other word lines in the DRAM memory array, activates the word line first, and then reads the first logic data; after the traversal is complete, if all of the word lines of the DRAM memory array fail to read the first logic data, the address collection analysis module 92 determines that there are word lines in the DRAM memory array that are always active.
Optionally, the positioning device for a storage array failure word line of the present embodiment further includes: a third graphics vector generation module 94, coupled to the storage array, for generating a third graphics vector; after determining that there are word lines in the memory array that are always active, the third graphics vector generation module 94 performs, based on the third graphics vector: writing first logic data to the memory array; writing second logic data to the memory cells corresponding to the nth word line, and writing first logic data to the memory cells corresponding to the other word lines except the nth word line; the address collection analysis module reads the first logic data from the memory cell corresponding to the n+1th word line, and determines the position of the word line always in an activated state based on the read result of the first logic data.
In response to a failure to read the first logic data, the address collection analysis module 92 determines that the nth word line is the word line that is always in an active state; in response to successful reading of the first logic data, the address collection analysis module 92 determines that the nth word line is not the word line that is always in an active state.
In an application scenario, each word line of the DRAM memory array is traversed sequentially according to the following sub-steps: writing first logic data to the DRAM memory array; activating a second preset word line; writing second logic data to a second preset word line; writing first logic data to other word lines in the DRAM memory array; reading first logic data from a next adjacent word line of the second preset word line; the address collection analysis module 92 determines the location of the word line in the DRAM memory array that is always active based on the read results of the next adjacent word line.
Specifically, if the next adjacent word line fails to read the first logic data, the address collection analysis module 92 determines that the second predetermined word line is the word line that is always in the active state; if the next adjacent word line successfully reads the first logic data, the address collection analysis module 92 determines that the second preset word line is not the always active word line.
The positioning device of the present embodiment further includes: and the initialization module 95 is connected with the storage array and is used for powering up and initializing the storage array.
The working principle of the positioning device for the failed word line of the memory array in this embodiment can be referred to the above embodiment, which is not repeated here.
Compared with the prior art, the method comprises the steps of firstly writing first logic data into the memory cells of the memory array, then traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result; since the read result is empty when the corresponding memory cell is written with the first logic data if the word line cannot be activated, if the read result of the memory cell is empty, it can be determined that the word line at the corresponding position is invalid, and the failure cause is determined that the word line cannot be activated.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims (10)

1. A method for locating a failed word line of a memory array, comprising:
writing first logic data to memory cells of a memory array;
traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result;
in response to the read result of the memory cell being empty, the word line at the corresponding location fails, and a failure cause is determined as the word line cannot be activated;
traversing at least part of word lines in the memory array, and performing data reading operation on the corresponding memory cells to obtain a reading result, wherein the method comprises the following steps:
writing second logic data into the memory cells corresponding to at least part of the word lines;
performing data reading operation on the memory cells corresponding to the rest part of the word lines to obtain a reading result;
the positioning method further comprises the following steps:
and determining that the first logic data is failed to be read based on the reading result, wherein invalid word lines exist in the rest word lines, and determining that the word lines are always in an activated state as a failure reason.
2. The positioning method according to claim 1, wherein said writing second logic data to said memory cells corresponding to at least part of said word lines comprises:
performing data reading operation on the memory cells corresponding to at least part of the word lines;
and after the data reading operation, writing second logic data into the corresponding storage unit.
3. The positioning method according to claim 1, characterized in that the positioning method further comprises:
the location of the word line that is always active is determined.
4. A positioning method according to claim 3, wherein said determining the location of the word line that is always active comprises:
writing the first logic data to the storage array;
writing the second logic data to the memory cells corresponding to the nth word line, and writing the first logic data to the memory cells corresponding to the rest word lines except the nth word line;
reading the first logic data from the memory cells corresponding to the n+1th word line;
the location of the word line that is always in an active state is determined based on the read result of the first logic data.
5. The positioning method according to claim 4, wherein the determining the position of the word line always in the activated state based on the read result of the first logic data includes:
in response to a failure to read the first logic data, determining that an nth one of the word lines is always in an activated state;
in response to successful reading of the first logic data, it is determined that the nth of the word lines is not a word line that is always in an active state.
6. A memory array failure word line locating apparatus, comprising:
the first graphic vector generation module is connected with the storage array and used for generating a first graphic vector, writing first logic data to the storage array based on the first graphic vector, traversing at least part of word lines in the storage array, and performing data reading operation on storage units of the corresponding storage array to obtain a reading result;
the address collection analysis module is connected with the storage array and is used for collecting a read result of the data read operation, determining that the word line at a corresponding position is invalid if the read result of the storage unit is empty, and determining that the failure is caused by the fact that the word line cannot be activated;
the word line that fails includes the word line that is always in an activated state, the positioning device further comprising: a second graphics vector generation module, coupled to the storage array, for generating a second graphics vector, the second graphics vector generation module performing based on the second graphics vector: writing first logic data into memory cells of the memory array, writing second logic data into memory cells corresponding to at least part of the word lines, and performing data reading operation on the memory cells corresponding to the rest part of the word lines to obtain a reading result;
and if the first logic data is determined to fail to be read based on the reading result, the address collection analysis module determines that the rest word lines have failed word lines, and the failure reason is determined that the word lines are always in an activated state.
7. The positioning device of claim 6, wherein the first graphics vector generation module performs a data reading operation on at least a portion of the memory cells corresponding to the word lines after writing first logic data to the memory cells of the memory array based on the first graphics vector, writes second logic data to the corresponding memory cells after the data reading operation, and performs a data reading operation on the remaining portion of the memory cells corresponding to the word lines to obtain a read result.
8. The positioning device as set forth in claim 7 further comprising: the third graphic vector generation module is connected with the storage array and is used for generating a third graphic vector; after determining that there are word lines in the memory array that are always active, the third graphics vector generation module performs, based on the third graphics vector:
writing the first logic data to the storage array;
writing the second logic data to the memory cells corresponding to the nth word line, and writing the first logic data to the memory cells corresponding to the rest word lines except the nth word line;
the address collection analysis module reads the first logic data from the storage unit corresponding to the n+1th word line, and determines the position of the word line in an activated state all the time based on the reading result of the first logic data.
9. The positioning device of claim 8, wherein in response to a failure to read the first logic data, the address collection analysis module determines an nth of the word lines to be a word line that is always active;
in response to successful reading of the first logic data, the address collection analysis module determines that the nth word line is not a word line that is always in an active state.
10. The positioning device as set forth in claim 6 further comprising: and the initialization module is connected with the storage array and is used for powering on and initializing the storage array.
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Publication number Priority date Publication date Assignee Title
KR20120025768A (en) * 2010-09-08 2012-03-16 주식회사 하이닉스반도체 Test method of semiconductor device
JP2013012275A (en) * 2011-06-29 2013-01-17 Renesas Electronics Corp Semiconductor memory and its testing method
CN104751875A (en) * 2013-12-25 2015-07-01 上海华虹宏力半导体制造有限公司 Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120025768A (en) * 2010-09-08 2012-03-16 주식회사 하이닉스반도체 Test method of semiconductor device
JP2013012275A (en) * 2011-06-29 2013-01-17 Renesas Electronics Corp Semiconductor memory and its testing method
CN104751875A (en) * 2013-12-25 2015-07-01 上海华虹宏力半导体制造有限公司 Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip

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