CN104751875A - Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip - Google Patents
Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip Download PDFInfo
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Abstract
The invention discloses a failure bitmap analysis method applied to an NVM (Non-Volatile Memory) chip. According to the method, an HV (High Voltage) signal is input from the outside of the chip through a tester having a bitmap analyzing function; the erasing function, the programming function and the reading function of the chip are tested; analysis is performed with a bitmap analysis method; in a storage unit array, rows or columns close to a defect are presented as error reading in a bitmap, and rows or columns far away from the defect are presented as correct reading in the bitmap; and a failure mechanism is analyzed and a failure position is positioned according to defect feature information reflected by the bitmap. Through improvement on a conventional failure bitmap analysis method, the HV signal is input from the outside of the chip by the tester instead of being generated by a Pump circuit module inside the chip, so that the bitmap information with defect features of the failure chip is obtained under the situation that all the storage units Read of an NVM storage array fail; limitations on the conventional bitmap analysis method are broken; and effectiveness and application range of bitmap analysis and positioning are improved greatly.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to the failure analysis of integrated circuit (IC) chip, more particularly, the failure analysis because of NVM memory cell array Erase or the abnormal whole storage-unit-failure of memory array caused of Program action HV voltage signal used is related to.
Background technology
NVM(Non-Volatile Memory, non-volatility memorizer) the common technology means of chip failure analysis use inefficacy bitmap location (Bitmap), the method is the fail address utilizing tester to obtain memory chip storage unit, set up physical address bitmap mapping, thus on chip failing the physical location of localizing faults, then carry out corresponding Analysis of Failure Mechanism and physics of failure analysis.
The method is applicable to the analysis that can be obtained storage unit feature failure address by conventional func test, but in some cases, defect may cause the key signal current potential in memory cell array overall abnormal, when making to test NVM chip, Read(reads) result be that all memory cells in whole memory cell array all lost efficacy, so just cannot obtain the validity feature address information relevant to failures position, namely the message bit pattern that effectively lost efficacy cannot be obtained, so just cannot carry out Analysis on Mechanism and physical positioning to defective locations further.
By to causing the reason that in NVM chip, all storage unit Read lost efficacy to analyze, failure cause can be divided into two kinds of main Types, a kind of is that the defect peripheral circuit region dropped on outside memory cell array causes circuit function fault, another kind is that defect drops in memory cell array region, cause the HV(Erase/Program high voltage of memory cell array) signal network potential anomalies, thus cause Erase (erasing) or the Program(programming of all storage unit) disabler.For these two kinds of failure types, adopt conventionally test bitmap analysis method to be formed and effectively for the message bit pattern analyzed, therefore can cannot apply bitmap analysis method and further Analysis of Failure Mechanism and defect location analysis are done to it.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of fail bit figure analysis method being applied to NVM chip, and it can improve validity and the scope of application of bitmap analysis location.
For solving the problems of the technologies described above, the fail bit figure analysis method being applied to NVM chip of the present invention, the method inputs HV signal from chip exterior by the tester with bitmap analysis function, the erasing of test chip, programming, read functions, analyze by bitmap analysis method, in memory cell array, row or column near defect shows as read error in bitmap, row or column away from defect shows as and reads correctly in bitmap, according to defect characteristic information analysis failure mechanism and the locate failure position of bitmap reflection.
The present invention is by improving conventional fail bit figure analysis method, HV signal is produced to change into by chip internal Pump circuit module and is inputted by chip exterior tester, thus when the whole storage unit Read of NVM storage array lost efficacy, obtain the message bit pattern with defect characteristic of chip failing, solve conventional bitmap analysis method and cannot obtain the problem with feature failure message bit pattern in the face of the whole element failure of NVM memory cell array that causes because of manufacturing defect, and substantially increase validity and the scope of application of bitmap analysis location.
Accompanying drawing explanation
Fig. 1 is chip design schematic diagram.
Fig. 2 is whole storage unit Read inefficacy bitmaps.
Fig. 3 is the normal bitmap of whole storage unit Read.
Fig. 4 is four kinds of common failure feature bitmaps.
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
For causing the latter event that in NVM chip, all storage unit Read lost efficacy; by the analysis to NVM circuit theory and considered repealed case; find that the HV voltage used in Erase/Program action is the key signal that NVM chip-stored cellular zone is subject to defective effect most; when manufacturing process defect drops on memory cell areas, usually can cause being short-circuited between HV voltage signal and other electric potential signals and producing leakage current.Simultaneously, because HV signal is boosted by inner Pump(usually) circuit module generation, its current driving ability is less, when the leakage current value that short circuit causes is greater than its driving force, just the output voltage amplitude of Pump circuit module can be dragged down, the magnitude of voltage making the voltage amplitude on the HV signal network line of the shared whole memory cell region that it exports cannot meet storage unit to carry out needed for Erase/Program operation, thus cause the Erase/Program of all storage unit in chip to lose efficacy, and then show as Read inefficacy, adopt conventional bitmap analysis method just cannot obtain reflecting the message bit pattern of defect characteristic.But, if we can be inputted the Pump HV signal of a HV signal replacement chip internal by tester from chip exterior, the driving force of the HV signal provided due to tester is better than chip internal leakage current, and its total physical efficiency of current potential be applied on HV signal network keeps its input amplitude.But due to the existence of via resistance on HV signal path in chip, short circuit leakage current is coating-forming voltage dividing potential drop on HV path, thus the closer to defect location of short circuit, its current potential is lower, the HV signal amplitude near defective locations may be made still can not to meet the requirement of Erase/Program successful operation.Go the Erase/Program/Read function of test chip in this case and adopt bitmap analysis method to analyze, then can show as the row or column Read mistake in memory cell array near defect in bitmap, away from the row/column of defect point, then Read is correct.By this method, we just can obtain the message bit pattern with defect characteristic.
Based on above-mentioned principle, the present invention proposes a kind of bitmap analysis method of improvement, comprise the following steps:
Step 1, in chip design stage, is drawn out to chip HV test pin by the HV signal that storage unit Erase/Program action uses by connecting path, as shown in Figure 1.
Step 2, carries out Erase, Program and Read operation by tester to chip failing, determines that chip functions abnormal operation is Erase or Program operation.Meanwhile, following operation acknowledgement invalidate object chip failure situation is adopted to meet two applicability features of this method:
1) in Read operation, carry out bitmap test analysis, confirm that chip has storage unit and all lost efficacy, cannot the feature of expression characteristics inefficacy bitmap, as shown in Figure 2.
2) by the HV signal voltage amplitude measurement in dysfunction course of action out, confirm that HV signal exists voltage magnitude abnormal feature on the low side.
Step 3, use usual manner to carry out storage data background to chip failing to arrange, if when namely abnormal operation object action is Erase, then conventional Program operation is carried out to chip, if when abnormal operation object action is Program, then conventional Erase operation is carried out to chip.
Step 4, after data background is provided with, a HV magnitude of voltage corresponding with design specification is applied by the HV signal testing pin of tester to chip failing, with this understanding chip is carried out to the test operation of described dysfunction action, i.e. Erase or Program, then carries out Read operation to chip and adopts bitmap method of testing to obtain message bit pattern.
Step 5, if the bitmap obtained in step 4 still cannot expression characteristics inefficacy message bit pattern, then need the additional HV magnitude of voltage described in set-up procedure 4, and the test process re-started described in step 3 and step 4, until the message bit pattern obtained can present defect speciality failure characteristics (as Fig. 4).
The concrete grammar changing additional HV voltage is: when previous bitmap is rendered as whole storage-unit-failure (as Fig. 2), then on previous HV voltage basis, increase additional HV magnitude of voltage; When previous bitmap be rendered as whole storage unit normal time (as Fig. 3), then on previous HV voltage basis, reduce additional HV magnitude of voltage.
Step 6, according to the message bit pattern (as Fig. 4) with defect characteristic obtained, carries out further Analysis of Failure Mechanism and location of losing efficacy.
Embodiment 1 embedded flash memory chip failure is analyzed
Below illustrate the practical application of the present invention in the failure analysis of embedded Flash (flash memory) chip product.
Flash storage in chip can use two HV high voltage signals in Erase/Program operation, and one is positive HV signal, and we are referred to as VPOS, and another is negative HV signal, and we are referred to as VNEG.Above-mentioned two HV signals all belong to internal chip enable signal, do not need in actual applications to be drawn out to external terminal, but carry out test analysis to realize measurability and applying bitmap analysis method of the present invention, in chip design stage, we are just connected to chip exterior test pin by connecting path, external testing pin is called after VPOS and VNEG respectively, by the break-make of gauge tap control linkage path on connecting path.
There is low yield issues in this chip product, failure testing project relevant with the Flash in chip in the fabrication process, its failure cause of Water demand.Apply bitmap analysis method of the present invention to analyze chip failing, step comprises:
The first step, the tester with bitmap analysis function is used first to carry out Erase operation (VPOS and VNEG all not impressed voltage) to the FLASH in inefficacy sample, then data Read carried out to chip and carry out conventional bitmap analysis, Read data after result display Erase are normal, illustrate that Erase operation exception does not occur.Then, Program test operation (VPOS and VNEG all not impressed voltage) is carried out to FLASH, then data Read carried out to it and carry out conventional bitmap analysis, found that all storage unit of memory array all lost efficacy, illustrating that Program operation is the abnormal operation object of chip failure.Further, the test access switch of VPOS and VNEG is opened by tester control chip, VPOS and VNEG magnitude of voltage in Program test operating procedure is measured, find that VPOS magnitude of voltage in Program operating process is lower than design specification value Vspec, belong to abnormal ranges, and VNEG magnitude of voltage is in normal range.Thus the failure characteristics confirming this chip failing meets two applicability features of the present invention, the abnormal operation simultaneously confirming chip failing occurs in Program operation.
Second step, carries out Erase test operation to chip failing, makes the data background of its NVM storer be state after Erase.
3rd step, the test access switch of VPOS is opened by tester control chip, VPOS test pin is applied to the voltage of Vspec simultaneously, carry out Program operation with this understanding, then Read carried out to chip and use the data bitmap after bitmap test acquisition Program operation, find that all storage unit Read data of storage array are all normal, illustrate that additional VPOS voltage makes fault location current potential reach the requirement of satisfied normal Program operation.
4th step, for exposing defect characteristic, after resetting memory array background is operated to chip Erase, the impressed voltage value of suitable reduction VPOS, with this understanding, Program operation is carried out to chip, then Read operation carried out to chip and obtain the data bitmap of memory array, found that bitmap presents ranks intersection failure characteristics, namely obtain effective message bit pattern with defect failure feature.It is noted that the trial the need of carrying out changing VPOS voltage, relevant to the electric leakage degree that chip failing defect causes, this step is optional step.After obtaining effective message bit pattern, then can carry out Analysis of Failure Mechanism and location according to the message bit pattern with failure characteristics obtained.
Pass through the method for the invention, the message bit pattern with defect characteristic of chip failing can be obtained when the whole storage unit Read of NVM storage array lost efficacy, breach the restriction of conventional bitmap analysis method, substantially increase validity and the scope of application of bitmap analysis location.According to our practical experience at certain NVM memory chip Product Failure Analysis, in the case adopting bitmap analysis, the growing number that conventional bitmap analysis method can be adopted to obtain validity feature message bit pattern accounts for about 40%, and the growing number of the bitmap analysis method that invention must be adopted to propose accounts for about 60%.The validity of conventional bit map method, depends on chip circuit design, laying out pattern relative to the susceptibility of defective workmanship type.Along with reducing and the application of low power dissipation design of integrated circuit minimum feature, in NVM chip, the susceptibility of HV voltage network to manufacturing defect is more and more higher, this type of ratio lost efficacy in all inefficacies of NVM chip is also more and more higher, therefore the validity of conventional bitmap analysis method will be more and more lower, and the bitmap analysis method of the improvement that the present invention proposes can improve success ratio and the scope of application of the failure analysis of NVM chip product greatly.
Claims (5)
1. be applied to the fail bit figure analysis method of NVM chip, it is characterized in that, HV signal is inputted by the tester with bitmap analysis function from chip exterior, the erasing of test chip, programming, read functions, analyze by bitmap analysis method, in memory cell array, the row or column near defect shows as read error in bitmap, row or column away from defect shows as and reads correctly in bitmap, according to defect characteristic information analysis failure mechanism and the locate failure position of bitmap reflection.
2. method according to claim 1, is characterized in that, step comprises:
1) in chip design stage, the HV signal that cell erase and programming action use is drawn out to chip HV signal testing pin by connecting path;
2) by tester, chip failing wiped, programme and read operation, determine that chip functions abnormal operation is erasing or programming operation;
3) the storage data background of chip failing is set;
4) a HV magnitude of voltage corresponding with design specification is applied by tester to the HV signal testing pin of the dysfunction action object of chip failing, with this understanding chip carry out step 2) test operation of described dysfunction action, then read operation is carried out to chip, and adopt bitmap method of testing to obtain effective message bit pattern with failure characteristics;
5) Analysis of Failure Mechanism and inefficacy positioning analysis is carried out according to the message bit pattern obtained.
3. method according to claim 2, is characterized in that, step 2) further comprising the steps:
21) in read operation, carry out bitmap test analysis, confirm chip whether have storage unit all lost efficacy, cannot the feature of expression characteristics inefficacy bitmap;
22) the HV signal voltage amplitude in measurement function abnormal operation process, confirms whether HV signal exists voltage magnitude abnormal feature on the low side.
4. method according to claim 2, it is characterized in that, between step 4) and step 5), further comprising the steps of: set-up procedure 4) described in HV magnitude of voltage, and the test process carried out described in step 3) and step 4), until obtain the message bit pattern that can present defect speciality failure characteristics.
5. method according to claim 4, is characterized in that, the method for adjustment of described HV magnitude of voltage is: when previous bitmap is rendered as whole storage-unit-failure, then on previous HV voltage basis, increase additional HV magnitude of voltage; When previous bitmap be rendered as whole storage unit normal time, then on previous HV voltage basis, reduce additional HV magnitude of voltage.
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Cited By (5)
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| CN107610738A (en) * | 2017-09-29 | 2018-01-19 | 北京中电华大电子设计有限责任公司 | A kind of efficient out of memory analysis method |
| CN109283451A (en) * | 2018-09-18 | 2019-01-29 | 电子科技大学 | A kind of integrated circuit non-defective unit detection system and method |
| TWI701429B (en) * | 2019-09-12 | 2020-08-11 | 力晶積成電子製造股份有限公司 | Defect analysis method and memory chip |
| CN113823349A (en) * | 2021-08-30 | 2021-12-21 | 全芯智造技术有限公司 | Chip failure mode determination method and terminal |
| CN114758693A (en) * | 2022-05-12 | 2022-07-15 | 西安紫光国芯半导体有限公司 | Method and device for positioning failed word line of memory array |
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| CN113823349A (en) * | 2021-08-30 | 2021-12-21 | 全芯智造技术有限公司 | Chip failure mode determination method and terminal |
| CN114758693A (en) * | 2022-05-12 | 2022-07-15 | 西安紫光国芯半导体有限公司 | Method and device for positioning failed word line of memory array |
| CN114758693B (en) * | 2022-05-12 | 2023-11-10 | 西安紫光国芯半导体有限公司 | Positioning method and positioning device for invalid word line of memory array |
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