CN109902042B - Method and system for realizing high-speed data transmission between DSP and ZYNQ - Google Patents
Method and system for realizing high-speed data transmission between DSP and ZYNQ Download PDFInfo
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- CN109902042B CN109902042B CN201910090176.3A CN201910090176A CN109902042B CN 109902042 B CN109902042 B CN 109902042B CN 201910090176 A CN201910090176 A CN 201910090176A CN 109902042 B CN109902042 B CN 109902042B
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Abstract
The invention discloses a method and a system for realizing high-speed data transmission between a DSP and a ZYNQ, comprising the ZYNQ, the DSP and a DDR memory. The ZYNQ internal configuration includes PS and PL; the DDR memory is connected with the PS; the PL internal configuration comprises a DMA unit, a control unit, a first FIFO unit and a second FIFO unit; the PS is connected with the DMA unit; the DMA unit is connected with the control unit; the control unit is connected with the first FIFO unit and the second FIFO unit; the DSP provides an EMIF interface and is connected with the first FIFO unit and the second FIFO unit; and high-speed data transmission is realized between the DSP and the ZYNQ. The invention realizes the bidirectional high-speed data transmission between the DSP and the ZYNQ through the EMIF interface and the double FIFO design, and provides an effective solution for the real-time transmission and processing of data; the method can be widely applied to transmission and processing of various real-time data.
Description
Technical Field
The invention relates to the technical field of data transmission between a DSP and ZYNQ, in particular to a method and a system for realizing high-speed data transmission between the DSP and the ZYNQ based on an EMIF interface and a FIFO.
Background
The Zynq-7000 series fully programmable System on a Chip (SoC) proposed by Xilinx corporation adopts a microprocessor plus programmable logic architecture, integrates dual cores (PS, processing System) and up to 500 or more tens of thousands of logic gate programmable logic (PL, programmable Logic) units. The software programmability of the Zynq-7000SoC series integrated ARM processor and the hardware programmability of the FPGA can realize important analysis and hardware acceleration, and meanwhile, the CPU, DSP, ASSP and mixed signal functions are highly integrated on a single device. High-speed digital signal processing (DSP, digital signal processing) enables a variety of digital signal processing algorithms to be implemented quickly. The ZYNQ+DSP architecture has been applied in a large number of high-end embedded applications such as video surveillance, automobile driver assistance, and factory automation, in combination with the advantages of both. Parallel processing of multiple processing chips is an effective solution way for improving processing capacity, so that interconnection between chips is particularly important, namely, instantaneity and effectiveness of data transmission between ZYNQ and DSP directly affect the processing capacity of the whole system.
Disclosure of Invention
Aiming at the problems, the invention provides a method for realizing high-speed data transmission between a DSP and a ZYNQ; wherein the ZYNQ internal configuration comprises PS and PL, and the PS is connected with the DDR memory; the PL internal configuration comprises a DMA unit and a control unit, and the PS is connected with the DMA unit; the DMA unit is connected with the control unit;
the method for realizing high-speed data transmission between the DSP and the ZYNQ comprises the following steps:
a first FIFO unit and a second FIFO unit are configured in PL of the ZYNQ, and the first FIFO unit and the second FIFO unit are respectively connected with the control unit; wherein the first FIFO unit is used for the ZYNQ write data and the DSP read data, and the second FIFO unit is used for the DSP write data and the ZYNQ read data;
providing an EMIF interface through the DSP, and respectively connecting the EMIF interface with the first FIFO unit and the second FIFO unit; for enabling data interaction between the DSP and the ZYNQ.
Further, the method also includes configuring a read channel and a write channel in the DMA unit, wherein the read channel is for reading data in the DDR memory and the write channel is for writing data in the DDR memory.
Further, the method further comprises configuring the PS to control the read channel and the write channel of the DMA unit to start working, and setting the address and the quantity of the data of the DDR memory read-write by the DMA unit.
Further, the ZYNQ transmitting data to the DSP comprises the steps of:
the PS of ZYNQ starts a DMA unit of PL and sets addresses and quantity of data movement, the DMA unit moves the data in the DDR memory to the control unit according to the parameters set by the PS, and the control unit writes the data into the first FIFO unit;
when the DMA unit completes data movement, the PS generates an interrupt signal and applies for interrupt to an interrupt controller of the DSP through the GPIO of the ZYNQ;
the DSP responds to the interrupt and reads data from the first FIFO unit of the ZYNQ through the EMIF interface.
Further, the DSP transmitting data to the ZYNQ includes the steps of:
the DSP writes data into a second FIFO unit of the ZYNQ through the EMIF interface;
after the DSP finishes writing data, generating an interrupt signal through the GPIO of the DSP, and requesting interrupt to the interrupt controller of the ZYNQ;
and the PS of the ZYNQ responds to the interrupt, a DMA unit of the PL is set and started, the DMA unit reads out the data in the second FIFO unit through the control unit and writes the data into the DDR memory, and after the completion, the PS is notified, and the PS reads out the data in the DDR memory.
Correspondingly, the invention also provides a system for realizing high-speed data transmission between the DSP and the ZYNQ, wherein the system comprises the ZYNQ, the DSP and the DDR memory; wherein the ZYNQ internal configuration comprises PS and PL; the DDR memory is connected with the PS; the PL internal configuration comprises a DMA unit and a control unit; the PS is connected with the DMA unit; the DMA unit is connected with the control unit;
furthermore, the PL internal configuration further comprises a first FIFO unit and a second FIFO unit; the first FIFO unit and the second FIFO unit are respectively connected with the control unit; the DSP comprises an EMIF interface which is respectively connected with the first FIFO unit and the second FIFO unit; for enabling data interaction between the DSP and the ZYNQ.
Further, the DMA unit includes a read channel and a write channel; the read channel is used for reading out data of the DDR memory, and the write channel is used for writing the data into the DDR memory; the PS can control the read channel and the write channel of the DMA unit to start working, and can set the address and the quantity of the DDR memory data read and written by the DMA unit.
Further, the physical connection between the ZYNQ and the DSP is as follows:
the write interface of the first FIFO unit is connected with the read channel of the DMA unit through the control unit and is used for writing the data of the DDR memory into the first FIFO unit;
the read interface of the second FIFO unit is connected with the write channel of the DMA unit through the control unit and is used for reading out the data in the second FIFO unit and moving the data to the DDR memory;
the EMIF interface data line provided by the DSP is respectively connected to the read interface of the first FIFO unit and the write interface of the second FIFO unit, and the control signal AOE, ARE, AWE, CE of the EMIF interface is connected with signals corresponding to the first FIFO unit and the second FIFO unit through combinational logic to realize the read-write function of the ZYNQ; the ZYNQ can realize the read-write function of the first FIFO unit and the second FIFO unit through PS control DMA unit.
Further, the interrupt controller and the GPIO in the ZYNQ are transmitted through the PS control signal, and the interrupt controller and the GPIO in the DSP are transmitted through the CPU control signal of the DSP.
Further, the ZYNQ controls the DMA unit to directly move the data in the DDR memory through the PS; the control unit writes the DMA shifted data into the first FIFO unit; the PS generates an interrupt signal after the DMA unit moves the data, and applies for interrupt to an interrupt controller of the DSP; the DSP responds to an interrupt request and reads out data from the first FIFO unit through the EMIF interface;
the DSP writes data into the second FIFO unit through the EMIF interface; after the DSP writes the data, an interrupt signal is generated, and an interrupt is applied to an interrupt controller of the ZYNQ; the PS responds to the interrupt request and starts the DMA unit to move the data in the second FIFO unit to the DDR memory through the control unit.
The invention establishes two FIFO units at the PL end of ZYNQ, the first FIFO unit is used for writing data at the ZYNQ end and reading data at the DSP end, the second FIFO unit is used for writing data at the DSP end and reading data at the ZYNQ end, and the data interaction between the ZYNQ and the DSP is completed through an EMIF interface at the DSP end; the bidirectional high-speed data transmission between the DSP and the ZYNQ is realized through the EMIF interface and the double FIFO design, and the data high-speed and full-duplex transmission is realized because different FIFO units are used for reading and writing; the chip-level interconnection between the DSP and the ZYNQ is solved, and the method can be widely applied to transmission and processing of various real-time data.
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Fig. 1 is a schematic block diagram of a method and a system for implementing high-speed data transmission between a DSP and a ZYNQ according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present embodiment provides a method for implementing high-speed data transmission between a DSP and a ZYNQ; wherein the ZYNQ internal configuration comprises PS and PL, and the PS is connected with the DDR memory; the PL internal configuration comprises a DMA unit and a control unit, wherein the PS is connected with the DMA unit, and the DMA unit is connected with the control unit; the method for realizing high-speed data transmission between the DSP and the ZYNQ comprises the following steps:
a first FIFO unit and a second FIFO unit are configured in the PL of ZYNQ, and the first FIFO unit and the second FIFO unit are respectively connected with a control unit; the first FIFO unit is used for writing data by using the ZYNQ and reading data by using the DSP, and the second FIFO unit is used for writing data by using the DSP and reading data by using the ZYNQ;
providing an EMIF interface through a DSP, and respectively connecting the EMIF interface with a first FIFO unit and a second FIFO unit of ZYNQ; the EMIF is a communication interface between the DSP and the external memory, and the DDR memory at the ZYNQ end can be accessed by the DSP by connecting the EMIF interface with pins corresponding to the first FIFO unit and the second FIFO unit, so that data interaction between the DSP and the ZYNQ is realized.
Further, the method also includes configuring a read channel and a write channel in the DMA unit, wherein the read channel is for reading data in the DDR memory and the write channel is for writing data in the DDR memory. The PS is configured to control the read channel and the write channel of the DMA unit to start working, and to set the address and the quantity of the DDR memory data read and written by the DMA unit.
The DDR memory can be selected from DDR1, DDR2 and DDR3 memories according to different bandwidth requirements. The depth and data bit width of the first FIFO unit and the second FIFO unit may be configured according to different applications, wherein the depth may be configured as 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, etc., and the data bit width may be configured as 8, 16, 32, 64, etc. The data bit width of the two channels read and write by the DMA unit can be configured to be 32 bits or 64 bits according to the bit widths of the first FIFO unit and the second FIFO unit.
Further, the transmission of data from the ZYNQ to the DSP comprises the steps of:
1. the PS of ZYNQ starts a DMA unit of PL, sets addresses and quantity of data movement, and the DMA unit moves the data in the DDR memory to a control unit according to parameters set by the PS, and the control unit writes the data into a first FIFO unit;
2. when the DMA unit completes data movement, PS generates an interrupt signal and applies for interrupt to an interrupt controller of the DSP through GPIO of ZYNQ;
3. the DSP responds to the interrupt and reads data from the first FIFO element of ZYNQ via the EMIF interface.
Further, the DSP transmitting data to ZYNQ comprises the steps of:
1. the DSP writes data into a second FIFO unit of the ZYNQ through an EMIF interface;
2. after the DSP finishes writing data, generating an interrupt signal through GPIO of the DSP, and requesting interrupt to an interrupt controller of ZYNQ;
3. and the PS of ZYNQ responds to the interrupt, a DMA unit of PL is set and started, the DMA unit reads out the data in the second FIFO unit through the control unit and writes the data into the DDR memory, the PS end is notified after the completion, and the PS reads out the data in the DDR memory.
Correspondingly, the embodiment also provides a system for realizing high-speed data transmission between the DSP and the ZYNQ, wherein the system comprises the ZYNQ, the DSP and the DDR memory; wherein the ZYNQ internal configuration comprises PS and PL; the DDR memory is connected with the PS; the PL internal configuration comprises a DMA unit, a first FIFO unit, a second FIFO unit and a control unit; the PS is connected with the DMA unit; the DMA unit is connected with the control unit; the first FIFO unit and the second FIFO unit are respectively connected with the control unit; the DSP comprises an EMIF interface which is respectively connected with the first FIFO unit and the second FIFO unit; and realizing data interaction between the DSP and the ZYNQ.
The DMA unit comprises a read channel and a write channel; the read channel is used for reading data of the DDR memory, and the write channel is used for writing the data into the DDR memory; the PS may control the read channel and the write channel of the DMA unit to start working, and may set the address and the number of the DMA unit to read and write DDR memory data. The interrupt controller and GPIO in ZYNQ are transmitted through PS control signals, and the interrupt controller and GPIO in the DSP are transmitted through CPU control signals of the DSP.
Further, the physical connection between ZYNQ and DSP is as follows:
the write interface of the first FIFO unit is connected with the read channel of the DMA unit through the control unit and is used for writing the data of the DDR memory into the first FIFO unit; the read interface of the second FIFO unit is connected with the write channel of the DMA unit through the control unit and is used for reading out the data in the second FIFO unit and moving the data to the DDR memory; the EMIF interface data line is respectively connected with the read interface of the first FIFO unit and the write interface of the second FIFO unit, and the control signal AOE, ARE, AWE, CE of the EMIF interface is connected with signals corresponding to the first FIFO unit and the second FIFO unit through combinational logic, so that the read-write function of ZYNQ is realized; the ZYNQ can realize the read-write function of the first FIFO unit and the second FIFO unit through the PS control DMA unit.
Further, ZYNQ directly moves data in the DDR memory through the PS control DMA unit; the control unit writes the data moved by the DMA into a first FIFO unit; PS generates interrupt signal after DMA unit moves data, and applies interrupt to DSP interrupt controller; the DSP responds to the interrupt request and reads out data from the first FIFO unit through the EMIF interface;
the DSP writes the data into the second FIFO unit through the EMIF interface; after the DSP writes the data, an interrupt signal is generated, and an interrupt is applied to an interrupt controller of the ZYNQ; the PS responds to the interrupt request and starts the DMA unit to move the data in the second FIFO unit to the DDR memory through the control unit.
The scheme of the embodiment establishes two FIFO units at the PL end of the ZYNQ, wherein the first FIFO unit is used for writing data at the ZYNQ end and reading data at the DSP end, the second FIFO unit is used for writing data at the DSP end and reading data at the ZYNQ end, and the data interaction between the ZYNQ and the DSP is completed through an EMIF interface at the DSP end; the bidirectional high-speed data transmission between the DSP and the ZYNQ is realized through the EMIF interface and the double FIFO design, and the data high-speed and full-duplex transmission is realized because different FIFO units are used for reading and writing; the chip-level interconnection between the DSP and the ZYNQ is solved, and the method can be widely applied to transmission and processing of various real-time data.
In addition, it should be noted that, in the embodiments of the present invention, "first" and "second" are merely for distinguishing technical terms and convenience of description, and should not be construed as limiting the embodiments of the present invention. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for realizing high-speed data transmission between DSP and ZYNQ, wherein the internal configuration of the ZYNQ comprises PS and PL, and the PS is connected with DDR memory; the PL internal configuration comprises a DMA unit and a control unit, and the PS is connected with the DMA unit; the DMA unit is connected with the control unit;
the method is characterized in that the method for realizing high-speed data transmission between the DSP and the ZYNQ comprises the following steps:
a first FIFO unit and a second FIFO unit are configured in PL of the ZYNQ, and the first FIFO unit and the second FIFO unit are respectively connected with the control unit; wherein the first FIFO unit is used for the ZYNQ write data and the DSP read data, and the second FIFO unit is used for the DSP write data and the ZYNQ read data;
providing an EMIF interface through the DSP, and respectively connecting the EMIF interface with the first FIFO unit and the second FIFO unit; the method is used for realizing data interaction between the DSP and the ZYNQ;
the ZYNQ transmitting data to the DSP comprises the following steps:
the PS of ZYNQ starts a DMA unit of PL and sets addresses and quantity of data movement, the DMA unit moves the data in the DDR memory to the control unit according to the parameters set by the PS, and the control unit writes the data into the first FIFO unit;
when the DMA unit completes data movement, the PS generates an interrupt signal and applies for interrupt to an interrupt controller of the DSP through the GPIO of the ZYNQ;
the DSP responds to the interrupt and reads out data from the first FIFO unit of the ZYNQ through the EMIF interface;
the DSP transmitting data to the ZYNQ comprises the following steps:
the DSP writes data into a second FIFO unit of the ZYNQ through the EMIF interface;
after the DSP finishes writing data, generating an interrupt signal through the GPIO of the DSP, and requesting interrupt to the interrupt controller of the ZYNQ;
the PS of ZYNQ responds to the interrupt, a DMA unit of PL is set and started, the DMA unit reads out the data in the second FIFO unit through the control unit and writes the data into the DDR memory, and after the completion, the PS is notified, and the PS reads out the data in the DDR memory;
the write interface of the first FIFO unit is connected with the read channel of the DMA unit through the control unit, and the data of the DDR memory is written into the first FIFO unit;
the read interface of the second FIFO unit is connected with the write channel of the DMA unit through the control unit, and reads out the data in the second FIFO unit and moves the data to the DDR memory;
the EMIF interface data line provided by the DSP is respectively connected to the read interface of the first FIFO unit and the write interface of the second FIFO unit, and the control signal AOE, ARE, AWE, CE of the EMIF interface is connected with signals corresponding to the first FIFO unit and the second FIFO unit through combinational logic to realize the read-write function of the ZYNQ; the ZYNQ can realize the read-write function of the first FIFO unit and the second FIFO unit through PS control DMA unit.
2. The method of achieving high speed data transfer between a DSP and a ZYNQ of claim 1, further comprising configuring a read channel and a write channel in the DMA unit, wherein the read channel is for reading data in the DDR memory and the write channel is for writing data in the DDR memory.
3. The method of achieving high speed data transfer between a DSP and a ZYNQ of claim 2, further comprising configuring PS to control the read channel and the write channel of the DMA unit to start operating and to set the address and the amount of the DMA unit to read and write the DDR memory data.
4. A system for enabling high speed data transfer between a DSP and a ZYNQ, the system comprising a ZYNQ, a DSP, and a DDR memory; wherein the ZYNQ internal configuration comprises PS and PL; the DDR memory is connected with the PS; the PL internal configuration comprises a DMA unit and a control unit; the PS is connected with the DMA unit; the DMA unit is connected with the control unit;
wherein the PL internal configuration further comprises a first FIFO element and a second FIFO element;
the first FIFO unit and the second FIFO unit are respectively connected with the control unit; the DSP comprises an EMIF interface which is respectively connected with the first FIFO unit and the second FIFO unit; for enabling data interaction between the DSP and the ZYNQ.
5. The system for achieving high-speed data transfer between a DSP and a ZYNQ of claim 4, wherein the DMA unit includes a read channel and a write channel; the read channel is used for reading out data of the DDR memory, and the write channel is used for writing the data into the DDR memory; the PS can control the read channel and the write channel of the DMA unit to start working, and can set the address and the quantity of the DDR memory data read and written by the DMA unit.
6. The system for achieving high-speed data transfer between a DSP and a ZYNQ of claim 5, wherein the physical connection between the ZYNQ and the DSP is as follows:
the write interface of the first FIFO unit is connected with the read channel of the DMA unit through the control unit and is used for writing the data of the DDR memory into the first FIFO unit;
the read interface of the second FIFO unit is connected with the write channel of the DMA unit through the control unit and is used for reading out the data in the second FIFO unit and moving the data to the DDR memory;
the EMIF interface data line provided by the DSP is respectively connected to the read interface of the first FIFO unit and the write interface of the second FIFO unit, and the control signal AOE, ARE, AWE, CE of the EMIF interface is connected with signals corresponding to the first FIFO unit and the second FIFO unit through combinational logic to realize the read-write function of the ZYNQ; the ZYNQ can realize the read-write function of the first FIFO unit and the second FIFO unit through PS control DMA unit.
7. The system for implementing high-speed data transmission between a DSP and a ZYNQ according to claim 4, wherein the interrupt controller and the GPIO in the ZYNQ are transmitted through the PS control signal, and the interrupt controller and the GPIO in the DSP are transmitted through the CPU control signal of the DSP.
8. The system for implementing high-speed data transfer between DSP and ZYNQ according to claim 7, wherein the ZYNQ controls the DMA unit to directly move data in the DDR memory through the PS; the control unit writes the DMA shifted data into the first FIFO unit;
the PS generates an interrupt signal after the DMA unit moves the data, and applies for interrupt to an interrupt controller of the DSP; the DSP responds to an interrupt request and reads out data from the first FIFO unit through the EMIF interface;
the DSP writes data into the second FIFO unit through the EMIF interface; after the DSP writes the data, an interrupt signal is generated, and an interrupt is applied to an interrupt controller of the ZYNQ; the PS responds to the interrupt request and starts the DMA unit to move the data in the second FIFO unit to the DDR memory through the control unit.
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| CN110579642B (en) * | 2019-09-20 | 2020-11-13 | 哈尔滨工业大学 | Zynq-based airborne alternating current multi-path parallel acquisition and processing system |
| CN111506249B (en) * | 2020-04-23 | 2023-03-24 | 珠海华网科技有限责任公司 | Data interaction system and method based on ZYNQ platform |
| CN112711925B (en) * | 2021-02-10 | 2022-10-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Virtual EMIF bus DSP software design method |
| CN113255254B (en) * | 2021-04-22 | 2024-01-19 | 江苏省电力试验研究院有限公司 | Controller of DSP and ZYNQ architecture and data transmission design method |
| CN115051881B (en) * | 2022-06-07 | 2023-10-31 | 北京计算机技术及应用研究所 | Gigabit Ethernet implementation method based on DSP28346 and ZYNQ double main chips |
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