CN114696829B

CN114696829B - Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Info

Publication number: CN114696829B
Application number: CN202011580091.2A
Authority: CN
Inventors: 杨泽坤; 杨培; 杨华中; 李学清; 殷秀梅
Original assignee: Beijing Tebang Microelectronic Technology Co ltd; Tsinghua University
Current assignee: Beijing Tebang Microelectronic Technology Co ltd; Tsinghua University
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2024-07-02
Anticipated expiration: 2040-12-28
Also published as: CN114696829A

Abstract

The present disclosure relates to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter, the circuit being a stage of the pipeline analog-to-digital converter, the circuit comprising: the digital-analog conversion SADC module, the digital-analog conversion and amplification MDAC module and the digital reconstruction module are arranged in the digital-analog conversion module SADC module, wherein the digital-analog conversion SADC module, the digital-analog conversion and amplification MDAC module and the digital reconstruction module comprise a double comparator component, the double comparator component is used for outputting a judging result signal of the double comparator when the difference value between a first analog signal and a first reference electric signal is in a preset range, generating a first electric signal sequence, and gating the double comparator by using the first electric signal sequence so that the MDAC module outputs a first residual difference signal according to the comparison result of the gated comparator; and the digital reconstruction module is used for digitally reconstructing the digital output signal. The embodiment of the disclosure can respond to the change of the gain error in real time on the premise of not increasing the swing amplitude, and timely adjust the working state of the circuit, so that the inter-stage gain error is always controlled within a certain range, and an accurate digital output signal is output.

Description

Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter.

Background

The pipelined Analog-to-Digital Converter (ADC) is made up of several stages of functionally similar modules, each comprising a Sub Analog-to-Digital Converter (SADC) module and a digital-to-Analog Converter (MDAC, multiplying Digital-to-Analog Converter) module, etc. In the pipeline analog-to-digital converter of the related art, the MDAC module has nonlinear gain distortion, so that the accuracy of the ADC of the related art is lower.

Disclosure of Invention

In view of this, the present disclosure proposes an analog-to-digital conversion circuit, which is a stage of a pipeline analog-to-digital converter, for performing analog-to-digital conversion on an input analog signal to obtain a digital output signal, the circuit comprising: the digital-to-analog conversion system comprises a sub-digital conversion SADC module, a digital-to-analog conversion and amplification MDAC module and a digital reconstruction module, wherein the SADC module is used for carrying out analog-to-digital conversion on an input first analog signal to obtain a first digital signal; the MDAC module is used for generating a residual signal by utilizing the first digital signal and the first analog signal, wherein: the SADC module comprises a multipath comparison unit, any path of the multipath comparison unit comprises a double comparator assembly, the double comparator assembly comprises a double comparator, the double comparator is used for judging the range of a first analog signal, and the double comparator assembly is used for: outputting a judging result signal of the double comparators when the difference value between the first analog signal and the first reference electric signal is in a preset range, wherein the judging result signal indicates whether the comparison results of the double comparators are the same, generating and outputting a first electric signal sequence according to the judging result signal, and gating one of the double comparators by using the first electric signal sequence so that the MDAC module outputs a first residual signal according to the comparison result of the gated comparator; the digital reconstruction module is used for: and receiving the judgment result signal, the first electric signal sequence, the digital signal quantized by the post-stage circuit of the first residual signal and the digital output signal, digitally reconstructing the digital output signal by using the judgment result signal, the first electric signal sequence and the digital signal quantized by the post-stage circuit of the first residual signal, and outputting the reconstructed digital output signal.

In one possible implementation manner, the dual comparator includes a first comparator and a second comparator, the equivalent reference electrical signal of the first comparator is the sum of the first reference electrical signal and a first threshold electrical signal, the equivalent reference electrical signal of the second comparator is the sum of the first reference electrical signal and a second threshold electrical signal, and the input signals of the first comparator and the second comparator are the first analog signals, wherein the preset range is determined according to the first threshold electrical signal and the second threshold electrical signal.

In one possible implementation manner, if the codeword of the first electrical signal sequence corresponding to the current sampling period is at a high level, the dual comparator component is configured to gate the first comparator, perform digital-to-analog conversion using the comparison result output by the first comparator, and output the gating result of gating the first comparator to the SDAC units in the MDAC module; if the comparison results of the first comparator and the second comparator are detected to be the same in the current holding stage, the dual comparator component keeps gating the first comparator in the next adjacent sampling period and outputs the gating result of gating the first comparator to the SDAC units.

In one possible implementation, if it is detected in the current hold phase that the comparison results of the first comparator and the second comparator are different, at the beginning of the next sampling phase, the dual comparator component is configured to update the first electrical signal sequence with the determination result signal, gate the first comparator or the second comparator with the updated first electrical signal sequence, and output a gate result to the SDAC unit, where, when the codeword of the first electrical signal sequence is at a low level in the next sampling period, the dual comparator component is configured to gate the second comparator to output the comparison result of the second comparator, perform digital-to-analog conversion with the comparison result output by the second comparator, and output the gate result of gating the second comparator to the SDAC unit.

In one possible implementation manner, the dual comparator assembly includes a comparison and judgment unit, wherein the comparison and judgment unit is electrically connected to the first comparator and the second comparator, and is configured to determine whether the comparison results of the first comparator and the second comparator are the same according to the output results of the first comparator and the second comparator, and output the judgment result signal.

In one possible implementation manner, the circuit includes a first control unit, where the first control unit includes a trigger and a linear feedback shift register, where the trigger is configured to output a clock signal after sampling an output signal of the comparison and judgment unit, and the linear feedback shift register is configured to generate a first electrical signal sequence according to the clock signal, where the dual comparator component is further configured to gate the first comparator or the second comparator with the first electrical signal sequence, and output a gate result to a sub digital-to-analog conversion SDAC unit in the MDAC module.

In a possible implementation manner, the dual comparator assembly includes a multiplexing unit, wherein the multiplexing unit is electrically connected to the first comparator and the second comparator, and is configured to gate the result of the first comparator or the second comparator according to the first electric signal sequence.

In one possible implementation, the digital reconstruction module includes: the first error calculation unit is used for carrying out correlation operation on the first electric signal sequence, the judging result signal and the digital signal of the first residual error signal after the post-quantization to obtain a first error estimated value, wherein the first error estimated value is a gain error between first steps; the first digital reconstruction unit is electrically connected with the first error calculation unit and is used for digitally reconstructing the digital output signal by utilizing the first error estimation value and outputting the reconstructed digital output signal.

In one possible implementation manner, the circuit further comprises a third comparator and a fourth comparator, wherein an equivalent reference electric signal of the third comparator is a sum of a second reference electric signal and a third threshold electric signal, an equivalent reference electric signal of the fourth comparator is a sum of the second reference electric signal and a fourth threshold electric signal, and inputs of the third comparator and the fourth comparator are the first analog signals.

In a possible implementation manner, the MDAC module includes a sub digital-to-analog conversion SDAC unit, an adding unit and an amplifying unit, the SDAC unit is configured to convert the first digital signal to obtain a second analog signal, the adding unit is configured to perform a difference operation on the first analog signal and the second analog signal and output the difference operation to the amplifying unit to amplify the difference signal, so as to obtain the residual signal, and the MDAC module further includes a first switch, a second switch, a third switch, and a first capacitor, where: the first end of the first switch receives a first reference electric signal, the second end of the first switch is electrically connected to the first end of the first capacitor, the first end of the second switch receives a second reference electric signal, the second end of the second switch is electrically connected to the first end of the first capacitor, wherein the first reference electric signal is positive, the second reference electric signal is negative, the first end of the third switch receives a common mode electric signal, the second end of the third switch is electrically connected to the first end of the first capacitor, the second end of the first capacitor is electrically connected to the adding unit, and the SADC module is further used for controlling the conducting states of the first switch, the second switch and the third switch according to the comparison results of the third comparator and the fourth comparator and/or the second electric signal sequence, so that the MDAC module outputs a second residual difference signal according to the comparison results of the third comparator and the fourth comparator.

In one possible implementation manner, the controlling the conducting states of the first switch, the second switch and the third switch according to the comparison result of the third comparator and the fourth comparator includes: and when the comparison results of the third comparator and the fourth comparator are the same, the first switch and the second switch are controlled to be disconnected, and the third switch is controlled to be connected.

In one possible implementation manner, the controlling the conducting states of the first switch, the second switch and the third switch according to the comparison result of the third comparator and the fourth comparator includes: and when the comparison results of the third comparator and the fourth comparator are different, controlling the third switch to be turned off, and controlling the first switch or the second switch to be turned on according to a second electric signal sequence.

In one possible implementation manner, when the comparison results of the third comparator and the fourth comparator are different, controlling the first switch or the second switch to be turned on according to a second electric signal sequence includes: when the comparison results of the third comparator and the fourth comparator are different, and the current code word of the second electric signal sequence is at a high level, the first switch is controlled to be turned on, and the second switch is controlled to be turned off; or when the comparison results of the third comparator and the fourth comparator are different, and the current code word of the second electric signal sequence is in a low level, the first switch is controlled to be turned off, and the second switch is controlled to be turned on.

In one possible implementation, the digital reconstruction module includes: a second error calculation unit configured to determine a second error estimation value and a third error estimation value by using a first determination result signal of the first comparator and the second comparator, a second determination result signal of the third comparator and the fourth comparator, the first electrical signal sequence, the second electrical signal sequence, the first determination result signal indicating a digital signal in which the first residual signal and the second residual signal are quantized in a latter stage when a comparison result of the first comparator and the second comparator is different, and the second determination result signal indicating a digital signal in which the second residual signal is quantized in a latter stage when a comparison result of the third comparator and the fourth comparator is different, the second error estimation value being a first-stage gain error and a third-stage gain error when a third-stage gain error is calculated; and the second digital reconstruction unit is used for digitally reconstructing the digital output signal by using the second error estimated value, the third error estimated value and the digital output signal to obtain a reconstructed digital output signal.

In one possible implementation manner, the MDAC module further includes a second capacitor, a dual comparator corresponding to the second capacitor, a third capacitor, and a dual comparator corresponding to the third capacitor, where the MDAC module is configured to digitally reconstruct the digital output signal according to the digital signal quantized by the third residual signal and the digital signal quantized by the fourth residual signal quantized by the later stage by using the second capacitor, the dual comparator corresponding to the second capacitor, the third capacitor, and the dual comparator corresponding to the third capacitor in different comparison periods, and obtain a third residual signal and a fourth residual signal by using comparison results output by the comparators selected by the third electric signal sequence and the fourth electric signal sequence.

According to another aspect of the disclosure, a pipelined analog-to-digital converter is provided, each stage of which includes the analog-to-digital conversion circuit.

Through the circuit, when the difference value between the first analog signal and the first reference electric signal is in the preset range, the embodiment of the disclosure can utilize the first electric signal sequence to gate one of the double comparators, so that the MDAC module outputs a first residual difference signal according to the comparison result of the gated comparator, and uses the digital signal corresponding to the first residual difference signal to digitally reconstruct the digital output signal, so that the working state of the correction circuit can be timely adjusted in response to the change of the gain error on the premise of not increasing the swing amplitude, the inter-stage gain error is always controlled in a certain range, and an accurate digital output signal is output.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of the digital output curve of the current stage, the residual curve, and the overall digital output curve of the pipeline ADC in the ideal case of the subsequent stage when calculating the gain error between the first stages according to one embodiment of the present disclosure.

Fig. 3 is a schematic diagram of the digital output curves of the current stage, the residual curves, and the overall digital output curves of the pipeline ADC in the ideal case of the subsequent stage when calculating the gain error between the third stages according to an embodiment of the disclosure.

Fig. 4a shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Fig. 4b shows a schematic diagram of a dual comparator assembly in an analog to digital conversion circuit according to an embodiment of the present disclosure.

Fig. 4c shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Fig. 4d shows a schematic diagram of a first control unit in an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a dual comparator detecting the amplitude of an input signal according to an embodiment of the present disclosure.

Fig. 6 shows an ADC workflow diagram according to an embodiment of the disclosure.

Fig. 7 shows a schematic diagram of a select comparator according to an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Referring to fig. 1, fig. 1 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure.

The analog-to-digital conversion circuit 10 may include: the sub-analog-digital conversion (SADC) module 101, the input end of the sadc module 101 receives the input signal Vin, and the output end outputs an analog-digital converted digital signal D1; wherein if not, vin is an analog signal provided by the previous stage analog-to-digital conversion circuit; the digital-to-analog conversion and amplification (MDAC) module 102, wherein the MDAC module 102 is connected to the SADC module 101, one input terminal inputs the initial signal Vin, the other input terminal inputs the digital signal D1, and the output terminal outputs the residual signal Vres.

In one possible implementation, as shown in FIG. 1, the MDAC module 102 may include a Sub Digital-to-Analog Converter (SDAC), an adder, and a residual amplifier AMP. SDAC, wherein the input end of the adder is input with a digital signal D1, and the output end of the adder is connected with an input end of the adder; the other input end of the adder inputs an initial signal Vin, and the output end of the adder is connected with the input end of the residual amplifier AMP; the output terminal of the residual amplifier AMP outputs a residual signal Vres.

For example, the input signal Vin enters the SADC module 101 and the MDAC module 102 at the same time, and coarse quantization (i.e., preliminary analog-to-digital conversion) is performed in the SADC module 101, for example, 1-4 bits are quantized, and the quantized result (digital signal D1) is sent to the MDAC module 102. The MDAC module 102 converts the output of the SADC module 101 into different reference electrical signals, subtracts the input signal Vin from the reference electrical signals, amplifies the subtracted input signal Vin by a Gain unit Gain to obtain a residual difference signal Vres (Residue Voltage), and sends the residual difference signal Vres (Residue Voltage) to the next stage for processing.

It should be noted that, the electrical signals mentioned in the various embodiments of the present disclosure may include voltage signals and current signals, and the electrical signals are described below as exemplary voltage signals. In one example, the Gain unit Gain may include an operational amplifier OPA. In one example, the residual amplifier AMP may be of a single-ended gain type, a differential type. The following description takes differential types as examples. Ideally, the output of the residual amplifier is: v _res＝G*(V_in -D), where V _res is the output residual, D is the result of converting the SADC digital output to an analog signal, G represents the ideal gain of the residual amplifier, where the ideal gain G can be set toB ₁ is the stage valid bit.

However, in a practical circuit, there are cases where the residual amplifier has first-order gain distortion and high-order nonlinear distortion, i.e., there is an inter-stage gain error. Let the first and third order gain errors (IGE, inter-STAGE GAIN error) be k ₁、k₃, respectively, and the residual amplifier output can be expressed as:

Referring to fig. 2, fig. 2 is a schematic diagram showing a digital output curve of a current stage, a residual curve, and a digital output curve of a pipeline ADC as a whole in an ideal case of a subsequent stage when calculating a gain error between first stages according to an embodiment of the disclosure.

Referring to fig. 3, fig. 3 is a schematic diagram showing a digital output curve of a current stage, a residual curve, and a digital output curve of a pipeline ADC as a whole in an ideal case of a subsequent stage when calculating a gain error between third stages according to an embodiment of the disclosure.

The left diagrams of fig. 2 and fig. 3 show the digital output curve and the residual curve of the current stage when the gain error exists, and the right diagrams of fig. 2 and fig. 3 show the digital output curve of the whole pipeline ADC in the ideal case of the later stage.

The ideal transmission characteristic curve (comprising ideal residual and ideal output) is shown by a dotted line, the digital output curve with interstage gain error and residual curve are shown by dark and light solid lines in the left graph respectively, and the solid line in the right graph of the digital output curve of the whole pipeline ADC. It can be seen that the presence of the interstage gain error causes the residual curve to shift in relation to the signal, resulting in degradation of ADC performance.

Therefore, it is desirable to accurately evaluate and compensate for the inter-stage gain error at as little cost as possible to ensure ADC accuracy.

However, the related art directly improves the gain and linearity of the residual amplifier, which significantly increases the cost of the analog circuit, and increases the design complexity, power consumption, size, and the like. Analog correction schemes often require changing the original analog circuit structure of the ADC, and the correction effect is susceptible to PVT (process, supply voltage, temperature, process, voltage, temperature). Some digital calibration schemes may cause the swing of the input signal of the differential amplifier to increase, even saturate the differential amplifier, and the error occurs. In the existing technical scheme, the scheme capable of controlling the swing amplitude cannot effectively calibrate the gain error between the third-order steps, and the scheme capable of performing the third-order calibration often leads to remarkable increase of the swing amplitude.

The present disclosure provides a circuit for measuring and calibrating inter-stage gain errors in real time, which can measure first-order and third-order gain errors of a residual amplifier in real time (or near real time) on the premise of not increasing swing amplitude, and when the inter-stage gain errors are found to change, the working state of a correction circuit is timely adjusted, so that the inter-stage gain errors are always controlled within a certain range.

Referring to fig. 4a, fig. 4a shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure.

The circuit is a stage of a pipeline analog-to-digital converter, and is configured to perform analog-to-digital conversion on an input analog signal to obtain a digital output signal D _out,1, and generate a residual signal V _res,1 to a post-stage analog-to-digital converter, and the circuit includes: the digital-to-analog conversion SADC module 101, the digital-to-analog conversion and amplification MDAC module 102 and the digital reconstruction module 103, wherein the SADC module 101 is used for carrying out analog-to-digital conversion on the input first analog signal Vin to obtain a first digital signal; the MDAC module 102 is configured to generate a residual signal using the first digital signal and the first analog signal, wherein:

the SADC module 101 includes a multiple-path comparing unit, any path of the multiple-path comparing unit includes a dual comparator assembly, the dual comparator assembly includes a dual comparator, the dual comparator is used for judging a range of the first analog signal, wherein the dual comparator assembly is used for:

outputting a judging result signal of the double comparator when the difference value between the first analog signal Vin and the first reference electric signal is in a preset range, wherein the judging result signal indicates whether the comparison result of the double comparator is the same,

Generating and outputting a first electric signal sequence according to the judging result signal,

Gating one of the dual comparators with the first electrical signal sequence such that the MDAC module 102 outputs a first residual signal V _res,1 according to a comparison result of the gated comparator;

the digital reconstruction module 103 is configured to:

And reconstructing the digital output signal D _out,1 by using the judgment result signal, the first electric signal sequence and the digital signal D _be obtained by quantizing the first residual difference signal by a later-stage circuit, and outputting a reconstructed digital output signal D _out.

Through the circuit, when the difference value between the first analog signal and the first reference electric signal is in the preset range, the embodiment of the disclosure can utilize the first electric signal sequence to gate one of the double comparators, so that the MDAC module outputs a first residual error signal according to the comparison result of the gated comparator, and reconstruct the digital output signal by utilizing the judgment result signal, the first electric signal sequence and the digital signal of the first residual error signal, so that the working state of the correction circuit can be timely adjusted in response to the change of the gain error in a near real-time manner on the premise of not increasing the swing amplitude, the inter-stage gain error is always controlled in a certain range, and an accurate digital output signal is output.

It should be noted that the analog-to-digital conversion circuit may be in a differential form, and embodiments of the present disclosure are described by way of example in a single-ended form.

The analog-to-digital conversion circuit of the embodiment of the present disclosure may be applied to various types of terminals, servers, etc. that need analog-to-digital conversion, where the terminals are also called User Equipment (UE), mobile Station (MS), mobile Terminal (MT), etc. that are devices that provide voice and/or data connectivity to a user, such as a handheld device with a wireless connection function, a vehicle-mounted device, etc. Currently, some examples of terminals are: a mobile phone, a tablet, a notebook, a palm, a mobile internet device (mobile internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an augmented reality (augmentedreality, AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned (selfdriving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (SMART GRID), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (SMART CITY), a wireless terminal in smart home (smart home), a wireless terminal in the internet of vehicles, and the like.

The analog-to-digital conversion circuit of the embodiment of the disclosure can calibrate the gain error between first-order steps and the gain error between third-order steps, and the following exemplary description of possible implementation manners of calibration is provided.

Embodiments of the present disclosure may determine a gain error between first steps and calibrate the gain error between first steps, and exemplary description of calibration procedures and principles follows.

Referring to fig. 4b together, fig. 4b is a schematic diagram illustrating a dual comparator assembly in an analog-to-digital conversion circuit according to an embodiment of the disclosure.

Referring to fig. 4c together, fig. 4c is a schematic diagram illustrating an analog-to-digital conversion circuit according to an embodiment of the disclosure.

In one possible embodiment, as shown in fig. 4b and fig. 4c, any one of the multiple comparing units may include a dual comparator, where the dual comparator may include a first comparator cmpA and a second comparator cmpB (in dual-comparator assembly 1), the equivalent reference electric signal of the first comparator cmpA is equal to or similar to the sum of the first reference electric signal and the first threshold electric signal (in an allowable error range), the equivalent reference electric signal of the second comparator cmpB is equal to or similar to the sum of the first reference electric signal and the second threshold electric signal (in an allowable error range), and the input signals of the first comparator cmpA and the second comparator cmpB are the first analog signals, where the preset range is determined according to the first threshold electric signal and the second threshold electric signal.

The first threshold electrical signal and the second threshold electrical signal may be equal or different, and may be positive or negative, which is not limited in this embodiment of the disclosure.

In one example, the preset range may be an electrical signal interval determined at the first threshold electrical signal and the second threshold electrical signal.

It should be noted that the embodiments of the present disclosure will be exemplarily described with respect to the equivalent reference electric signal as a constant value, however, it should be understood that in an actual circuit, the equivalent reference electric signal of the comparator is difficult to set as a constant value due to environmental noise, process factors, and the like.

In one example, the reference electrical signals of the first comparator cmpA, the second comparator cmpB may be set by:

Setting reference electric signals of the first comparator cmpA and the second comparator cmpB to be the first reference electric signal, and setting Offset electric signals (deviation of the reference electric signals of the comparators from a design value) of the first comparator cmpA and the second comparator cmpB to be opposite, wherein the magnitude of the Offset electric signals can be the first threshold electric signal or the second threshold electric signal; or (b)

Setting reference electric signals of the first comparator cmpA and the second comparator cmpB to be the first reference electric signal, and realizing that the equivalent reference electric signal of the first comparator cmpA is equal to or similar to the sum of the first reference electric signal and the first threshold electric signal and the equivalent reference electric signal of the second comparator cmpB is equal to or similar to the sum of the first reference electric signal and the second threshold electric signal by adjusting noise of the first comparator cmpA and the second comparator cmpB;

The method combines the Offset setting and the noise adjusting to realize that the equivalent reference electric signal of the first comparator cmpA is equal to or similar to the sum of the first reference electric signal and the first threshold electric signal, and the equivalent reference electric signal of the second comparator cmpB is equal to or similar to the sum of the first reference electric signal and the second threshold electric signal; or (b)

The reference electrical signal of the first comparator cmpA is directly set to be the sum of the first reference electrical signal and the first threshold electrical signal, and the reference electrical signal of the second comparator cmpB is directly set to be the sum of the first reference electrical signal and the second threshold electrical signal.

Of course, the above description of setting the equivalent reference electrical signal of the comparator is exemplary, and embodiments of the present disclosure may also set the equivalent reference electrical signal of the comparator in other ways.

In one example, the first comparator cmpA, the second comparator cmpB may be obtained by replacing a comparator in the comparing unit, for example, the reference electrical signal of the original comparator is 1/16, and the embodiments of the present disclosure may replace the original comparator with the first comparator cmpA, the second comparator cmpB having equivalent reference electrical signals of 1/16-0.005V and 1/16+0.005V, respectively. Of course, a comparator may be added to form a dual comparator with the original comparator to obtain the first comparator cmpA and the second comparator cmpB, for example, the original comparator may be used as the first comparator cmpA, the second comparator cmpB may be added, and the equivalent reference electric signals of the first comparator cmpA and the second comparator cmpB are respectively set to 1/16-0.005V and 1/16+0.005v, in this example, the first reference electric signal is 1/16V, the first threshold electric signal is-0.005V, the second threshold electric signal may be 0.005V, and the preset range determined based on the first threshold electric signal and the second threshold electric signal may be [ -0.005v,0.005v ].

The embodiment of the disclosure can realize the detection of the amplitude of the input signal by using the double-comparator circuit, and can judge whether the amplitude of the input signal is in a preset range or not according to the comparison results of the two comparators.

In one example, the disclosed embodiments are illustratively described in terms of a 4-bit ADC (3-bit valid bit), and for a 4-bit ADC, SADC module 101 may include 16 comparators (16 comparison units) with reference electrical signals of 15/16, 13/16, 11/16, 9/16, 7/16, 5/16, 3/16, 1/16, respectively. The embodiment of the disclosure can replace any one of the comparators by the first comparator and the second comparator so as to detect the range of the input signal, and for convenience of representation, we take a comparator with a reference electric signal of 1/16 as an example for analysis.

In one example, to improve the accuracy of the digital signal reconstruction, the disclosed embodiments may constrain the first reference electrical signal to ± a number as small as possible (first threshold), that is to say the input signal, to a range as small as possible, in one example, the first threshold may be set to 0.005V.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a dual comparator detecting an input signal amplitude according to an embodiment of the disclosure.

In one example, as shown in FIG. 5, the equivalent reference signals of the first comparator cmpA and the second comparator cmpB are respectively 1/16-0.005V and 1/16+0.005V, and the comparison results are respectively denoted as Da and Db. The comparison results of the first comparator cmpA and the second comparator cmpB are the same when the input signal amplitude is less than 1/16-0.005 or greater than 1/16+0.005, and the comparison results of the first comparator cmpA and the second comparator cmpB are different when the input signal amplitude is between 1/16-0.005 and 1/16+0.005. That is, when the first comparator cmpA and the second comparator cmpB quantize a certain input signal, the input signal amplitude can be considered to be in the vicinity of 1/16 if the comparison result da+notedb. Specifically, for an input signal of less than 1/16-0.005, both the first comparator cmpA and the second comparator cmpB consider it to be less than their own comparison threshold; for an input signal greater than 1/16+0.005, both the first comparator cmpA and the second comparator cmpB consider it to be greater than their own comparison threshold, whereas when the input signal is between 1/16+0.005, the comparator with reference to the electrical signal 1/16-0.005 considers the input signal to be greater than the comparison threshold, and the comparator with reference to the electrical signal 1/16+0.005 considers the input signal to be less than the comparison threshold.

It should be noted that in each example of the embodiments of the present disclosure, the unit of the electrical signal is volt (V), and in other embodiments, mV or other electrical signal units may be used, which is not limited to the embodiments of the present disclosure.

In the disclosed embodiment, the detection and determination of the inter-stage gain error is implemented by using a PN Sequence (Pseudo-noise Sequence) gating comparator which is not related to the signal and then using the PN Sequence to correlate with the digital signal output from the subsequent stage. Since the inter-stage gain error is multiplicative, the PN sequence inserted between SADC and SDAC (for example, the insertion of an electrical signal sequence, that is, gating the comparator with the electrical signal sequence, and performing subsequent conversion and operation with the comparison result of the gated comparator) is converted into an analog electrical signal by the MDAC module and amplified to carry error information, and how to insert the PN sequence and how to solve the error information through the post-stage output will be described in detail later.

The PN sequence is inserted into the residual error by switching the output result of the comparator (i.e. a comparison result is output by gating one of the double comparators with the PN sequence) is described below.

In one possible implementation manner, if the codeword of the first electrical signal sequence corresponding to the current sampling period is at a high level, the dual comparator component gates the first comparator, uses the comparison result output by the first comparator as the output result of the whole of the first comparator and the second comparator, so as to perform digital-to-analog conversion, and outputs the gating result of the gated first comparator to the SDAC units in the MDAC module;

if the comparison results of the first comparator and the second comparator are detected to be the same in the current holding stage, the dual comparator component keeps gating the first comparator in the next adjacent sampling period and outputs the gating result of gating the first comparator to the SDAC units.

In a possible implementation, if it is detected in the current hold phase that the comparison results of the first comparator and the second comparator are different, at the beginning of the next sampling phase, the dual comparator component is configured to update the first electrical signal sequence with the determination result signal, gate the first comparator or the second comparator with the updated first electrical signal sequence, output the gate result to the SDAC unit,

When the code word of the first electric signal sequence is at a low level in the next sampling period, the dual comparator component is used for gating the second comparator to output a comparison result of the second comparator, performing digital-to-analog conversion by using the comparison result output by the second comparator, and outputting a gating result for gating the second comparator to the SDAC units.

For example, for a pipelined ADC with a first stage of 4-bit (3-bit valid bit), the comparator with the equivalent reference signal 1/16 is replaced by the first comparator cmpA and the second comparator cmpB with the equivalent reference signal 1/16±0.005, the PN sequence is used as the strobe signal in one comparison period, the comparison result of one of the first comparator cmpA and the second comparator cmpB is selected as the output result of the dual comparator (i.e. the output result of the original comparator with the reference signal 1/16), and SDAC is combined with the output result of the dual comparator and the comparison result of other comparison units to perform digital-analog conversion.

In one example, when PN >0 (PN is high), the first comparator cmpA with the equivalent reference electrical signal of 1/16+0.005 is gated, at which time the output da=0 of SADC; when PN <0 (PN is low), the second comparator cmpB with 1/16-0.005 of equivalent reference signal is gated, and the output db=1/8 of SADC (SADC of 3-bit effective value, 1/16 left is 0 and right is 1/8).

Thus, the equivalently inserted PN sequence can be expressed as:

Wherein S is a positive integer, PN _S represents an electrical signal sequence inserted into the residual signal, and PN represents the first electrical signal sequence.

Referring to fig. 6, fig. 6 shows a schematic diagram of an ADC workflow according to an embodiment of the disclosure.

Referring to fig. 7, fig. 7 shows a schematic diagram of a selection comparator according to an embodiment of the disclosure.

In one possible implementation, the timing control for implementing the above process is shown in fig. 6 and 7.

In one example, fig. 6 shows the working flow of the pipeline ADC in one clock cycle, which is divided into two sections of sampling and holding, wherein the input signal in the holding stage is quantized into a digital signal through a SADC module, then converted into an analog signal through a SDAC module, and the difference between the input signal and the analog signal obtained by conversion of SDAC is amplified by a residual amplifier to obtain a residual and sent to a later stage. The digital outputs of the dual comparator first comparator cmpA and the second comparator cmpB may be used as a basis for determining the range of the input signal.

In one example, fig. 7 illustrates a timing diagram of the operation of an ADC with the switching of the first comparator cmpA and the second comparator cmpB controlled by a PN sequence. The codeword of the PN sequence of the ith beat is denoted by PN [ i ], where as shown at the top of fig. 7, the PN sequence includes PN [0] =1 (high level), PN [1] = -1 (low level), PN [2] =1 … …, and the like. In the sampling stage, the corresponding comparator can be gated according to the code word PN [ i ] of the PN sequence as the digital output of the whole, in the holding stage, whether the comparison results Da and Db of the first comparator cmpA and the second comparator cmpB are equal or not is judged, if so, the gating result controlled by PN [ i ] is still adopted in the next sampling stage, and at the moment, the digital output of the whole is the same no matter which one of the first comparator cmpA and the second comparator cmpB is gated; if not, it is equivalent to inserting the first electrical signal sequence.

In one example, the post-digital output signal of the corresponding comparator (the post-digital output signal of the current-stage analog-to-digital conversion circuit) that is gated according to PN [ i ] can be taken out as a basis for the correlation inter-stage gain error by the digital reconstruction module, and gating in the first comparator cmpA and the second comparator cmpB is performed according to the codeword PN [ i+1] of the next beat of the PN sequence in the next sampling stage. For example, as shown in fig. 7, PN [0] =1, the first comparator cmpA is gated in the sampling stage, if the result of the two comparators is detected to be equal (da=db) in the holding stage, the next sampling stage still controls to gate the first comparator cmpA by PN [0] =1, and if da++db is detected in the holding stage (the comparison result of the two comparators is different), then the digital output signal of this beat is taken out to be correlated to determine the gain error, the first electric signal sequence is updated by using the determination result signal, the first comparator or the second comparator is gated by using the updated first electric signal sequence, the gating result is output to the SDAC unit, for example, the next codeword of the updated PN sequence is switched, the second comparator cmpB is controlled to gate by PN [1] =0, and the operation is continued.

In one example, the first comparator cmpA or the second comparator cmpB may be gated according to the positive and negative of the current codeword of the PN sequence, and when detecting that the comparison results of the first comparator cmpA and the second comparator cmpB are different, the dual comparator assembly 1 updates the first electrical signal sequence PN ₁ with the determination result signal, gates the first comparator cmpA or the second comparator cmpB with the updated first electrical signal sequence PN ₁, outputs the gating result to the SDAC unit, i.e., determines the positive and negative of the updated first electrical signal sequence PN ₁ and selects the corresponding comparator, for example, when the codeword of the first electrical signal sequence PN ₁ is at a low level in the next sampling period, the dual comparator assembly 1 is configured to gate the second comparator cmpB to output the comparison result of the second comparator cmpB, perform digital-analog conversion with the comparison result output by the second comparator cmpB, and output the gating result of the second comparator cmpB to the gating unit SDAC.

In one possible implementation, as shown in fig. 4c, the dual comparator assembly may include a comparison decision unit 1010, wherein,

The comparing and judging unit 1010 is electrically connected to the first comparator cmpA and the second comparator cmpB, and is configured to determine whether the comparison results of the first comparator cmpA and the second comparator cmpB are the same according to the output results of the first comparator cmpA and the second comparator cmpB, and output a judging result signal EN ₁.

In one example, the comparison and judgment unit 1010 may be implemented by exclusive or gate XOR, which performs an exclusive or operation on the output results of the first comparator cmpA and the second comparator cmpB, and judges whether the comparison results are the same according to the operation results.

In one example, the comparing and judging unit 1010 may further judge whether the comparison results of the first comparator cmpA and the second comparator cmpB are the same according to the output results of the two comparators, for example, if the comparison results of the two comparators are 1 or 0, the comparison results of the two comparators are the same, and if the output results of the first comparator cmpA and the second comparator cmpB are 1 and the output results of the two comparators are 0, the comparison results of the two comparators are different.

In one example, when the comparison determination unit 1010 obtains the determination result signal, the determination result signal EN ₁ may be transmitted to the digital reconstruction module 103, so that the digital reconstruction module 103 determines the first electrical signal sequence into which the current output signal is inserted.

In one example, the comparison and judgment unit 1010 may also be disposed outside SADC, which is not limited by the embodiments of the present disclosure.

In a possible embodiment, as shown in fig. 4b and 4c, the circuit may comprise a first control unit, which may be used to generate a sequence of electrical signals.

Referring to fig. 4d, fig. 4d is a schematic diagram illustrating a first control unit in an analog-to-digital conversion circuit according to an embodiment of the disclosure.

In one possible implementation, the circuit includes a first control unit, where the first control unit includes a flip-flop (e.g., D-flip-flop) DFF and a Linear Feedback Shift Register (LFSR), where the flip-flop is configured to sample an output signal En of the comparison and judgment unit and output a clock signal clk_pn, and the linear feedback shift register is configured to generate a strobe signal PN (i.e., a first electrical signal sequence) according to the clock signal clk_pn, where the dual comparator component is further configured to strobe the first comparator or the second comparator with the strobe signal, and output a strobe result to a sub digital-to-analog conversion SDAC unit in the MDAC module.

In one example, a linear feedback shift register may also be utilized to generate a sequence of electrical signals, wherein a value in the sequence of electrical signals may represent a high or low level, e.g., when a certain value in the sequence of electrical signals is 1 may represent a high level, a0 or-1 may represent a low level.

In one possible implementation, as shown in fig. 4c, the SADC module 101 may include a multiplexing unit 1011, wherein,

The multiplexing unit 1011 is electrically connected to the first comparator cmpA and the second comparator cmpB, and is configured to gate the result of the first comparator cmpA or the second comparator cmpB according to the first electrical signal sequence, and output the determination result signal EN ₁ to the digital reconstruction module 103.

In one example, when the digital reconstruction module 103 determines that the comparison results of the two comparators are different according to the determination result signal EN ₁, the error estimation value may be determined using the first electrical signal sequence corresponding to the determination result signal and the corresponding digital signal (obtained by post-quantization of the first residual signal inserted into the first electrical signal sequence).

In one example, the multiplexing unit 1011 may include a multiplexer MUX.

In one example, the multiplexing unit 1011 may be disposed outside the SADC module, and the embodiment of the present disclosure is not limited in this regard.

In one possible implementation, as shown in fig. 4c, the digital reconstruction module 103 may include:

The first error calculating unit 1031 is configured to perform a correlation operation by using the first electrical signal sequence and the digital signal Dbe that is quantized by the later stage of the first residual signal, so as to obtain a first error estimated value k ₁, where the first error estimated value is a gain error between steps;

a first digital reconstruction unit 1032, electrically connected to the first error calculation unit 1031, configured to reconstruct the digital output signal by using the first error estimation value, and output the reconstructed digital output signal.

It should be noted that, the digital reconstruction module 103, and each unit in the digital reconstruction module according to the embodiments of the present disclosure may be implemented by using a hardware circuit, for example, using a dedicated hardware circuit, or using a general-purpose hardware circuit (digital signal processor, central processing unit, microprocessor, etc.) in combination with executable logic.

The disclosed embodiment can implement calculation of gain error between first-order steps and reconstruction of digital output signal by using the dual comparator assembly 1 (as shown in fig. 4 c) and the digital reconstruction module 103, and is described below as an example.

The calculation of the gain error between the first steps is exemplarily described below with specific examples.

For example, for a pipelined ADC with a first stage of 4-bits (3-bit valid bits), assuming that there is only one inter-stage gain error, the residual signal of the first stage is:

V_res,1＝G₁*k₁*(V_in-D₁) (2)

where G ₁ is the gain of the amplifier in the ideal case, for example 8.

Assuming that the post-stage is ideal, neglecting quantization errors, and the digital output signal of the residual electric signal of the first stage after the post-stage quantization is:

D_be＝G₁*k₁*(V_in-D₁) (3)

The comparison thresholds of the first comparator cmpA and the second comparator cmpB, which record the reference electric signal as being in the vicinity of 1/16, are V _cmpa and V _cmpb, respectively, and there are:

When the input signal is at (V _cmpa,V_cmpb), the first comparator cmpA and the second comparator cmpB output different results, if the comparison result of the first comparator cmpA is selected, the module SDAC output is 0, and if the comparison result of the second comparator cmpB is selected, the module SDAC output is 1/8.

When the input signal vin=1/16+Δ ₁, in which |Δ ₁ | <0.005, and the first comparator cmpA and the second comparator cmpB are gated by the first electric signal sequence, the PN ₁ sequence (s=1, the first electric signal sequence) equivalent to the equation (1) is inserted, the residual signal output by the MDAC module is:

assuming that the post-stage is ideal, ignoring quantization error, consider the post-stage digital output Db _e,1＝V_res,1, then:

Then the first time period of the first time period,

Wherein,Representing performing a correlation operation.

For equation (8):

Bringing formulae (19), (10) into formula (8), yields:

From this, the estimated value of k ₁ can be found as

Therefore, the first error calculation unit 1031 performs a correlation operation using the first electric signal sequence (PN ₁) and the digital signal D _be,1 (ignoring quantization errors) after the post quantization of the first residual signal, and may obtain the first error estimation value k ₁.

In one example, for a (3+1) -bit sub-stage, the formula for the digital output signal, if not calibrated, is: d _out＝D_out,1+D_be/8, where D _out,1 is the digital output signal of the first stage and D _be is the post-stage digital output. Ideally, ignoring quantization error, D _be＝8(Vin-D_out,1), then D _out＝D_out,1+Vin-D_out,1 = Vin; assuming that first order non-idealities are considered, D _be＝8*k₁*(Vin-D_out,1), a signal reconstruction formula can be obtained: d _out＝D_out,1+D_be/8/k₁.

Thus, the first digital reconstruction unit 1032 of the embodiment of the present disclosure may reconstruct the digital output signal using the first error estimation value and output the reconstructed digital output signal.

For example, in one example, the first digital reconstruction unit 1032 may control the adder to add the digital output signal to the compensation value D _cali(D_be/8/k₁) to implement error compensation and output the reconstructed digital output signal.

In one example, embodiments of the present disclosure may reconstruct a digital output signal using an average of multiple calculated compensation values, or select one compensation value to reconstruct the signal according to a trend of the compensation value over time, which may reduce fluctuations, and may increase stability while improving the output accuracy of the ADC.

While the determination of the gain error between the first steps and the digital reconstruction of the digital output signal have been described above by gating the dual comparators with the first electrical signal sequence, embodiments of the present disclosure may also implement the calculation of the gain error between the first steps and the digital reconstruction of the digital output signal by adding the dual comparator assembly 2, additional capacitors, and switches, as described below.

Referring to fig. 8, fig. 8 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure.

In one possible implementation manner, a capacitor is additionally added to the capacitor array of the MDAC module, and the embodiment of the disclosure may select one end of the electrical signal Vrefp or Vrefn connected to the capacitor according to the electrical signal sequence, so that the electrical signal sequence PN is converted into an analog signal through the capacitor, amplified by the residual amplifier, and then enters a subsequent stage to insert the electrical signal sequence into the residual signal, where the residual electrical signal of the stage is:

V_res,1＝G₁*k₁*(V_in-D₁-PN)+k₃*(V_in-D₁-PN)³ (13)

Where G ₁ represents the ideal gain, PN represents the inserted PN sequence, and D ₁ represents the first digital signal output by the SADC module.

In one possible implementation, as shown in fig. 8, a third comparator cmpC and a fourth comparator cmpD (in the dual comparator assembly 2) are added in the SADC module or outside the SADC module in the embodiment of the disclosure, the equivalent reference electrical signal of the third comparator cmpC is the sum of the second reference electrical signal and the third threshold electrical signal or is close to the sum of the second reference electrical signal and the third threshold electrical signal (within a certain range of the sum of the third threshold electrical signal and the second reference electrical signal), the equivalent reference electrical signal of the fourth comparator cmpD is the sum of the second reference electrical signal and the fourth threshold electrical signal or is close to the sum of the second reference electrical signal and the fourth threshold electrical signal, and the inputs of the third comparator cmpC and the fourth comparator cmpD are the first analog signals.

In one example, the second reference electrical signal may be 0.

In one example, the third threshold electric signal and the fourth threshold electric signal may be only positive values or negative values, and the absolute values of the third threshold electric signal and the fourth threshold electric signal may be equal or different, which is not limited by the embodiments of the present disclosure.

In one example, the third threshold electrical signal may be equal to the first threshold electrical signal, and the fourth threshold electrical signal may be equal to the second threshold electrical signal, that is, the first threshold electrical signal, the second threshold electrical signal, the third threshold electrical signal, and the fourth threshold electrical signal may be independent values, and they may be equal in absolute value or unequal in value, which may be set by those skilled in the art according to needs or practical situations.

In one example, the third comparator cmpC, the fourth comparator cmpD may be set by:

Setting the reference electric signals of the third comparator cmpC and the fourth comparator cmpD to 0, and setting Offset (deviation of the reference electric signals of the comparators from the design values) of the first comparator cmpA and the second comparator cmpB to be opposite, wherein the magnitudes of the Offset electric signals can be respectively the third threshold electric signal and the fourth threshold electric signal (for example, respectively 5mV, -5 mV); or (b)

Setting the reference electric signals of the third comparator cmpC and the fourth comparator cmpD to be 0, and realizing that the equivalent reference electric signal of the third comparator cmpC is equal to or similar to the third threshold electric signal and the equivalent reference electric signal of the fourth comparator cmpD is equal to or similar to the fourth threshold electric signal by adjusting the noise of the first comparator cmpA and the second comparator cmpB;

The mode of setting Offset electric signal Offset and adjusting noise is combined to realize that the equivalent reference electric signal of the third comparator cmpC is equal to or similar to the third threshold electric signal, and the equivalent reference electric signal of the fourth comparator cmpD is equal to or similar to the fourth threshold electric signal; or (b)

The reference electrical signal of the third comparator cmpC is directly set as the third threshold electrical signal, and the reference electrical signal of the fourth comparator cmpD is directly set as the fourth threshold electrical signal.

In a possible embodiment, the circuit may further comprise a second control unit for generating a second sequence of electrical signals from the clock signal for enabling gating control of the comparator.

The specific description of the second control unit refers to the previous description of the first control unit, and will not be repeated here.

In one possible implementation manner, as shown in fig. 8, the MDAC module may include a sub digital-to-analog conversion SDAC unit, an adding unit, and an amplifying unit, where the SDAC unit is configured to convert the first digital signal to obtain a second analog signal, and the adding unit is configured to perform a difference operation on the first analog signal and the second analog signal and output the difference signal to the amplifying unit to amplify the difference signal, so as to obtain the residual signal, and the MDAC module may further include a first switch K1, a second switch K2, a third switch K3, and a first capacitor Ce, where:

The first end of the first switch K1 receives a first reference electric signal Vrefp, the second end is electrically connected with the first end of the first capacitor Ce,

The first end of the second switch K2 receives a second reference electrical signal Vrefn, and the second end is electrically connected to the first end of the first capacitor Ce, where the first reference electrical signal Vrefp is positive (high level), the second reference electrical signal Vrefn is negative (low level),

The first end of the third switch K3 receives the common mode electric signal Vcm, the second end is electrically connected to the first end of the first capacitor Ce,

The second end of the first capacitor Ce is electrically connected to the adding unit,

The SADC module (dual-comparator module 2) is further configured to control the on states of the first switch K1, the second switch K2, and the third switch K3 according to the comparison results of the third comparator cmpC and the fourth comparator cmpD and/or the second electrical signal sequence, so that the MDAC module outputs a second residual signal according to the comparison results of the third comparator and the fourth comparator, thereby implementing the insertion of the second electrical signal sequence into the residual signal.

In one possible implementation, the controlling the on states of the first switch K1, the second switch K2, and the third switch K3 according to the comparison results of the third comparator cmpC and the fourth comparator cmpD includes:

When the comparison results of the third comparator cmpC and the fourth comparator cmpD are the same, the first switch K1 and the second switch K2 are controlled to be turned off, and the third switch K3 is controlled to be turned on.

when the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, the third switch K3 is controlled to be turned off, and the first switch K1 or the second switch K2 is controlled to be turned on according to the second electric signal sequence PN 2.

In one possible implementation, when the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, controlling the first switch K1 or the second switch K2 to be turned on according to a second electrical signal sequence includes:

When the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, and the current codeword of the second electrical signal sequence is at a high level, the first switch K1 is controlled to be turned on, and the second switch K2 is controlled to be turned off; or (b)

When the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, and the current codeword of the second electrical signal sequence is at a low level, the first switch K1 is controlled to be turned off, and the second switch K2 is controlled to be turned on.

Through the above circuit, the embodiments of the present disclosure can control the on states of the first switch K1, the second switch K2, and the third switch K3 through the comparison results of the third comparator and the fourth comparator, so as to insert the second electrical signal sequence into the residual signal.

In one example, the digital reconstruction module may determine a gain error between the first steps based on the second electrical signal sequence and the digital signal of the second residual signal quantized by the later stage, and digitally reconstruct the digital output signal of the current stage, as described in the following exemplary description.

In a possible implementation manner, as shown in fig. 8, the first error calculating unit 1031 may be further configured to determine a first error estimate by using the second electrical signal sequence and the digital signal output by the second residual signal through the post-quantization, where the first error estimate is a gain error between steps.

In one example, in the embodiment of the disclosure, the new equivalent reference electrical signals are respectively the third comparator cmpC, the fourth comparator cmpD, the first switch K1, the second switch K2, the third switch K3, and the first capacitor Ce of 5mV, -5mV, the input signals are compared by the third comparator cmpC and the fourth comparator cmpD to obtain a comparison result, the on states of the first switch K1, the second switch K2, and the third switch K3 are controlled according to the comparison results of the third comparator cmpC and the fourth comparator cmpD and the second electrical signal sequence, so that the MDAC module outputs a second residual signal according to the comparison results of the third comparator and the fourth comparator, wherein when the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, the third switch K3 is controlled to be turned off, the first switch K1 or the second switch K2 is controlled according to the second electrical signal sequence PN2, and the second electrical signal sequence is judged to be turned on, and the digital reconstructed sequence ₂ is inserted.

In one example, the first digital reconstruction unit 1032 reconstructs the digital output signal based on the first inter-level gain error determined by the first error calculation unit 1031.

It should be noted that, when only the first-stage gain error exists, the digital reconstruction module performs a digital reconstruction process using the determined first-stage gain error in a similar manner, whether the dual comparator is gated by the first electric signal sequence as shown in fig. 4c or the second electric signal sequence is inserted by the additional capacitor as shown in fig. 8, and the detailed description is omitted herein.

In the above description, when only the first-stage gain error exists, the embodiment of the disclosure may further determine the first-stage gain error and the third-stage gain error when the third-stage gain error exists by combining the manner of inserting the first electric signal sequence into the dual-comparator shown in fig. 4c and the manner of inserting the second electric signal sequence into the dual-comparator shown in fig. 8 by using the additional capacitor, and when the third-stage gain error is calculated, the embodiment of the disclosure may control the on states of the first switch K1, the second switch K2 and the third switch K3 by using the comparison results of the second electric signal sequence, the third comparator and the fourth comparator, so that the MDAC module outputs a second residual signal according to the comparison results of the third comparator and the fourth comparator, and combines the comparison results of the first electric signal sequence, the first comparator and the second comparator to select the comparator (one of the first comparator and the second comparator) to obtain the first residual signal inserted into the first electric signal sequence, thereby determining the first-stage error and the third-stage gain error, and improving the accuracy of the reconstruction of the digital gain signal.

An exemplary description of the error determination and digital reconstruction scheme in the presence of a third-order inter-gain error is provided below.

Referring to fig. 9, fig. 9 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure.

In one possible implementation, as shown in fig. 9, the digital reconstruction module may further include:

The second error calculating unit 1033 may be configured to determine a second error estimation value and a third error estimation value by using a first determination result signal of the first comparator and the second comparator, a second determination result signal of the third comparator and the fourth comparator, the first electric signal sequence, the second electric signal sequence, the first determination result signal indicating a digital signal in which the first residual signal and the second residual signal are quantized in a later stage when the comparison results of the first comparator and the second comparator are different, and the second determination result signal indicating a digital signal in which the second residual signal is quantized in a later stage when the comparison results of the third comparator and the fourth comparator are different, where the second error estimation value is a first-stage gain error when a third-stage gain error is calculated, and the third error estimation value is a third-stage gain error.

When EN ₁, EN2 are true, i.e., the comparison results of the dual comparators in dual comparator assembly 1 are different and/or the comparison results of the dual comparators in dual comparator assembly 2 are different, embodiments of the present disclosure perform the calculation of the error estimate.

In one example, as shown in fig. 9, taking a path of comparison unit with a reference electric signal of 1/16V in the SADC module as an example, on the one hand, in the embodiment of the disclosure, the comparator with the reference electric signal of 1/16V may be replaced by a first comparator cmpA and a second comparator cmpB, and equivalent reference electric signals are set to be 1/16-0.005V and 1/16+0.005v respectively, when an input signal is received, the first comparator cmpA and the second comparator cmpB respectively compare the equivalent reference electric signals of the input signal to obtain comparison results, the comparison judging unit 1010 performs an exclusive or operation on the output results of the first comparator cmpA and the second comparator cmpB to determine whether the comparison results of the first comparator cmpA and the second comparator cmpB are the same, and output a judging result signal EN ₁, if the comparison results of the first comparator cmpA and the second comparator cmpB are different, the multiplexing unit 1011 gates the first comparator cmpA or the second comparator cmpB according to a first electric signal sequence, so that the first comparator module outputs a two-stage digital signal and the first digital component of the first comparator ₁ may output the digital component.

On the other hand, in the embodiment of the disclosure, the new added equivalent reference electrical signals are respectively 5mV, -5mV of the third comparator cmpC, the fourth comparator cmpD, the first switch K1, the second switch K2, the third switch K3, and the first capacitor Ce, the dual comparator assembly 2 (may also be referred to as the second comparator assembly) uses the third comparator cmpC and the fourth comparator cmpD to compare the input signals to obtain comparison results, and controls the on states of the first switch K1, the second switch K2, and the third switch K3 according to the comparison results of the third comparator cmpC and the fourth comparator cmpD and the second electrical signal sequence, so that the MDAC module outputs a second residual difference signal according to the comparison results of the third comparator and the fourth comparator, wherein when the comparison results of the third comparator cmpC and the fourth comparator cmpD are different, the third switch K3 is controlled to be turned off, and the first switch K1 or the second switch K2 is controlled according to the second electrical signal sequence PN ₂, and the digital difference signal is quantized and outputted to the second digital difference signal sequence ₂.

The digital reconstruction module determines a second error estimation value and a third error estimation value according to a first judgment result signal of the first comparator and the second comparator, a second judgment result signal of the third comparator and the fourth comparator, the first electric signal sequence, the second electric signal sequence, the first judgment result signal indicating a digital signal of which the first residual error signal and the second residual error signal are quantized at a later stage when comparison results of the first comparator and the second comparator are different, and the second judgment result signal indicating a digital signal of which the second residual error signal is quantized at a later stage when comparison results of the third comparator and the fourth comparator are different, wherein the second error estimation value is a first-stage gain error when a third-stage gain error is calculated, and the third error estimation value is a third-stage gain error.

Possible implementations of the second error calculation unit 1033 for determining the second error estimate (first-order inter-gain error k ₂), the third error estimate (third-order inter-gain error k ₃) are exemplarily described below.

In one example, for a pipelined ADC with a first stage of 4-bit (3-bit valid bit), when interstage gain errors are present, the residual electrical signal for the first stage is:

V_res,1＝G₁*k₂*(V_in-D₁)+k₃*(V_in-D₁)³ (14)

Where G ₁ is the gain of the amplifier in the ideal case, in this case 8.

D_be＝G₁*k₂*(V_in-D₁)+k₃*(V_in-D₁)³ (15)

The process of inserting the first electric signal sequence by switching the output results of the first comparator and the second comparator when the input signal is at (1/16-0.005,1/16+0.005) and inserting the second electric signal sequence by adding the first capacitor Ce in the MDAC module when the input signal is at (-0.005, +0.005) (s=2), then the second error calculation unit may include:

The comparison thresholds (equivalent reference electric signals) of the first comparator cmpA and the second comparator cmpB of the two comparators, which are in the vicinity of 1/16, are V _cmpa and V _cmpb, respectively, and the comparator comprises:

the first electrical signal sequence PN1 is used as a control signal to gate one of the first comparator cmpA and the second comparator cmpB as the output result of the first comparator cmpA and the second comparator cmpB, when PN1>0, the comparison result of the first comparator cmpA is selected, the output of the SDAC module is 0, and when PN1<0, the comparison result of the second comparator cmpB is selected, and when SDAC module outputs 1/8. When the input signal is in (V _cmpa,V_cmpb), the output results of the two comparators are different, the EN ₁ signal (first judgment result signal) obtained by the exclusive-or operation of the two comparators is positive, and the digital signal which corresponds to the residual error and is quantized at the later stage is taken out for digital reconstruction.

In one example, when the first determination result signal EN ₁ received by the second error calculation unit 1033 is positive, the second error calculation unit 1033 may confirm the first electric signal sequence into which the residual error signal outputted by SDAC is inserted, and the second error calculation unit 1033 may acquire the digital signal, the first electric signal sequence, and the digital output signal of the subsequent stage to perform calculation and compensation of the error estimation value.

When the input signal vin=1/16+Δ ₁, where |Δ ₁ | <0.005, the first electrical signal sequence PN ₁ equivalent to equation (1) is inserted, then the residual electrical signal of the first stage is:

Assuming that the post-stage is ideal, ignoring quantization error, consider the post-stage digital output D _be,1＝V_res,1, then:

Then the first time period of the first time period,

Wherein, Δ ₁ is smaller in magnitude and can be ignored approximately, and equation (20) can be organized as:

the comparison thresholds of the third comparator cmpC and the fourth comparator cmpD near the reference electric signal 0V are V _cmpc and V _cmpd, respectively, and include:

V_cmpc＝-0.005 (22)

V_cmpd＝+0.005 (23)

the SADC module (for example, the control unit 1013 therein, or may also be a controller disposed outside the ADC) performs an exclusive-or operation according to the two comparison results of the third comparator cmpC and the fourth comparator cmpD and switches the switch of the first capacitor C1 in the MDAC module according to the positive and negative of the second electric signal sequence PN 2.

In one example, when the input signal does not fall near 0 (the result of the exclusive-or operation between the two comparison results of the third comparator cmpC and the fourth comparator cmpD is 0, the comparison result is the same), the third switch K3 of the first capacitor Ce is turned on, and the remaining switches are turned off, so that one end of the first capacitor Ce is cut to the common mode electrical signal Vcm, which may be 1V in one example.

In one example, when the input signal is at (V _cmpc,V_cmpd), i.e. falls near 0, it is detected that the output results of the two comparators are different according to the result of the exclusive-or operation, and at this time, one end of the first capacitor Ce is controlled by using the second electrical signal sequence PN ₂ to access the first reference electrical signal Vrefp or the second reference electrical signal Vrefn, where the magnitudes of the first reference electrical signal Vrefp and the second reference electrical signal Vrefn may be set according to the magnitudes of other reference electrical signals of the SDAC module, and the magnitude of the second electrical signal sequence PN ₂ may be determined according to the relative magnitudes of the first capacitor Ce and the other capacitors, and the specific magnitude of the first reference electrical signal Vrefp and the second reference electrical signal Vrefn is not limited.

In one example, when EN ₂ is equal to 1 and PN ₂ >0, the first switch K1 is on, the remaining switches are off, the first capacitor C1 is connected to the first reference electrical signal Vrefp, when EN ₂ is equal to 1 and PN2<0, the second switch K2 is on, the remaining switches are off, the first capacitor C1 is connected to the second reference electrical signal Vrefn, and the above operation is inserted with the second electrical signal sequence PN ₂ having an amplitude of 1/32 (exemplary).

It should be noted that, in the embodiment of the present disclosure, the amplitude of the second electrical signal sequence PN ₂ is 1/32, the amplitude of the first electrical signal sequence PN ₁ is 1/16, and the specific amplitudes of the first electrical signal sequence PN ₁ and the second electrical signal sequence PN ₂ are not limited, the amplitudes of the first electrical signal sequence PN ₁ and the second electrical signal sequence PN ₂ may also take other numbers (they are different), in one example, the first electrical signal sequence PN ₁ may be 1/m, where m is the number of comparators of the original SADC, and the second electrical signal sequence PN ₂ may take other numbers. The value of the first electrical signal sequence PN ₁ may be determined according to the reference electrical signals of the comparison units in SADC, may be near the original SADC reference electrical signals (in 4-bit SADC, 16 choices may be included), and the value of the second reference electrical signal corresponding to the second electrical signal sequence PN ₂ may be between (-1, +1), where the specific size needs to be determined according to the magnitude of the inserted PN and the magnitude of the offset, and does not cause the oscillation amplitude increasing principle. Wherein the larger the amplitude of the electrical signal sequence, the better the reconstruction accuracy, however, in the present example, in order to control the output swing of the MDAC module, the electrical signal sequence should be set to be less than or equal to 1/16 so that the swing is within ±1/2.

Note V _in＝Δ₂, where Δ ₂ is less than 0.005 in absolute value, where the residual is:

Similar to the case where the input signal is in the vicinity of 1/16, it is possible to obtain

Wherein, Δ ₂ is smaller in magnitude and can be ignored approximately, and equation (25) can be organized as:

Since D _be,1、D_be,2、PN₁、PN₂ is known in both the equation (21) and the equation (26), the second error calculation unit 1033 can calculate the second error estimation value k ₂ and the third error estimation value k ₃ according to the equation (21) and the equation (26).

In one example, the second error calculation unit 1033 may calculate the second error estimation value k ₂ and the third error estimation value k ₃ by using the combination of (21) and (26), or may obtain the second error estimation value k ₂ and the third error estimation value k ₃ by using a least square method or the like, which is not limited to the embodiment of the disclosure.

In one possible implementation, as shown in fig. 9, the digital reconstruction module may further include: the second digital reconstruction unit 1034 may be configured to obtain a reconstructed digital output signal using the second error estimate, the third error estimate, and the digital output signal.

In one example, when the second error calculation unit 1033 determines the second error estimation value k ₂ and the third error estimation value k ₃ according to the first determination result signal of the first comparator and the second comparator, the first electric signal sequence, the second electric signal sequence, the first determination result signal indicating that the comparison result of the first comparator and the second comparator is different, the first residual signal and the second residual signal are post-quantized digital signals, and the second determination result signal indicating that the comparison result of the third comparator and the fourth comparator is different, the second digital reconstruction unit 1034 may directly calculate the compensation value using newton's method (exemplary), or a formula according to a root of a unitary third order equation, and reconstruct the digital output signal using the compensation value:

D _be＝8*k₁*D_cali+k₃*D_cali ≡3, where D _cali represents the compensation value.

In one example, the second digital reconstruction unit 1034 may add (with an adder) the compensation value to the digital output signal of the current stage to obtain a reconstructed digital output signal D _out.

In one example, embodiments of the present disclosure may reconstruct a digital output signal using an average of multiple calculated compensation values, or select one of the compensation values to reconstruct according to a trend of the compensation value over time, which may reduce fluctuations, while improving the accuracy of the ADC output.

Through the circuit, when only a first-order gain error exists or a first-order gain error and a third-order gain error exist, the interstage gain error is corrected on the premise of not increasing the output swing, the digital output signal is reconstructed, the accuracy of the ADC is improved, the cost of the analog circuit is only 3 comparators and 1 capacitor, and compared with the related art, the analog circuit has the advantages of being low in cost, low in power consumption, low in size cost and the like.

For the gain error between the third steps, the embodiment of the disclosure also provides another digital reconstruction mode.

In one possible implementation manner, the MDAC module may further include a second capacitor and a third capacitor, and are disposed in dual comparators (not shown) corresponding to the second capacitor and the third capacitor, where the MDAC module is configured to obtain the third residual signal and the fourth residual signal according to comparison results output by the comparators selected by the second capacitor, the dual comparators corresponding to the second capacitor, the third capacitor and the dual comparators corresponding to the third capacitor in different comparison periods by using the third electrical signal sequence and the fourth electrical signal sequence,

The digital reconstruction module is further configured to digitally reconstruct the digital output signal according to the digital signal after the third residual signal is quantized at the later stage and the digital signal after the fourth residual signal is quantized at the later stage, and output the reconstructed digital output signal.

The analog-digital conversion circuit provided by the embodiment of the disclosure can measure the inter-stage gain error in real time and reconstruct a digital output signal according to the measured inter-stage gain error, and can measure the first-order gain error and the third-order gain error of the residual error amplifier in near real time on the premise of not increasing the swing amplitude, and when the inter-stage gain error is found to change, the working state of the correction circuit is timely adjusted, so that the inter-stage gain error is always controlled within a certain range.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit, wherein the circuit is a stage of a pipeline analog-to-digital converter for analog-to-digital converting an input analog signal to a digital output signal, the circuit comprising: the digital-to-analog conversion system comprises a sub-digital conversion SADC module, a digital-to-analog conversion and amplification MDAC module and a digital reconstruction module, wherein the SADC module is used for carrying out analog-to-digital conversion on an input first analog signal to obtain a first digital signal; the MDAC module is used for generating a residual signal by utilizing the first digital signal and the first analog signal, wherein:

the SADC module comprises a multipath comparison unit, any path of the multipath comparison unit comprises a double comparator assembly, the double comparator assembly comprises a double comparator, the double comparator is used for judging the range of a first analog signal, and the double comparator assembly is used for:

Outputting a judging result signal of the double comparator when the difference value between the first analog signal and the first reference electric signal is in a preset range, wherein the judging result signal indicates whether the comparison results of the double comparators are the same,

Gating one of the dual comparators with the first electrical signal sequence such that the MDAC module outputs a first residual signal according to a comparison result of the gated comparator;

The digital reconstruction module is used for:

Receiving the judgment result signal, the first electric signal sequence, the digital signal of the first residual difference signal quantized by the post-stage circuit and the digital output signal,

And carrying out digital reconstruction on the digital output signal by utilizing the judgment result signal, the first electric signal sequence and the digital signal quantized by the first residual difference signal through a later-stage circuit, and outputting the reconstructed digital output signal.

2. The circuit of claim 1, wherein the dual comparator comprises a first comparator and a second comparator, wherein an equivalent reference electrical signal of the first comparator is a sum of the first reference electrical signal and a first threshold electrical signal, an equivalent reference electrical signal of the second comparator is a sum of the first reference electrical signal and a second threshold electrical signal, and input signals of the first comparator and the second comparator are the first analog signals, wherein the preset range is determined according to the first threshold electrical signal and the second threshold electrical signal.

3. The circuit of claim 2, wherein the dual comparator component is configured to gate the first comparator if a codeword of the first electrical signal sequence corresponding to the current sampling period is high, perform digital-to-analog conversion using a comparison result output by the first comparator, and output a gating result of gating the first comparator to a SDAC unit in the MDAC module;

4. The circuit of claim 3, wherein if the comparison results of the first comparator and the second comparator are detected to be different in the current hold stage, the dual comparator assembly is configured to update a first electric signal sequence with the determination result signal and gate the first comparator or the second comparator with the updated first electric signal sequence, output a gate result to the SDAC unit,

5. The circuit of claim 3 or 4, wherein the dual comparator assembly comprises a comparison and judgment unit, wherein the comparison and judgment unit is electrically connected to the first comparator and the second comparator, and is configured to determine whether the comparison results of the first comparator and the second comparator are the same according to the output results of the first comparator and the second comparator, and output the judgment result signal.

6. The circuit of claim 5, comprising a first control unit comprising a flip-flop for outputting a clock signal after sampling an output signal of the comparison and judgment unit and a linear feedback shift register for generating a first electrical signal sequence according to the clock signal, wherein the dual comparator component is further configured to gate the first comparator or the second comparator with the first electrical signal sequence and output a gate result to a sub digital-to-analog conversion SDAC unit in the MDAC module.

7. The circuit of claim 6, wherein the dual comparator assembly comprises a multiplexing unit, wherein the multiplexing unit is electrically connected to the first comparator and the second comparator for gating the results of the first comparator or the second comparator according to the first sequence of electrical signals.

8. The circuit of claim 1, wherein the digital reconstruction module comprises:

The first error calculation unit is used for carrying out correlation operation on the first electric signal sequence, the judging result signal and the digital signal of the first residual error signal after the post-quantization to obtain a first error estimated value, wherein the first error estimated value is a gain error between first steps;

The first digital reconstruction unit is electrically connected with the first error calculation unit and is used for digitally reconstructing the digital output signal by utilizing the first error estimation value and outputting the reconstructed digital output signal.

9. The circuit of claim 1, further comprising a third comparator, a fourth comparator, wherein an equivalent reference electrical signal of the third comparator is a sum of a second reference electrical signal and a third threshold electrical signal, wherein an equivalent reference electrical signal of the fourth comparator is a sum of the second reference electrical signal and a fourth threshold electrical signal, and wherein inputs of the third comparator and the fourth comparator are the first analog signal.

10. The circuit of claim 9, wherein the MDAC module includes a sub-digital-to-analog conversion SDAC unit, an adding unit, and an amplifying unit, the SDAC unit is configured to convert the first digital signal to obtain a second analog signal, the adding unit is configured to perform a difference operation on the first analog signal and the second analog signal and output the difference signal to the amplifying unit to amplify the difference signal, and the MDAC module further includes a first switch, a second switch, a third switch, and a first capacitor, where:

The first end of the first switch receives a first reference electric signal, the second end is electrically connected with the first end of the first capacitor,

The first end of the second switch receives a second reference electric signal, the second end is electrically connected with the first end of the first capacitor, wherein the first reference electric signal is positive, the second reference electric signal is negative,

The first end of the third switch receives the common mode electric signal, the second end is electrically connected with the first end of the first capacitor,

The second end of the first capacitor is electrically connected to the adding unit,

The SADC module is further configured to control the on states of the first switch, the second switch, and the third switch according to the comparison results of the third comparator and the fourth comparator and/or the second electrical signal sequence, so that the MDAC module outputs a second residual signal according to the comparison results of the third comparator and the fourth comparator.

11. The circuit of claim 10, wherein the controlling the on states of the first switch, the second switch, and the third switch according to the comparison results of the third comparator and the fourth comparator comprises:

And when the comparison results of the third comparator and the fourth comparator are the same, the first switch and the second switch are controlled to be disconnected, and the third switch is controlled to be connected.

12. The circuit of claim 10, wherein the controlling the on states of the first switch, the second switch, and the third switch according to the comparison results of the third comparator and the fourth comparator comprises:

and when the comparison results of the third comparator and the fourth comparator are different, controlling the third switch to be turned off, and controlling the first switch or the second switch to be turned on according to a second electric signal sequence.

13. The circuit of claim 12, wherein when the comparison results of the third comparator and the fourth comparator are different, controlling the first switch or the second switch to be turned on according to a second electric signal sequence comprises:

When the comparison results of the third comparator and the fourth comparator are different, and the current code word of the second electric signal sequence is at a high level, the first switch is controlled to be turned on, and the second switch is controlled to be turned off; or (b)

And when the comparison results of the third comparator and the fourth comparator are different, and the current code word of the second electric signal sequence is in a low level, the first switch is controlled to be turned off, and the second switch is controlled to be turned on.

14. The circuit of claim 10, wherein the digital reconstruction module comprises:

A second error calculation unit configured to determine a second error estimation value and a third error estimation value by using a first determination result signal of a first comparator and a second determination result signal of a second comparator, a second determination result signal of the third comparator and the fourth comparator, the first electrical signal sequence, the second electrical signal sequence, the first determination result signal indicating a digital signal of the first residual signal and the second residual signal quantized at a later stage when comparison results of the first comparator and the second comparator are different, and the second determination result signal indicating a digital signal of the third comparator and the fourth comparator quantized at a later stage when comparison results of the second residual signal quantized at a later stage are different, where the second error estimation value is a first-order gain error and a third-order gain error when a third-order gain error is calculated;

And the second digital reconstruction unit is used for digitally reconstructing the digital output signal by using the second error estimated value, the third error estimated value and the digital output signal to obtain a reconstructed digital output signal.

15. The circuit of claim 1, wherein the MDAC module further comprises a second capacitor, a double comparator corresponding to the second capacitor, a third capacitor and a double comparator corresponding to the third capacitor, wherein the MDAC module is configured to obtain a third residual signal and a fourth residual signal by using the comparison results output by the comparators selected by the second capacitor, the double comparator corresponding to the second capacitor, the third capacitor and the double comparator corresponding to the third capacitor in different comparison periods by using a third electric signal sequence and a fourth electric signal sequence,

16. A pipelined analog-to-digital converter, characterized in that each stage of the pipelined analog-to-digital converter comprises an analog-to-digital conversion circuit according to any one of claims 1 to 15.