CN114661087A - Reference voltage source with bias current matching - Google Patents
Reference voltage source with bias current matching Download PDFInfo
- Publication number
- CN114661087A CN114661087A CN202210234907.9A CN202210234907A CN114661087A CN 114661087 A CN114661087 A CN 114661087A CN 202210234907 A CN202210234907 A CN 202210234907A CN 114661087 A CN114661087 A CN 114661087A
- Authority
- CN
- China
- Prior art keywords
- resistor
- transistor
- tube
- npn
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to the field of integrated circuits, and discloses a reference circuit with bias current matching.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a reference voltage source circuit with bias current matching.
Background
With the continuous development of integrated circuit technology, the performance requirements for integrated circuit systems are also higher and higher. The reference voltage source provides the required reference voltage for other functional modules of the circuit, and is a very critical module in the circuit system. The principle of the reference voltage source is to add the voltage with positive temperature coefficient and the voltage with negative temperature coefficient after weighting to obtain the reference voltage with approximate zero temperature coefficient.
The band-gap reference voltage source has the characteristics of wide process conditions, high precision, strong stability and the like, has excellent performance in the aspects of power supply rejection ratio, temperature drift coefficient and the like, and is widely applied. Band-gap reference voltage source utilizes base-emitter voltage with negative temperature coefficient and thermal voltage V with positive temperature coefficient of BJT triodeTAnd weighting and adding to obtain the reference voltage of the low temperature drift coefficient. The reference voltage with low temperature drift coefficient has important effect on the stability and the precision of the system. Common bandgap references have a Brokaw structure and a Wildar structure, and a Brokaw-type reference can generate twice PTAT current, so that the device mismatch problem caused by the large emitter junction area ratio of a reference pair tube is reduced, the resistance for generating the PTAT current is small, and the output noise is low.
The Brokaw reference is often biased with a current source to reduce interference from the supply voltage. If the bias current is not matched with the temperature coefficient of the current required by the reference core, when the temperature changes in a wide range, the bias state of the reference core to the tube changes, the collector current generates deviation, the reference voltage is affected, and the temperature drift coefficient is large. The PTAT current source matched with the current temperature coefficient of the reference core pair transistor is introduced, so that the bias state of the reference core pair transistor is effectively ensured to be consistent, the temperature drift coefficient of the reference voltage is reduced, and the stable and accurate reference voltage is obtained.
Disclosure of Invention
The invention aims to provide a band-gap reference voltage source with bias current matching, which improves a bias current source on the basis of the traditional Brokaw reference, so that the temperature coefficients of the bias current source and the current on a pair of reference core tubes are kept consistent, and the low-temperature drift coefficient of a reference voltage is realized in a wider temperature range.
The technical scheme of the invention is as follows:
a reference voltage source with bias current matching comprises a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth PNP tube Q5, a sixth PNP tube Q6, a seventh PNP tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9 and a tenth NPN tube Q10; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20; a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; a first capacitor C1.
Specifically, one end of the first resistor R1 is connected to GND, and the other end is connected to the emitter of the first NPN transistor Q1.
One end of the second resistor R2 is connected to GND, and the other end is connected to the emitter of the second NPN transistor Q2, the emitter of the third NPN transistor Q3, and one end of the fifth resistor R5.
Specifically, one end of the third resistor R3 is connected to the input voltage VIN, and the other end is connected to the source of the first PMOS transistor M1.
One end of the fourth resistor R4 is connected to the input voltage VIN, and the other end is connected to the source of the second PMOS transistor M2.
The other end of the fifth resistor R5 is connected to the drain of the third NMOS transistor M3.
One end of the sixth resistor R6 is connected to the source and the gate of the fourth PMOS transistor M4, the gate of the third PMOS transistor M3, and the gate of the tenth PMOS transistor M10, and the other end is connected to the drain of the fifth NMOS transistor M5.
One end of the seventh resistor R7 is connected to the input voltage VIN, and the other end is connected to the gate of the seventh PMOS transistor M7, one end of the eighth resistor R8, and one end of the ninth resistor R9.
The other end of the eighth resistor R8 is connected to the drain of the seventh PMOS transistor M7, the gate of the first PMOS transistor M1, the gate of the second PMOS transistor M2 and the gate of the eighth PMOS transistor M8.
The other end of the ninth resistor R9 is connected to the drain of the sixth NMOS transistor M6.
One end of the tenth resistor R10 is connected to the input voltage VIN, and the other end is connected to the source of the eighth PMOS transistor M8.
One end of an eleventh resistor R11 is connected with the drain of the eighth PMOS tube M8, and the other end is connected with the gate and the drain of the ninth NMOS tube M9, the gate of the fifth NMOS tube M5, one end of a twelfth resistor R12 and the gate of the twelfth NMOS tube M12.
The other end of the twelfth resistor R12 is connected to GND.
One end of the thirteenth resistor R13 is connected to the source of the eleventh NMOS transistor M11, and the other end is connected to one end of the fourteenth resistor R14, one end of the fifteenth resistor R15, one end of the sixteenth resistor R16, and the base of the tenth NPN transistor Q10.
The other end of the fourteenth resistor R14 is connected to the emitter of the fifth PNP transistor Q5.
The other end of the fifteenth resistor R15 is connected to the emitter of the sixth PNP transistor Q6.
The other end of the sixteenth resistor R16 is connected to the emitter of the seventh PNP transistor Q7.
One end of the seventeenth resistor R17 is connected to the emitter of the eighth NPN transistor Q8, and the other end is connected to one end of the eighteenth resistor R18 and the emitter of the ninth NPN transistor Q9.
The other end of the eighteenth resistor R18 is connected to GND.
One end of the nineteenth resistor R19 is connected to the collector of the seventh PNP transistor Q7, and the other end is connected to GND.
One end of the twentieth resistor R20 is connected to the output terminal VREF, the base of the eighth NPN transistor Q8, the base of the ninth NPN transistor Q9, and the emitter of the tenth NPN transistor Q10.
The base of the first NPN transistor Q1 is connected to the base and collector of the second NPN transistor Q2 and the drain of the second PMOS transistor M2, and the collector thereof is connected to the drain of the first PMOS transistor M1 and the base of the third NPN transistor Q3.
The collector of the third NPN transistor Q3 is connected to the source of the fifth NMOS transistor M5.
The base and collector of the fourth NPN transistor Q4 are connected to the source of the ninth NMOS transistor M9, and the emitter thereof is connected to GND.
The base and collector of the fifth PNP transistor Q5 are connected to the base of the sixth PNP transistor Q6 and the collector of the eighth NPN transistor Q8.
The collector of the sixth PNP transistor Q6 is connected to the collector of the ninth NPN transistor Q9, one end of the first capacitor C1, the base of the seventh PNP transistor Q7, and the source of the twelfth NMOS transistor M12.
The source of the third PMOS transistor M3 is connected to the input voltage VIN.
The source of the fourth PMOS transistor M4 is connected to the input voltage VIN.
The gate of the sixth NMOS transistor M6 is connected to the input enable signal EN, and the source is connected to GND.
The source of the seventh PMOS transistor M7 is connected to the input voltage VIN.
The source of the tenth PMOS transistor M10 is connected to the input voltage VIN, the drain is connected to the drain and gate of the eleventh NMOS transistor M11, and the gate of the thirteenth NMOS transistor M13.
The drain of the twelfth NMOS transistor M12 is connected to the input voltage VIN.
The drain of the thirteenth NMOS transistor M13 is connected to the input voltage VIN.
The other end of the first capacitor C1 is connected to GND.
The invention has the beneficial effects that: according to the invention, the PTAT bias current source matched with the current temperature coefficient of the reference core pair transistor is introduced into the traditional Brokaw type band gap reference voltage source without an operational amplifier structure, so that when the temperature of the reference core pair transistor changes, the bias state is kept consistent, the collector currents are always equal, and the temperature drift coefficient of the reference voltage is reduced.
Drawings
FIG. 1 is a schematic diagram of a reference circuit with bias current matching according to the present invention
FIG. 2 is a waveform illustrating operation of an embodiment of the present invention
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
fig. 1 is a schematic diagram of a reference circuit with bias current matching according to the present invention, including a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a fifth PNP transistor Q5, a sixth PNP transistor Q6, a seventh PNP transistor Q7, an eighth NPN transistor Q8, a ninth NPN transistor Q9, and a tenth NPN transistor Q10; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20; a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; a first capacitor C1.
The gate of the sixth NMOS transistor M6 is connected to the input enable signal EN, and when the EN level is greater than its threshold voltage, M6 turns on and pulls its drain potential to ground, and the branch with M6 generates current. The seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the seventh NMOS transistor M7 form a bias voltage generating circuit, a bias voltage is generated at the drain electrode of the M7, and the bias voltage is connected to the gate electrodes of the first NMOS transistor M1, the second NMOS transistor M2 and the eighth NMOS transistor M8, so that the M1, the M2 and the M8 generate currents which are not influenced by the input voltage VIN. The third resistor R3, the fourth resistor R4 and the tenth resistor R10 are equal in size, the gate-source voltages of M1, M2 and M8 are adjusted, and currents on M1, M2 and M8 are equal. The eleventh resistor R11, the ninth NMOS transistor M9, the fourth NPN transistor Q4 and the twelfth resistor R12 together generate a suitable bias voltage, which is connected to the gate of the fifth NMOS transistor and the gate of the twelfth NMOS transistor, and the value of the bias voltage is the base-collector voltage of Q4 plus the gate-source voltage of M9. During the start-up of the circuit, the bias voltage of the gate of M9 can turn on M12, quickly charge the first capacitor C1, accelerate the reference establishment, and after the reference voltage VREF is established, the voltage on C1 is high enough to make the gate-source voltage of M9 smaller than the threshold voltage thereof, and M12 is turned off.
The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first NPN transistor Q6, the second NPN transistor Q2, the third NPN transistor Q3, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4 and the fifth NMOS transistor M5 are used as a bias current source generating circuit to generate a PTAT bias current with the same reference core temperature coefficient. R3 is identical to R4 and M1 is identical to M2, so that flow through Q1 and Q2 are equal, I1. The emitter junction area ratio of Q1 to Q2 was 1: 4. M3 and M4 form a current mirror, so that the current flowing through M3 and M4 is I2. The resistance values of R1 and R2 are equal. When M5 is turned on, a PTAT current I2 is generated, whose value is:
the fourth PMOS transistor M4 and the tenth PMOS transistor M10 form a current mirror, the ratio of M is 1:4, M10 is four times the PTAT current I2 of the mirror M4, and the current source is used as a reference current source. And the gate of the eleventh NMOS transistor M11 is shorted to the drain, and a bias voltage is provided for the thirteenth NMOS transistor M13. The thirteenth resistor R13 generates a voltage drop to make the base-collector of the tenth NPN transistor Q10 in proper reverse bias state. The fourteenth resistor R14 and the fifteenth resistor R15 raise the small signal impedance of the fifth PNP transistor Q5 and the sixth PNP transistor Q6 looking into the collector. The emitting junctions of the Q5 and the Q6 are equal in area, and form a current mirror, so that the currents of the branches where the Q5 and the Q6 are located are equal. The eighth NPN transistor Q8 and the ninth NPN transistor Q9 are used as reference core pair transistors, the ratio of the emitter junction areas is 1:10, the difference of base-emitter voltages of Q8 and Q9 generates a reference core current I3 on a seventeenth resistor R17, the current is PTAT current, and the value of the PTAT current is PTAT current
Two PTAT currents equal to I3 produce a PTAT voltage across the eighteenth resistor R18, plus a CTAT base-emitter voltage V of Q9be,Q9Generating a reference voltage VREF having a magnitude of
VREF＝Vbe,Q9+2I3·R18
The ratio of the currents flowing through the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 is 1:1:2, and the resistances of R1, R2 and R17 are set so that I2 is I3, there are
Thus, the temperature coefficients of the currents I2 and I3 are equal, and when the temperature changes, the magnitude of the current supplied by M10 is just equal to the magnitude of the current required by the reference core pair tube, so that the magnitude of the current is not too large or too small, which causes a large difference between the bias states of Q8 and Q9.
The first capacitor C1 is the compensation capacitor of the reference circuit where the dominant pole is generated, making the loop of the reference core circuit stable. The seventh PNP tube Q7 and the sixteenth resistor R16 introduce negative feedback to stabilize the reference voltage VREF. The emitter junction area ratio of Q5, Q6 and Q7 is 1:1:2, and the resistance ratio of R14, R15 and R16 is 1:1:2, so that the base current of Q7 is equal to twice of the base current of Q5, the purpose of compensating the extra base currents of Q5 and Q6 is achieved, the collector currents of Q8 and Q9 are equal as much as possible, and the generated reference voltage is more stable. A nineteenth resistor R19 brings the Q7 collector to the proper potential. M13 bears the high voltage of the branch, and the tenth NPN tube Q10 is used as a regulating tube to provide the current needed by the branch. The twentieth resistor R20 is used as a load resistor, so that the reference voltage VREF can be conveniently divided to obtain reference voltages with different required sizes.
Fig. 2 is a simulated waveform diagram of dc temperature scan of a reference circuit with bias current matching according to the present invention, where VIN is 32V, VREF is the output reference voltage of the reference circuit, i.e. the emitter voltage of the tenth PNP transistor, I2 is the PTAT bias current generated by the bias current source, i.e. the emitter current of Q3, and I3 is the PTAT current on the reference core pair transistor, i.e. the current on R14. As can be seen from FIG. 2, the temperature variation ranges from-50 deg.C to 150 deg.C, I2 and I3 remain approximately equal throughout, the maximum deviation is only 0.76791 μ A, and the temperature coefficient of the reference voltage VREF is only 11.975 ppm/deg.C.
As can be seen from the above detailed description: according to the reference circuit with the bias current matching function, the temperature coefficient of the reference bias current is the same as that of the reference core current, so that when the working temperature changes, the bias current is always consistent with the current required by the reference core pair transistor, the collector currents of the reference pair transistor can be always approximately equal through the base current compensated by the feedback loop, and the purpose of reducing the temperature drift coefficient of the reference voltage is achieved.
Claims (2)
1. The reference voltage source with the bias current matching function is characterized by comprising a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth PNP tube Q5, a sixth PNP tube Q6, a seventh PNP tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9 and a tenth NPN tube Q10; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20; a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; a first capacitance C1;
specifically, one end of the first resistor R1 is connected to ground, and the other end is connected to the emitter of the first NPN transistor Q1;
one end of the second resistor R2 is connected to the ground, and the other end is connected to the emitter of the second NPN transistor Q2, the emitter of the third NPN transistor Q3 and one end of the fifth resistor R5;
one end of the third resistor R3 is connected with the input voltage VIN, and the other end is connected with the source electrode of the first PMOS tube M1;
one end of the fourth resistor R4 is connected with the input voltage VIN, and the other end is connected with the source electrode of the second PMOS tube M2;
the other end of the fifth resistor R5 is connected with the drain electrode of the third NMOS tube M3;
one end of the sixth resistor R6 is connected with the source and the gate of the fourth PMOS tube M4, the gate of the third PMOS tube M3 and the gate of the tenth PMOS tube M10, and the other end is connected with the drain of the fifth NMOS tube M5;
one end of the seventh resistor R7 is connected to the input voltage VIN, and the other end is connected to the gate of the seventh PMOS transistor M7, one end of the eighth resistor R8, and one end of the ninth resistor R9;
the other end of the eighth resistor R8 is connected to the drain of the seventh PMOS transistor M7, the gate of the first PMOS transistor M1, the gate of the second PMOS transistor M2 and the gate of the eighth PMOS transistor M8;
the other end of the ninth resistor R9 is connected with the drain of the sixth NMOS transistor M6;
one end of the tenth resistor R10 is connected to the input voltage VIN, and the other end is connected to the source of the eighth PMOS transistor M8;
one end of an eleventh resistor R11 is connected with the drain electrode of the eighth PMOS tube M8, and the other end of the eleventh resistor R11 is connected with the gate electrode and the drain electrode of the ninth NMOS tube M9, the gate electrode of the fifth NMOS tube M5, one end of a twelfth resistor R12 and the gate electrode of the twelfth NMOS tube M12;
the other end of the twelfth resistor R12 is connected to the ground;
one end of the thirteenth resistor R13 is connected to the source of the eleventh NMOS transistor M11, and the other end is connected to one end of the fourteenth resistor R14, one end of the fifteenth resistor R15, one end of the sixteenth resistor R16, and the base of the tenth NPN transistor Q10;
the other end of the fourteenth resistor R14 is connected with the emitter of the fifth PNP tube Q5;
the other end of the fifteenth resistor R15 is connected with the emitter of the sixth PNP tube Q6;
the other end of the sixteenth resistor R16 is connected with the emitter of the seventh PNP tube Q7;
one end of the seventeenth resistor R17 is connected to the emitter of the eighth NPN transistor Q8, and the other end is connected to one end of the eighteenth resistor R18 and the emitter of the ninth NPN transistor Q9;
the other end of the eighteenth resistor R18 is connected to the ground;
one end of the nineteenth resistor R19 is connected with the collector of the seventh PNP tube Q7, and the other end is connected with the ground;
one end of the twentieth resistor R20 is connected to the output terminal VREF, the base of the eighth NPN transistor Q8, the base of the ninth NPN transistor Q9, and the emitter of the tenth NPN transistor Q10;
the base electrode of the first NPN tube Q1 is connected with the base electrode and the collector electrode of the second NPN tube Q2 and the drain electrode of the second PMOS tube M2, and the collector electrode of the first NPN tube Q1 and the base electrode of the third NPN tube Q3;
the collector of the third NPN transistor Q3 is connected to the source of the fifth NMOS transistor M5;
the base electrode and the collector electrode of the fourth NPN transistor Q4 are connected with the source electrode of the ninth NMOS transistor M9, and the emitter electrode of the fourth NPN transistor Q4 is connected with the ground;
the base electrode and the collector electrode of the fifth PNP tube Q5 are connected with the base electrode of the sixth PNP tube Q6 and the collector electrode of the eighth NPN tube Q8;
the collector of the sixth PNP transistor Q6 is connected to the collector of the ninth NPN transistor Q9, one end of the first capacitor C1, the base of the seventh PNP transistor Q7, and the source of the twelfth NMOS transistor M12;
the source electrode of the third PMOS transistor M3 is connected to the input voltage VIN;
the source electrode of the fourth PMOS transistor M4 is connected to the input voltage VIN;
the grid electrode of the sixth NMOS tube M6 is connected with the input enable signal EN, and the source electrode is grounded;
the source electrode of the seventh PMOS transistor M7 is connected to the input voltage VIN;
the source electrode of the tenth PMOS transistor M10 is connected to the input voltage VIN, the drain electrode is connected to the drain electrode and the gate electrode of the eleventh NMOS transistor M11, and the gate electrode of the thirteenth NMOS transistor M13;
the drain of the twelfth NMOS tube M12 is connected to the input voltage VIN;
the drain electrode of the thirteenth NMOS transistor M13 is connected to the input voltage VIN;
the other terminal of the first capacitor C1 is connected to ground.
2. The reference voltage source with bias current matching according to claim 1, wherein a temperature coefficient of a reference core PTAT bias current I2 generated by the first NPN transistor Q1, the second NPN transistor Q2, the third NPN transistor Q3, the first resistor R1 and the second resistor R2 is equal to a temperature coefficient of a PTAT current I3 on a reference core pair transistor formed by the eighth NPN transistor Q8 and the ninth NPN transistor Q9, so that when a temperature changes, a bias state of the reference core pair transistor is always consistent, collector currents are always equal, and a temperature drift coefficient of a reference voltage is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210234907.9A CN114661087B (en) | 2022-03-09 | 2022-03-09 | Reference voltage source with bias current matching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210234907.9A CN114661087B (en) | 2022-03-09 | 2022-03-09 | Reference voltage source with bias current matching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114661087A true CN114661087A (en) | 2022-06-24 |
| CN114661087B CN114661087B (en) | 2022-12-02 |
Family
ID=82030109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210234907.9A Active CN114661087B (en) | 2022-03-09 | 2022-03-09 | Reference voltage source with bias current matching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114661087B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN104714588A (en) * | 2015-01-05 | 2015-06-17 | 江苏芯力特电子科技有限公司 | Low temperature drift band-gap reference voltage source based on VBE linearization |
| CN104850167A (en) * | 2014-02-18 | 2015-08-19 | 亚德诺半导体集团 | Low power proportional to absolute temperature current and voltage generator |
| CN112034922A (en) * | 2020-11-06 | 2020-12-04 | 成都铱通科技有限公司 | Positive temperature coefficient bias voltage generating circuit with accurate threshold |
-
2022
- 2022-03-09 CN CN202210234907.9A patent/CN114661087B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN104850167A (en) * | 2014-02-18 | 2015-08-19 | 亚德诺半导体集团 | Low power proportional to absolute temperature current and voltage generator |
| CN104714588A (en) * | 2015-01-05 | 2015-06-17 | 江苏芯力特电子科技有限公司 | Low temperature drift band-gap reference voltage source based on VBE linearization |
| CN112034922A (en) * | 2020-11-06 | 2020-12-04 | 成都铱通科技有限公司 | Positive temperature coefficient bias voltage generating circuit with accurate threshold |
Non-Patent Citations (1)
| Title |
|---|
| 王宇奇: ""BiCMOS带隙基准电压源的设计及应用"", 《微电子技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114661087B (en) | 2022-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113359929B (en) | Band-gap reference circuit and low-offset high-power-supply-rejection-ratio band-gap reference source | |
| WO2023097857A1 (en) | Bandgap reference voltage circuit and bandgap reference voltage compensation method | |
| CN113050743B (en) | Current reference circuit capable of outputting multiple temperature coefficients | |
| CN114489221B (en) | Band-gap reference voltage source circuit and band-gap reference voltage source | |
| CN111045470B (en) | Band-gap reference circuit with low offset voltage and high power supply rejection ratio | |
| CN108052151B (en) | Band-gap reference voltage source of no-clamping operational amplifier | |
| CN117055681A (en) | Band gap reference circuit with high-order temperature compensation | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN116679789A (en) | Band-gap reference voltage source adopting second-order temperature compensation and working method thereof | |
| CN114661087B (en) | Reference voltage source with bias current matching | |
| CN112433556A (en) | Improved band-gap reference voltage circuit | |
| CN114546019B (en) | Temperature coefficient adjustable reference voltage source | |
| CN112256078B (en) | Positive temperature coefficient current source and zero temperature coefficient current source | |
| CN104820460A (en) | Bandgap voltage reference source circuit | |
| CN114489222A (en) | Band-gap reference circuit for power supply chip | |
| TWI714188B (en) | Reference voltage generation circuit | |
| CN112260655A (en) | Folding operational amplifier and band-gap reference circuit with asymmetric triode input | |
| JPH02191012A (en) | Voltage generating circuit | |
| CN111061329A (en) | Band-gap reference circuit with high loop gain and double loop negative feedback | |
| CN113485511B (en) | Band gap reference circuit with low temperature coefficient | |
| CN114706442B (en) | Low-power consumption band-gap reference circuit | |
| CN114115422B (en) | Band gap reference circuit | |
| CN218825340U (en) | High-voltage second-order compensation band-gap reference circuit | |
| US9588538B2 (en) | Reference voltage generation circuit | |
| Qi et al. | A wide input low quiescent current without operational amplifier bandgap reference circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |