CN114489222A - Band-gap reference circuit for power supply chip - Google Patents

Band-gap reference circuit for power supply chip Download PDF

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CN114489222A
CN114489222A CN202210125137.4A CN202210125137A CN114489222A CN 114489222 A CN114489222 A CN 114489222A CN 202210125137 A CN202210125137 A CN 202210125137A CN 114489222 A CN114489222 A CN 114489222A
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transistor
resistor
pmos transistor
npn
circuit
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周前能
杜永彪
李红娟
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Chongqing University of Post and Telecommunications
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Chongqing University of Post and Telecommunications
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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Abstract

The invention provides a band-gap reference circuit for a power supply chip, which comprises a starting circuit, a band-gap reference core circuit and a temperature compensation circuit. The invention adopts the clamping technology of a current mirror and a current source to ensure that an NPN triode Q1 and an NPN triode Q4 have the same collector voltage and the same base voltage, so that equal positive temperature coefficient current flows through a resistor R5 branch and a resistor R6 branch, and further positive temperature coefficient voltage is generated on a resistor R4 and a resistor R5 and first-order band gap reference voltage is generated with the base-emitter voltage of the NPN triode Q2; a reverse bias PN junction is obtained by adopting a base electrode and emitter electrode short circuit technology of an NPN triode, high-order temperature compensation current is generated by utilizing saturation current of the reverse bias PN junction, and high-order temperature compensation is carried out on first-order band gap reference voltage, so that the high-performance band gap reference circuit for the power supply chip is realized.

Description

Band-gap reference circuit for power supply chip
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a band-gap reference circuit for a power supply chip.
Background
With the increasing popularity of portable electric devices, the power supply chip provides different power supply voltages for different components of the same product, which requires higher conversion efficiency and higher stability of the power supply chip. The band-gap reference circuit is one of core modules of the power supply chip and provides bias for related functional sub-modules of the power supply chip so as to influence the performance characteristics of the power supply chip; with the development of integrated circuit technology, the performance requirements of the power supply chip on the internal bandgap reference voltage source are higher and higher.
FIG. 1 shows a conventional bandgap reference circuit, which mainly comprises an NPN transistor Q1 and an NPN transistorPole tube Q2, resistor R1, resistor R2, resistor R3, resistor R4 and amplifier A1. All resistors are made of the same material, the emitter area of the NPN triode Q1 is M times that of the NPN triode Q2, the resistor R3 is identical to the resistor R4, and the low-frequency gain A of the amplifier A1dHas Ad>>1, the NPN triode Q1 has the same collector current as the NPN triode Q2, and the output voltage V of the band gap reference circuitREFIs composed of
Figure BDA0003500134790000011
Wherein, VBE2Is the base-emitter voltage, R, of an NPN transistor Q21Is the resistance of a resistor R1, R2Is the impedance of the resistor R2, k is the boltzmann constant, T is the absolute temperature, and q is the amount of electron charge. The reference voltage V with zero temperature drift characteristic can be obtained within a certain temperature range by optimizing the resistance values of the resistor R1 and the resistor R2, the parameter N and the likeREF. Due to VBE2The temperature nonlinearity exists, so that the output voltage of the traditional first-order bandgap reference circuit has the problem of high temperature drift coefficient, and the application of the traditional first-order bandgap reference circuit in a high-precision system is greatly limited.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A bandgap reference circuit for a power supply chip is provided. The technical scheme of the invention is as follows:
a bandgap reference circuit for a power supply chip, comprising: the temperature compensation circuit comprises a starting circuit, a band-gap reference core circuit and a temperature compensation circuit, wherein the signal output end of the starting circuit is connected with the starting signal input end of the band-gap reference core circuit, the signal output end of the temperature compensation circuit is connected with the electric signal input end of the band-gap reference core circuit, and the signal output end of the band-gap reference core circuit is connected with the signal input end of the starting circuit; the starting circuit provides a starting signal for the band-gap reference core circuit, and the band-gap reference core circuit generates positive temperature coefficient voltage and weights the positive temperature coefficient voltage and the negative temperature coefficient NPN triode base electrode-emitter voltage to obtain first-order band-gap reference voltage VREF1The temperature compensation circuit passes PMThe OS tube M16 provides a current with a high-order temperature coefficient for the band-gap reference core circuit and compensates for a band-gap reference voltage.
Further, the start-up circuit includes: a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, and a resistor R1, wherein a source of the PMOS transistor M1 is connected to an external power VDD, a gate of the PMOS transistor M1 is connected to a drain of the PMOS transistor M1 and one end of the resistor R1, another end of the resistor R1 is connected to a gate of the NMOS transistor M5 and a drain of the NMOS transistor M2, a source of the NMOS transistor M2 is connected to a drain of the NMOS transistor M3, a gate of the NMOS transistor M3 is connected to a gate of the NMOS transistor M4 and an enable terminal EN, a source of the NMOS transistor M3 is connected to a source of the NMOS transistor M4 and an external ground GND, and a source of the NMOS transistor M5 is connected to a drain of the NMOS transistor M4.
Further, the bandgap reference core circuit includes: a PMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, and an NPN transistor Q4, wherein a source of the PMOS transistor M6 is connected to a source of the PMOS transistor M9, a source of the PMOS transistor M11, and an external power supply VDD, a drain of the PMOS transistor M11 is connected to a source of the PMOS transistor M11, a drain of the PMOS transistor M11 is connected to a gate of the PMOS transistor M11, and a gate of the resistor R11, and a drain of the PMOS transistor M11 are connected to a drain of the NMOS transistor M11, a drain of the transistor M11, a source of the transistor M11, a drain of the transistor M11, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor, the source of the PMOS transistor M10 is connected to the gate of the NMOS transistor M2 and one end of the resistor R3, the other end of the resistor R3 is connected to the gate of the NMOS transistor M8, one end of the resistor R4, the gate of the NMOS transistor M13, and the output terminal VREF, the other end of the resistor R4 is connected to one end of the resistor R5, one end of the resistor R6 and the drain of the PMOS transistor M16, the other end of the resistor R5 is connected to the base of the NPN transistor Q1, the base of the transistor Q2, and one end of the resistor R7, the other end of the resistor R7 is connected to the collector of the NPN transistor Q2 and the base of the NPN transistor Q3, the other end of the resistor R6 is connected to the base of the NPN transistor Q6 and the collector of the NPN transistor Q6, the emitter of the NPN Q6 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the emitter of the transistor Q6, the emitter of the transistor Q6, the emitter of the NPN, the transistor 6, the emitter, the ground, and the GND, the drain electrode of the PMOS tube M11 is connected with the source electrode of the PMOS tube M12, the drain electrode of the PMOS tube M12 is connected with the drain electrode of the NMOS tube M13, and the source electrode of the NMOS tube M13 is connected with the collector electrode of the NPN triode Q4.
Further, the temperature compensation circuit includes: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a PMOS transistor M16, and an NPN transistor Q5, wherein a source of the PMOS transistor M13 is connected to a source of the PMOS transistor M15 and an external power supply VDD, a gate of the PMOS transistor M13 is connected to a drain of the PMOS transistor M13, a source of the PMOS transistor M14, and a gate of the PMOS transistor M15, a gate of the PMOS transistor M14 is connected to a gate of the PMOS transistor M16, a drain of the PMOS transistor M14, and a collector of the NPN transistor Q5, a base of the NPN transistor Q5 is connected to an emitter of the NPN transistor Q5 and an external ground GND, and a drain of the PMOS transistor M15 is connected to a source of the PMOS transistor M16.
Furthermore, in the band gap reference core circuit, all resistors are made of the same material, the direct current amplification factor beta of all NPN triodes is far greater than 1, and the base current I of all NPN triodesbAll can be ignored; the NPN transistor Q1 and the NPN transistor Q2 form a current mirror and are completely the same, and the NPN transistor Q1 and the NPN transistor Q2 have the same collector current; the emitter area of the NPN triode Q4 is alpha times of the NPN triode Q1, the channel width-length ratio of the PMOS transistor M11 is alpha times of the PMOS transistor M6, the channel width-length ratio of the PMOS transistor M12 is alpha times of the PMOS transistor M7, and the channel width-length ratio of the NMOS transistor M13 is alpha times of the NMOS transistor M8, so that the NPN triode Q1 and the NPN triode Q4 have the same collector voltage and the same base voltage; meanwhile, the resistor R5 is the same as the resistor R6, the channel width-to-length ratio of the PMOS transistor M9 is 2 times that of the PMOS transistor M6, the channel width-to-length ratio of the PMOS transistor M10 is 2 times that of the PMOS transistor M7, the emitter area of the NPN triode Q3 is N times that of the NPN triode Q2, and the collector current I of the NPN triode Q1 is equal to that of the resistor R6C1Collector current I of NPN triode Q2C2、NPCollector current I of N triode Q3C3With the current I flowing through the resistor R4R4Has IR4＝2IC1＝2IC2＝2IC3＝2kT(ln N)/[q(R7+R8)]Where k is Boltzmann's constant, T is absolute temperature, q is the amount of electron charge, R7Is the resistance of resistor R7, R8Is the resistance of resistor R8. Current I flowing through resistor R4R4First-order band-gap voltage V generated by band-gap reference output end VREFREF1Is composed of
Figure BDA0003500134790000041
Wherein VBE2Is the base-emitter voltage, R, of an NPN transistor Q24Is the resistance of resistor R4, R5Is the resistance of resistor R5.
Furthermore, in the temperature compensation circuit, the NPN triode Q5 adopts a short circuit of a base electrode and an emitter electrode to enable a collector electrode-base electrode to form a reverse bias PN junction, the channel width-length ratio of the PMOS tube M15 is beta times of that of the PMOS tube M13, the channel width-length ratio of the PMOS tube M16 is beta times of that of the PMOS tube M14, and then the drain current I of the PMOS tube M1616Is composed of
Figure BDA0003500134790000042
Where b is a scaling factor, m is a constant equal to about-3/2, EgIs the bandgap energy of silicon.
Further, the output voltage V of the band-gap reference circuit for the power supply chipREFIs composed of
Figure BDA0003500134790000043
Wherein VREF1For a first-order bandgap reference voltage obtained by weighting a positive temperature coefficient voltage with a negative temperature coefficient voltage, factor
Figure BDA0003500134790000044
Compensation VREF1Thereby obtaining a bandgap reference voltage V for high-order temperature compensation of the power chipREF。
The invention has the following advantages and beneficial effects:
the band-gap reference circuit for the power chip is characterized in that a current mirror and a current source clamping technology are adopted, so that an NPN triode Q1 and an NPN triode Q4 have the same collector voltage and the same base voltage, equal positive temperature coefficient currents flow through a resistor R5 branch and a resistor R6 branch, and then positive temperature coefficient voltages are generated on a resistor R4 and a resistor R5 and are equal to a base-emitter voltage V of the NPN triode Q2BE2Generating a first-order temperature compensation band gap voltage; meanwhile, a collector-base electrode of the NPN triode forms a reverse bias PN junction by adopting a base electrode and emitter electrode short circuit technology, high-order temperature compensation current is generated by utilizing saturation current of the reverse bias PN junction, and high-order temperature compensation is carried out on first-order temperature compensation band gap voltage, so that high-performance band gap reference voltage for a power supply chip is obtained.
Drawings
FIG. 1 is a schematic diagram of a conventional first order bandgap reference circuit of the present invention;
FIG. 2 is a schematic diagram of a bandgap reference circuit for a power chip according to a preferred embodiment of the present invention;
fig. 3 is a simulation diagram of the output voltage temperature characteristic of the bandgap reference circuit for power supply chip according to the preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
in the embodiment of the present application, the clamping technique of the current mirror and the current source is adopted to make the NPN transistor Q1 and the NPN transistor Q4 have the same collector voltage and the same base voltage, so that the branch of the resistor R5 and the branch of the resistor R6 flow the same positive temperature coefficient current, and further the positive temperature coefficient voltage is generated on the resistor R4 and the resistor R5 and is equal to the base-emitter voltage V of the NPN transistor Q2BE2Generating a first-order temperature compensation band gap voltage; meanwhile, a base electrode and an emitting electrode of the NPN triode are short-circuited by adopting a base electrode and emitting electrode short-circuit technology, so that the NPN triode is integratedAnd a reverse bias PN junction is formed by the electrode-base electrode, high-order temperature compensation current is generated by utilizing the saturation current of the reverse bias PN junction, and high-order temperature compensation is carried out on the first-order temperature compensation band gap voltage, so that high-performance band gap reference voltage for the power supply chip is obtained.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and specific embodiments.
Examples
A band-gap reference circuit for a power supply chip is shown in figure 2 and comprises a starting circuit 1, a band-gap reference core circuit 2 and a temperature compensation circuit 3;
the signal output end of the starting circuit 1 is connected with the starting signal input end of the band-gap reference core circuit 2, the signal output end of the temperature compensation circuit 3 is connected with the electrical signal input end of the band-gap reference core circuit 2, the signal output end of the band-gap reference core circuit 2 is connected with the signal input end of the starting circuit 1, the band-gap reference core circuit 2 generates band-gap reference voltage, and the temperature compensation circuit 3 compensates the band-gap reference voltage generated by the band-gap reference core circuit 2 to obtain the band-gap reference voltage with low temperature drift coefficient;
the starting circuit 1 enables the band gap reference circuit to normally work and generate band gap reference voltage output, the band gap reference core circuit 2 generates positive temperature coefficient voltage and carries out weighting with base electrode-emitter voltage of an NPN triode with a negative temperature coefficient to obtain first-order band gap reference voltage VREF1The temperature compensation circuit 3 provides a current with a high-order temperature coefficient to the bandgap reference core circuit 2 through a PMOS transistor M16 and compensates the bandgap reference voltage, so as to obtain a bandgap reference voltage with high-order temperature compensation.
The starting circuit 1 only plays a role when the band gap reference circuit is electrified, and stops working after the band gap reference circuit is started, so that the influence of the starting circuit on a following circuit is avoided.
As a preferred technical solution, as shown in fig. 2, the starting circuit 1 includes: a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, and a resistor R1, wherein a source of the PMOS transistor M1 is connected to an external power supply VDD, a gate of the PMOS transistor M1 is connected to a drain of the PMOS transistor M1 and one end of the resistor R1, another end of the resistor R1 is connected to a gate of the NMOS transistor M5 and a drain of the NMOS transistor M2, a source of the NMOS transistor M2 is connected to a drain of the NMOS transistor M3, a gate of the NMOS transistor M3 is connected to a gate of the NMOS transistor M4 and an enable terminal EN, a source of the NMOS transistor M3 is connected to a source of the NMOS transistor M4 and an external ground GND, and a source of the NMOS transistor M5 is connected to a drain of the NMOS transistor M4;
the band gap reference core circuit 2 includes: a PMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, and an NPN transistor Q4, wherein a source of the PMOS transistor M6 is connected to a source of the PMOS transistor M9, a source of the PMOS transistor M11, and an external power supply VDD, a drain of the PMOS transistor M11 is connected to a source of the PMOS transistor M11, a drain of the PMOS transistor M11 is connected to a gate of the PMOS transistor M11, and a gate of the resistor R11, and a drain of the PMOS transistor M11 are connected to a drain of the NMOS transistor M11, a drain of the transistor M11, a source of the transistor M11, a drain of the transistor M11, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor, the source of the PMOS transistor M10 is connected to the gate of the NMOS transistor M2 and one end of the resistor R3, the other end of the resistor R3 is connected to the gate of the NMOS transistor M8, one end of the resistor R4, the gate of the NMOS transistor M13, and the output terminal VREF, the other end of the resistor R4 is connected to one end of the resistor R5, one end of the resistor R6 and the drain of the PMOS transistor M16, the other end of the resistor R5 is connected to the base of the NPN transistor Q1, the base of the transistor Q2, and one end of the resistor R7, the other end of the resistor R7 is connected to the collector of the NPN transistor Q2 and the base of the NPN transistor Q3, the other end of the resistor R6 is connected to the base of the NPN transistor Q6 and the collector of the NPN transistor Q6, the emitter of the NPN Q6 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the emitter of the transistor Q6, the emitter of the transistor Q6, the emitter of the NPN, the transistor 6, the emitter, the ground, and the GND, the drain electrode of the PMOS tube M11 is connected with the source electrode of the PMOS tube M12, the drain electrode of the PMOS tube M12 is connected with the drain electrode of the NMOS tube M13, and the source electrode of the NMOS tube M13 is connected with the collector electrode of an NPN triode Q4;
the temperature compensation circuit 3 includes: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a PMOS transistor M16, and an NPN transistor Q5, wherein a source of the PMOS transistor M13 is connected to a source of the PMOS transistor M15 and an external power supply VDD, a gate of the PMOS transistor M13 is connected to a drain of the PMOS transistor M13, a source of the PMOS transistor M14, and a gate of the PMOS transistor M15, a gate of the PMOS transistor M14 is connected to a gate of the PMOS transistor M16, a drain of the PMOS transistor M14, and a collector of the NPN transistor Q5, a base of the NPN transistor Q5 is connected to an emitter of the NPN transistor Q5 and an external ground GND, and a drain of the PMOS transistor M15 is connected to a source of the PMOS transistor M16.
In the band gap reference core circuit 2, all resistors are made of the same material, the direct current amplification factor beta of all NPN triodes is far greater than 1, and the base current I of all NPN triodesbAre all negligible (i.e. I)b0) is approximately distributed; the NPN transistor Q1 and the NPN transistor Q2 form a current mirror and are identical, and the collector current I of the NPN transistor Q1 is equal to the collector current IC1Collector current I of NPN triode Q2C2Has IC1＝IC2(ii) a The emitter area of the NPN triode Q4 is alpha times of the NPN triode Q1, the channel width-length ratio of the PMOS transistor M11 is alpha times of the PMOS transistor M6, the channel width-length ratio of the PMOS transistor M12 is alpha times of the PMOS transistor M7, and the channel width-length ratio of the NMOS transistor M13 is alpha times of the NMOS transistor M8, so that the NPN triode Q1 and the NPN triode Q4 have the same collector voltage and the same base voltage; meanwhile, the resistor R5 is the same as the resistor R6, the channel width-length ratio of the PMOS transistor M9 is 2 times of that of the PMOS transistor M6, the channel width-length ratio of the PMOS transistor M10 is 2 times of that of the PMOS transistor M7, and the collector current I of the NPN triode Q1C1Collector current I of NPN triode Q2C2Collector current I of NPN triode Q3C3With the current I flowing through the resistor R4R4Has IR4＝2IC1＝2IC2＝2IC3(ii) a The emitter area of NPN transistor Q3 is N times that of NPN transistor Q2, and current flowsCurrent I through resistor R4R4Is provided with
Figure BDA0003500134790000081
Wherein k is Boltzmann's constant, T is absolute temperature, q is amount of electron charge, and R is7Is the resistance of resistor R7, R8Is the resistance of resistor R8. The current I flowing through the resistor R4R4First-order band-gap voltage V generated by band-gap reference output end VREFREF1Is composed of
Figure BDA0003500134790000091
In the formula, VBE2Is the base-emitter voltage, R, of an NPN transistor Q24Is the resistance of resistor R4, R5Is the resistance of resistor R5. VBE2Having a negative temperature coefficient, factor
Figure BDA0003500134790000092
Has positive temperature coefficient, so that the first-order band-gap reference voltage V can be obtained by optimizing corresponding parametersREF1。
Further, to compensate for VREF1The temperature nonlinearity is realized by adopting the temperature compensation circuit 3, wherein the base electrode of the NPN triode Q5 is in short circuit with the emitter electrode, so that a reverse bias PN junction is formed by the collector electrode-base electrode of the NPN triode Q5, and the current I flows through the reverse bias PN junction formed by the NPN triode Q5SAs a function of temperature T IS(T) is
Figure BDA0003500134790000093
Where b is a scaling factor, m is a constant equal to about-3/2, EgIs the bandgap energy of silicon. The channel width-length ratio of the PMOS tube M15 is beta times of that of the PMOS tube M13, the channel width-length ratio of the PMOS tube M16 is beta times of that of the PMOS tube M14, and the drain current I of the PMOS tube M1616Is composed of
Figure BDA0003500134790000094
As can be seen from equations (2) and (4), the output voltage V of the bandgap reference circuit for the power supply chipREFIs composed of
Figure BDA0003500134790000095
In the formula, voltage VREFComprising 2 factors, factor VREF1For a first-order bandgap reference voltage obtained by weighting a positive temperature coefficient voltage with a negative temperature coefficient voltage, factor
Figure BDA0003500134790000096
Compensation VREF1Thereby obtaining a bandgap reference voltage V for high-order temperature compensation of the power chipREF。
FIG. 3 shows the output voltage V of the bandgap reference circuit for power supply chip according to the present inventionREFThe abscissa is the temperature T and the ordinate is the output voltage of the bandgap reference. Simulation results show that the output voltage V of the band-gap reference circuit for the power supply chip is within the temperature range of-40 ℃ to 150 DEG CREFThe temperature coefficient of (a) is only 1.76 ppm/DEG C.
In the above embodiments of the present application, a bandgap reference circuit for a power supply chip includes a start-up circuit, a bandgap reference core circuit, and a temperature compensation circuit. In the embodiment of the application, the clamping technology of the current mirror and the current source is adopted to enable the NPN triode Q1 and the NPN triode Q4 to have the same collector voltage and the same base voltage, so that equal positive temperature coefficient currents flow through the branch of the resistor R5 and the branch of the resistor R6, and then positive temperature coefficient voltages are generated on the resistor R4 and the resistor R5 and are equal to the base-emitter voltage V of the NPN triode Q2BE2Generating a first-order temperature compensation band gap voltage; meanwhile, a collector-base electrode of the NPN triode forms a reverse bias PN junction by adopting a base electrode and emitter electrode short-circuit technology, and saturation of the reverse bias PN junction is utilizedAnd generating a high-order temperature compensation current by the current and performing high-order temperature compensation on the first-order temperature compensation band gap voltage so as to obtain a high-performance band gap reference voltage for the power supply chip.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.

Claims (7)

1. A bandgap reference circuit for a power supply chip, comprising: the temperature compensation circuit comprises a starting circuit (1), a band-gap reference core circuit (2) and a temperature compensation circuit (3), wherein the signal output end of the starting circuit (1) is connected with the starting signal input end of the band-gap reference core circuit (2), the signal output end of the temperature compensation circuit (3) is connected with the electric signal input end of the band-gap reference core circuit (2), and the signal output end of the band-gap reference core circuit (2) is connected with the signal input end of the starting circuit (1); the starting circuit (1) provides a starting signal for the band-gap reference core circuit (2), and the band-gap reference core circuit (2) generates positive temperature coefficient voltage and weights the positive temperature coefficient voltage with negative temperature coefficient NPN triode base electrode-emitter voltage to obtain first-order band-gap reference voltage VREF1The temperature compensation circuit (3) provides a current with a high-order temperature coefficient to the bandgap reference core circuit (2) through a PMOS (P-channel metal oxide semiconductor) tube M16 and compensates the bandgap reference voltage, so that the bandgap reference voltage with high-order temperature compensation is obtained.
2. The bandgap reference circuit for power supply chip as claimed in claim 1,
the start-up circuit (1) comprises: PMOS transistor M1, NMOS transistor M2,、A NMOS transistor M3, a NMOS transistor M4, a NMOS transistor M5 and a resistor R1, wherein the source of the PMOS transistor M1 is connected with an external power supply VDD, the gate of the PMOS transistor M1 is respectively connected with the drain of the PMOS transistor M1 and one end of the resistor R1, and the other end of the resistor R1 is respectively connected with the gate of the NMOS transistor M5 and the drain of the NMOS transistor M2The source electrode of the NMOS tube M2 is connected with the drain electrode of the NMOS tube M3, the grid electrode of the NMOS tube M3 is respectively connected with the grid electrode of the NMOS tube M4 and the enable end EN, the source electrode of the NMOS tube M3 is respectively connected with the source electrode of the NMOS tube M4 and the external ground GND, and the source electrode of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M4.
3. The bandgap reference circuit for power supply chip as recited in claim 1,
the bandgap reference core circuit (2) comprises: a PMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, and an NPN transistor Q4, wherein a source of the PMOS transistor M6 is connected to a source of the PMOS transistor M9, a source of the PMOS transistor M11, and an external power supply VDD, a drain of the PMOS transistor M11 is connected to a source of the PMOS transistor M11, a drain of the PMOS transistor M11 is connected to a gate of the PMOS transistor M11, and a gate of the resistor R11, and a drain of the PMOS transistor M11 are connected to a drain of the NMOS transistor M11, a drain of the transistor M11, a source of the transistor M11, a drain of the transistor M11, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor M11 of the transistor, a drain of the transistor, the source of the PMOS transistor M10 is connected to the gate of the NMOS transistor M2 and one end of the resistor R3, the other end of the resistor R3 is connected to the gate of the NMOS transistor M8, one end of the resistor R4, the gate of the NMOS transistor M13, and the output terminal VREF, the other end of the resistor R4 is connected to one end of the resistor R5, one end of the resistor R6 and the drain of the PMOS transistor M16, the other end of the resistor R5 is connected to the base of the NPN transistor Q1, the base of the transistor Q2, and one end of the resistor R7, the other end of the resistor R7 is connected to the collector of the NPN transistor Q2 and the base of the NPN transistor Q3, the other end of the resistor R6 is connected to the base of the NPN transistor Q6 and the collector of the NPN transistor Q6, the emitter of the NPN Q6 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the emitter of the transistor Q6, the emitter of the transistor Q6, the emitter of the NPN, the transistor 6, the emitter, the ground, and the GND, the drain electrode of the PMOS tube M11 is connected with the source electrode of the PMOS tube M12, the drain electrode of the PMOS tube M12 is connected with the drain electrode of the NMOS tube M13, and the source electrode of the NMOS tube M13 is connected with the collector electrode of the NPN triode Q4.
4. The bandgap reference circuit for power supply chip as recited in claim 1,
the temperature compensation circuit (3) comprises: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a PMOS transistor M16, and an NPN transistor Q5, wherein a source of the PMOS transistor M13 is connected to a source of the PMOS transistor M15 and an external power supply VDD, a gate of the PMOS transistor M13 is connected to a drain of the PMOS transistor M13, a source of the PMOS transistor M14, and a gate of the PMOS transistor M15, a gate of the PMOS transistor M14 is connected to a gate of the PMOS transistor M16, a drain of the PMOS transistor M14, and a collector of the NPN transistor Q5, a base of the NPN transistor Q5 is connected to an emitter of the NPN transistor Q5 and an external ground GND, and a drain of the PMOS transistor M15 is connected to a source of the PMOS transistor M16.
5. The bandgap reference circuit for power supply chip as claimed in claim 3,
in the band-gap reference core circuit (2), base currents I of all NPN triodesbNegligible, the NPN triode Q1 is identical to the NPN triode Q2 and has the same collector current, the emitter area of the NPN triode Q4 is α times of the NPN triode Q1, the channel width-length ratio of the PMOS transistor M11 is α times of the PMOS transistor M6, the channel width-length ratio of the PMOS transistor M12 is α times of the PMOS transistor M7, and the channel width-length ratio of the NMOS transistor M13 is α times of the NMOS transistor M8, so that the NPN triode Q1 and the NPN triode Q4 have the same collector voltage and the same base voltage; meanwhile, the resistor R5 is the same as the resistor R6, the channel width-to-length ratio of the PMOS transistor M9 is 2 times that of the PMOS transistor M6, the channel width-to-length ratio of the PMOS transistor M10 is 2 times that of the PMOS transistor M7, the emitter area of the NPN triode Q3 is N times that of the NPN triode Q2, and the collector current I of the NPN triode Q1 is equal to that of the resistor R6C1Collector current I of NPN triode Q2C2Collector current I of NPN triode Q3C3With the current I flowing through the resistor R4R4Has IR4＝2IC1＝2IC2＝2IC3＝2kT(lnN)/[q(R7+R8)]Where k is Boltzmann's constant, T is absolute temperature, q is the amount of electronic charge, R7Is the resistance of resistor R7, R8Is the resistance of resistor R8;
current I flowing through resistor R4R4First-order band-gap voltage V generated by band-gap reference output end VREFREF1Is composed of
Figure FDA0003500134780000031
Wherein VBE2Is the base-emitter voltage, R, of an NPN transistor Q24Is the resistance of resistor R4, R5Is the resistance of resistor R5.
6. The bandgap reference circuit for power supply chip as claimed in claim 4,
in the temperature compensation circuit (3), an NPN triode Q5 adopts a short circuit of a base electrode and an emitter electrode to enable a collector electrode-base electrode to form a reverse bias PN junction, the channel width-length ratio of a PMOS tube M15 is beta times of that of a PMOS tube M13, the channel width-length ratio of a PMOS tube M16 is beta times of that of a PMOS tube M14, and then the drain current I of the PMOS tube M16 is16Is composed of
Figure FDA0003500134780000032
Where b is a scaling factor, m is a constant equal to about-3/2, EgIs the bandgap energy of silicon, k is the boltzmann constant, and T is the absolute temperature.
7. The bandgap reference circuit for power supply chip according to claim 6,
the output voltage V of the band-gap reference circuit for the power supply chipREFIs composed of
Figure FDA0003500134780000033
Wherein R is5Beta is the ratio of the channel width to length ratio of the PMOS transistor M16 and the PMOS transistor M14, b is a proportionality coefficient, M is a constant approximately equal to-3/2, E is the resistance value of the resistor R5gIs the band gap energy of silicon, k is the Boltzmann constant, T is the absolute temperature, VREF1A first order bandgap reference voltage, factor, generated for the bandgap reference core circuit (2)
Figure FDA0003500134780000041
Compensation VREF1Thereby obtaining a high-order temperature compensated bandgap reference voltage.
CN202210125137.4A 2022-02-10 2022-02-10 Band-gap reference circuit for power supply chip Pending CN114489222A (en)

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