CN114649306B - 用于改进的附接位置的掩模设计 - Google Patents

用于改进的附接位置的掩模设计 Download PDF

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CN114649306B
CN114649306B CN202111048672.6A CN202111048672A CN114649306B CN 114649306 B CN114649306 B CN 114649306B CN 202111048672 A CN202111048672 A CN 202111048672A CN 114649306 B CN114649306 B CN 114649306B
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semiconductor package
substrate
over
package
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CN114649306A (zh
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C·O·金
K·H·朴
J·H·郑
O·关
J·W·李
Y·J·张
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

一种半导体器件具有半导体封装，所述半导体封装包括具有接点栅格阵列的基板。组件设置在基板之上。在组件之上沉积封装物。接点栅格阵列保持在封装物之外。具有基准标记的金属掩模设置在接点栅格阵列之上。在半导体封装之上形成屏蔽层。在形成屏蔽层之后去除金属掩模。

Description

用于改进的附接位置的掩模设计
技术领域
本发明一般涉及半导体制造，并且更特别地涉及一种用于使用针对改进的附接定位而设计的掩模来形成选择性电磁干扰（EMI）的半导体器件和方法。
背景技术
半导体器件通常在现代电子产品中找到。半导体器件执行各种各样的功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子设备、将太阳光转换成电以及为电视显示器创建可视图像。半导体器件在通信、功率转换、网络、计算机、娱乐和消费者产品的领域中找到。半导体器件也在军事应用、航空、汽车、工业控制器和办公设备中找到。
半导体器件通常易受电磁干扰（EMI）、射频干扰（RFI）、谐波失真或其他器件间干扰的影响，例如电容、电感或导电耦合，也称为串扰，其可能干扰它们的操作。高速模拟电路（例如射频（RF）滤波器）或数字电路也产生干扰。
导电层通常形成在半导体封装之上以屏蔽封装内的电子零件免受EMI和其他干扰的影响。屏蔽层在信号可能碰到封装内的半导体管芯和分立组件之前吸收EMI，其否则可能故障。屏蔽层也形成在具有被预期成产生EMI的组件的封装之上以保护附近的器件。
半导体封装屏蔽的现有技术方法存在的一个问题是在封装之上形成屏蔽层完全覆盖了封装的顶部。许多半导体封装需要具有暴露的插座或端子的开口区域，其允许连接到相邻的半导体器件，或者需要在屏蔽层之外具有一些组件以执行它们的适当功能。遗憾的是，传统的屏蔽完全覆盖了封装，并且将使任何暴露的端子、插座或其他暴露的组件短路。带掩模已经用于形成部分屏蔽的封装。然而，带掩模具有在溅射之后层压掩模然后剥离掩模的复杂工艺要求。因此，需要具有选择性地形成的EMI屏蔽的半导体器件。
附图说明
图1a-1c示出具有由切道分开的多个半导体管芯的半导体晶片；
图2a-2m示出使用预成形掩模来选择性地形成屏蔽层；
图3示出具有选择性形成的屏蔽层的半导体器件；
图4a-4c示出可能导致制造缺陷的错位掩模；
图5a和5b示出具有基准标记以改善对准的预成形掩模；
图6示出具有彩色阳极化以改善对准的掩模；
图7示出具有二维条形码的掩模；以及
图8a和8b示出将选择性屏蔽的封装集成到电子设备中。
具体实施方式
在以下描述中，参考附图在一个或多个实施例中描述本发明，其中，相同的附图标记表示相同或相似的要素。虽然根据用于实现本发明的目的的最佳模式描述了本发明，但是本领域技术人员应当理解，本发明旨在覆盖可以包括在本发明的精神和范围内的替代、修改和等同物，其由所附权利要求以及以下公开和附图所支持的它们的等同物来限定。如本文所使用的术语“半导体管芯”指代词语的单数形式和复数形式两者，并且因此可指代单个半导体器件和多个半导体器件两者。术语“管芯”和“半导体管芯”可互换使用。
半导体器件通常使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含电连接以形成功能电路的有源和无源电组件。有源电组件（例如晶体管和二极管）具有控制电流流动的能力。无源电组件（例如电容器、电感器和电阻器）在执行电路功能所需的电压和电流之间产生关系。
后端制造是指将完成的晶片切割或单片化为单独的半导体管芯，并封装该半导体管芯以用于结构支撑、电互连和环境隔离。为了单片化半导体管芯，晶片被沿着称为切道或划线的晶片的非功能区刻划和断开。使用激光切割工具或锯条将晶片单片化。在单片化之后，将单个半导体管芯安装到封装基板，所述封装基板包括用于与其他***组件互连的引脚或接触焊盘。然后将形成在半导体管芯之上的接触焊盘连接到封装内的接触焊盘。可以用导电层、凸点、柱形凸点、导电膏、引线接合、或其他合适的互连结构来进行电连接。封装物或其他模制化合物沉积在封装之上以提供物理支撑和电隔离。然后将完成的封装***到电***中，并且使半导体器件的功能可用于其他***组件。
图1a示出了具有基底基板材料102的半导体晶片100，例如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅、或其他块体半导体材料。多个半导体管芯或组件104形成在晶片100上，由非有源、管芯间晶片区域或切道106分隔开，如上所述。切道106提供切割区域以将半导体晶片100单片化成单个半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米（mm）的宽度或直径。
图1b示出了半导体晶片100的一部分的截面图。每个半导体管芯104具有背部或非有源表面108和有源表面110，其包含模拟或数字电路，该模拟或数字电路被实现为根据管芯的电设计和功能而形成在管芯内或管芯之上并电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管和形成在有源表面110内的其他电路元件，以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、MEMS、存储器或其他信号处理电路。半导体管芯104还可含有用于RF信号处理的集成无源器件（IPD），例如电感器、电容器及电阻器。半导体晶片100的背表面108可以经历利用机械研磨或蚀刻工艺的可选的背研磨操作，以去除基底材料102的一部分并且减小半导体晶片100和半导体管芯104的厚度。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在有源表面110之上形成导电层112。导电层112包括一层或多层的铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其他合适的导电材料。导电层112用作电连接到有源表面110上的电路的接触焊盘。
导电层112可形成为与半导体管芯104的边缘相距第一距离并排设置的接触焊盘，如图1b所示。或者，导电层112可形成为接触焊盘，其在多个行中偏移，使得第一行接触焊盘设置在距管芯的边缘第一距离处，且与第一行交替的第二行接触焊盘设置在距管芯的边缘第二距离处。导电层112表示形成在半导体管芯104之上的最后的导电层，其具有用于随后电互连到较大***的接触焊盘。然而，在有源表面110上的实际半导体器件和用于信号路由的接触焊盘112之间可以形成有一个或多个中间导电和绝缘层。
使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺在导电层112之上沉积导电凸点材料。凸点材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选的助焊剂溶液。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合工艺将凸点材料接合到导电层112。在一个实施例中，通过将凸点材料加热到其熔点以上来使凸点材料回流以形成导电球或凸点114。在一个实施例中，导电凸点114形成在具有润湿层、阻挡层和粘合层的凸点下金属化（UBM）之上。导电凸点114也可以被压缩接合或热压接合到导电层112。导电凸点114代表一种类型的互连结构，其可以形成在导电层112上以电连接到基板。互连结构还可以使用接合线、导电膏、柱形凸点、微凸点或其他电互连。
在图1c中，使用锯条或激光切割工具118通过切道106将半导体晶片100单片化成单个半导体管芯104。单个半导体管芯104可以被检查和电测试，以标识KGD后单片化。
图2a示出了在选择性地形成屏蔽层之前的示例性半导体封装150的截面。在一些实施例中，半导体封装150是***级封装（SiP）器件。基板152包括与一个或多个导电层156交错的一个或多个绝缘层154。在一个实施例中，绝缘层154是其中导电层156在顶面和底面之上图案化的核心绝缘板，例如覆铜层压基板。导电层156还包括通过绝缘层154电耦合的导电通孔。
基板152可以包括任意数量的彼此交错的导电层156和绝缘层154。焊料掩模或钝化层可以形成在基板152的任一侧或两侧之上。在钝化层中形成开口以暴露导电层156的接触焊盘，以用于随后的互连。在其他实施例中，任何合适类型的基板或引线框架被用于基板152。通常，封装150形成在基板152上，作为足够大以一次形成几个到数百或数千个封装的面板。然后，通过切穿封装物168和基板152，将封装150单片化成单个封装，图2a示出了其中的一个示例。
在半导体封装150中希望被屏蔽的任何组件被安装到或设置在屏蔽区域160内的基板152之上，并且电连接到导电层156。提供屏蔽界面区域161，以用于将随后形成的屏蔽层连接到导电层156的接地条171。非屏蔽区域162包含不打算被屏蔽的其他组件。图2a示出了作为一个示例的安装在基板152上的半导体管芯104以及屏蔽区域160内的分立电组件164。分立组件164可以是无源组件（例如电容器、电阻器或电感器）、有源组件（例如二极管或晶体管）、或任何其他期望的电组件。多个半导体管芯可以设置在屏蔽区域160中。半导体管芯104可以作为更小的子封装的一部分而不是裸管芯来提供。
通过使用例如拾取和放置工艺或机器将半导体管芯设置在基板上，然后回流凸点114以将凸点物理且电连接到导电层156的暴露的接触焊盘，来将半导体管芯104安装到基板152。分立组件164通过类似的焊料凸点或焊膏166连接。焊膏166可以在拾取分立组件并将其放置到基板上之前印刷到基板152或分立组件164上。回流焊膏166将分立组件164物理且电耦合至导电层156的接触焊盘。
在将半导体管芯104、分立组件164和任何其他期望的电组件安装到屏蔽区域160内的基板152上之后，通过封装物或模制化合物168封装这些组件。使用浆料印刷、压缩模制、转移模制、液体封装物模制、真空层压、旋涂或其他合适的施加器将封装物168沉积在基板152、半导体管芯104和分立组件164之上。封装物168可以是聚合物复合材料，例如环氧树脂、环氧丙烯酸酯、或具有或不具有填料的聚合物。封装物168是不导电的，提供结构支撑，并且在环境方面保护半导体器件不受外部元件和污染物的影响。
掩模或其他机构可以用于防止封装物168覆盖屏蔽界面区域161和非屏蔽区域162。在其他实施例中，封装物168沉积在屏蔽界面区域161和非屏蔽区域162之上，然后在非屏蔽区域中被去除。在基板152的顶部之上形成的钝化层可以用作去除非屏蔽区域162和屏蔽界面区域161中的封装物时的蚀刻停止层。在去除封装物168之后，在钝化层中形成开口，以暴露接地条171和接点栅格阵列（land grid array）172的接触焊盘。
需要保持未屏蔽的任何电组件都设置在非屏蔽区域162内的基板152上或之上。在用封装物168封装之后用电组件填充非屏蔽区域162，以降低掩蔽非屏蔽区域以免被封装的复杂性。在其他实施例中，可以在沉积封装物168之前在非屏蔽区域162中的基板152上设置组件。非屏蔽区域162中的组件可以包括板对板连接器和其他物理接口、设置在基板152之上或形成为导电层156的一部分的天线、附加的分立组件164、或任何其他期望的电组件。
在图2a中，没有组件设置或形成在基板152之上的非屏蔽区域162中。导电层156的接触焊盘被暴露作为接点栅格阵列172，以用于电互连或用于在稍后阶段添加电组件。导电层156的另一部分作为接地条171在屏蔽界面区域161中暴露。图2b示出接地条171和接点栅格阵列172的俯视平面图。接点栅格阵列172提供了暴露的接触焊盘以电连接到半导体管芯104或封装150被结合到的下层器件。电连接可以通过将组件或物理端口焊接到接点栅格阵列172上来进行，或者可以使用具有弹簧针或其他合适结构的装置来进行临时连接。
图2c示出了在封装150之上形成屏蔽层期间将被用作载体的金属框架200和膜202。图2c包括图左侧的俯视图和图右侧的截面图。图2d、2e和2g类似地示出了它们各自的处理步骤的俯视图和截面图两者。框架200可由铝、铜、钢或另一合适的金属形成。或者，框架200可由塑料、木材或任何其他合适的刚性材料形成。带或膜202安装到框架200上以形成用于多个封装150的支撑基座。在一个实施例中，膜202由聚酰亚胺（PI）形成。膜202具有涂覆在膜表面上的粘合剂，以使膜粘附到金属框架200并使封装150粘合到膜。膜202上的粘合剂可以是热或紫外线（UV）剥离粘合剂。
在图2d中，使用激光切割工具206、机械冲头或任何其他合适的机构穿过膜202形成多个开口204。开口204小于封装150的覆盖区，以使封装设置在开口之上的膜202上。开口204有利于在形成屏蔽层之后从膜202去除封装150。
在图2e中，使用拾取和放置工艺或机器将封装150设置在开口204之上。基板152的底部在开口204周围始终物理地接触膜202，使得每个开口204完全被封装150覆盖。在一个实施例中，在开口204周围的膜202之上的基板152的重叠部分在基板的每侧上在0.1 mm至0.5 mm之间。在其他实施例中，开口204部分地延伸到封装150的覆盖区的外部。膜202上的粘合剂将封装140粘附到膜。
图2f示出了将被放置在非屏蔽区域162之上以阻挡屏蔽层直接形成在下层组件上的预成形掩模220。掩模220包括限定掩模腔230的侧部222、前部224、背部226和顶部228。侧部222、前部224和背部226中的每一个在所示轴的Z轴方向上具有一个高度。侧部222具有沿Y轴的宽度和沿X轴的厚度。前部224和背部226具有沿X轴的宽度和沿Y轴的厚度。顶部228具有沿Z轴的厚度、沿X轴的长度和沿Y轴的宽度。
在形成屏蔽层期间，在掩模腔230中设置接点栅格阵列172。侧部222和背部226的高度至少与基板152的顶部一样高。在其中组件设置在非屏蔽区域162内的基板152上的实施例中，掩模220被制成至少与非屏蔽区域162内的最高组件一样高。侧部222和背部226的底部可以放置在薄膜202上，其中，顶部228在接点栅格阵列172或其他组件之上延伸。前部224具有底部缘232，其沿着Z轴升高到高于侧部222和背部226的底部。缘232下方的开口提供了基板152从掩模220下方延伸至掩模外部的空间。
缘232接触或几近接触基板152的顶面，而侧部222和背部224向下延伸以用非屏蔽区域162围绕基板的端部。缘232沿X轴的长度大约等于或稍微长于基板152在相同方向上的宽度，使得侧部222接触或几近接触基板的侧部。侧部222的宽度大于非屏蔽区域162的宽度，使得当缘232放置在屏蔽界面区域161与非屏蔽区域162之间的边界上时，背部226正好位于基板152的覆盖区之外。
掩模220由金属、液晶聚合物（LCP）、塑料、聚合物、特氟隆、玻璃、橡胶、木材、膜、带、箔、其组合、或能够经受形成屏蔽层的工艺的任何其他固体材料来形成。通过模制、通过将材料片折叠或加工成所需形状、或通过任何其他合适的方式来形成掩模220。
图2g-2i示出了封装150，其中，掩模220被拾取并放置在非屏蔽区域162之上。图2g示出了俯视图和截面图，而图2h示出了透视图，并且图2i示出了详细的俯视平面图。掩模220覆盖非屏蔽区域162以在屏蔽层的溅射期间阻挡金属分子沉积在接点栅格阵列172上。屏蔽区域160和屏蔽界面区域161保持暴露以用于在那些区域之上形成屏蔽层。
在掩模220的腔230内设置接点栅格阵列172或任何期望的非屏蔽电组件。侧部222和背部226的底部靠在膜202上。前部224底部上的缘232接触或稍微高于基板152的顶面。顶部228在接点栅格阵列172的顶部之上延伸。基板152在非屏蔽区域162内的部分在侧部222之间延伸。侧部222和背部226的尺寸和位置被设成接触或几近接触基板152。
图2j示出了另一实施例，其中，封装252各自具有两个接点栅格阵列172，在基板152的两个相对侧中的每个上具有一个。每个封装使用两个掩模220来掩蔽两个接点栅格阵列。当相邻封装252的两个掩模220彼此直接相邻地设置时，在掩模之间保持至少2 mm的空间“X”。任何数量的接点栅格阵列或其他组件可以与适当成形以覆盖所有非屏蔽组件的掩模220一起使用。当组件以多组设置在基板152上时，使用多个掩模。
从图2g-2i继续，图2k示出了如箭头262所示在封装150之上溅射导电材料以形成屏蔽层260。使用任何合适的金属沉积技术（例如化学气相沉积、物理气相沉积、其他溅射方法、喷涂或电镀）来形成屏蔽层260。溅射材料可以是铜、钢、铝、金、其组合或任何其他合适的屏蔽层材料。屏蔽层260完全覆盖了封装150和掩模220的暴露表面。特别地，封装物168的所有四个侧表面和顶面都被屏蔽层260覆盖以围绕封装组件。屏蔽层260覆盖了掩模220，但是溅射的金属不穿透掩模。因此，屏蔽层260不直接形成在接点栅格阵列172上。基板152的除了在掩模220内的所有侧表面都被屏蔽层260覆盖。
在封装物168和掩模220之间的屏蔽界面区域161中的基板152的顶面被屏蔽层260覆盖。屏蔽界面区域161中的基板152的顶面包括导电层156的暴露的接地条171、或多个分立接触焊盘，屏蔽层260物理地接触其以提供到接地电压节点的电连接。在一些实施例中，导电层156的一部分暴露在基板152的侧表面处，使得屏蔽层260也物理地接触基板的侧部上的导电层。
在图2l中，去除掩模220，包括在掩模上形成的屏蔽层260的部分。可以使用与图2h中放置掩模的相同的拾取和放置机器或使用任何其他合适的机制来去除掩模220。在掩模220被去除的情况下，框架200内的区域在屏蔽层260中保持完全被覆盖，而不是在掩模220所处的接点栅格阵列172周围的屏蔽层中的开口中被覆盖。
掩模220是可重复使用的，因此拾取和放置机器可以将掩模放置到托盘或其他合适的存储介质中，以便以后重新应用到要屏蔽的下一组封装上。掩模220在多次使用之后可能会劣化，或者具有限制可以使用单独掩模的次数的另一因素。可以对特定的掩模设计进行测试，然后可以在经由测试所确定的适当的重复使用次数之后，丢弃每个掩模。金属掩模220通常可被重复使用约三十次。
在图2m中，封装150被从框架200和膜202上卸载下来。致动器270穿过开口204压在基板152的底部上，以从膜202的粘合剂剥离封装150。可施加UV光或热以减小膜202和基板152之间的粘合剂的影响。致动器270可与拾取和放置机器相呼应地在封装之间移动，所述拾取和放置机器拿起提升起来的封装150并用屏蔽封装装载JEDEC托盘、卷带或其他类似存储介质。屏蔽层260保持覆盖封装物168、基板152的侧表面的一部分、以及屏蔽界面区域161内的基板的顶面。
图3示出了完成的封装150的放大截面。屏蔽层260在所有侧部和顶部都包围半导体管芯104和分立组件164。屏蔽层260在屏蔽区域160和屏蔽界面区域161内沿着基板152的侧表面向下延伸。屏蔽层260覆盖屏蔽界面区域161内的基板152的顶面，包括物理地接触接地条171。掩模220确保了屏蔽层260不覆盖具有接点栅格阵列172的基板152的部分，使得接点栅格阵列保持可用于以后使用。
在一些实施例中，与半导体管芯104相对的基板152的底面具有在导电层156的接触焊盘上形成的焊料凸点或其他合适的互连结构，以用于将封装150附接和连接到电子设备的更大的PCB。导电层156的接触焊盘可以作为底部接点栅格阵列而保持暴露在底面上，而不是增加另一互连结构。虽然所示的工艺在形成屏蔽层260期间使用了金属框架200和膜202作为用于封装150的载体，但是也可以使用任何合适类型的载体，诸如玻璃、铝、钢、铜、聚合物、硅或其他合适材料的面板。
掩模220具有简单和成本低的优点。简单性是通过使用可以使用普通的拾取和放置处理设备来放置和去除的掩模来实现的。通过重复使用掩模220降低了成本。通过允许在与屏蔽组件（例如，半导体管芯104）相同的制造阶段期间将非屏蔽组件设置在基板152上，使整个工艺成流线型。现有技术的掩模方法（例如带掩模）要求非屏蔽区域162保持没有组件，直到形成屏蔽层并除去掩模之后。
图4a和4b示出了作为掩模300的另一实施例的覆盖区视图。图4a是顶部228的平面图，而图4b是示出了腔230的底部平面图。掩模300是使用CNC铣床、激光蚀刻、化学蚀刻或另一合适方式从铝块加工而成的。在其他实施例中，使用另一工艺来模制或形成掩模300。掩模300可由任何合适的金属、聚合物或其他材料形成。
掩模300的顶视图和底视图包括对于计算机视觉***容易可靠地区分的最小特征。即使当从底部观察掩模300时，掩模300的底面302、缘232和腔230内的表面304都处于不同的高度，视觉摄像机也不能根据给定情况下的确切角度和照明来识别特征之间的边界。
在没有任何显著的区别视觉特征的情况下，利用视觉摄像机来定位掩模300的拾取和放置机器可能会将掩模未对准地放置在封装150上，如图4c所示。图4c中的掩模300具有相对于封装150的角偏移，由符号θ（theta）表示。掩模300的侧部222应该平行于图4c中的Y轴，而前部224和背部226应该平行于X轴。然而，θ未对准导致侧部、前部和背部偏离期望定向某一角度θ。
根据掩模300相对于非屏蔽区域162的确切定位，θ偏移可能会引起多个问题。θ偏移会导致接地条171的一部分被掩模300覆盖，在这种情况下，屏蔽层260与地的连接将最终不如最初预期的那样坚固。这种制造缺陷增加了针对屏蔽层260的对地电阻，并且可能会导致屏蔽层的性能降低。另外，接点栅格阵列172的一个或多个接触焊盘可以在掩模300的保护之外，在这种情况下，屏蔽层260将被形成为延伸到暴露焊盘。出乎意料地，接点栅格阵列172接触焊盘至屏蔽层260的短路可能会导致终端设备的故障。
图5a和5b示出了在顶部228上具有基准标记322a和322b并且在腔230中的表面304上具有基准标记324a和324b的掩模320。基准标记322和324通过在掩模的彼此相对侧给摄像机两个分立的且容易看见的标记来帮助视觉摄像机θ对准掩模320。标记322a和322b沿y轴彼此对准，并且沿x轴彼此具有显著的分离。在一个实施例中，基准标记322大致位于前部224和背部226之间的中心，并且从基准中心到较近侧222的距离大致等于从前部到背部的距离的一半。基准标记324同样可以位于腔230内的三个相邻侧壁之间的中心，或者可以直接形成在基准标记322下方并与其对准。在其他实施例中，基准322和324可以形成在任何合适的位置处。
使用印刷、通过掩模的喷涂、在掩模之上刷涂、或另一合适机制将油墨、涂料或另一合适物质设置在掩模320上，以形成具有期望基准形状的物质，从而形成基准322和324。在其他实施例中，通过阳极化将颜色添加到掩模320以形成基准322和324。基准可以采用与掩模320形成对比的任何期望颜色来形成。基准可以以任何方式形成对比，无论是通过不同颜色、不同纹理、不同材料、或任何其他机器可辨别差异。不是向掩模添加有色材料或者除了向掩模添加有色材料之外，也可以通过蚀刻到掩模320的表面中来形成基准322和324。基准322和324可以以任何合适的形状来形成，例如圆形、三角形、矩形、正方形、十字形或星形。基准形状可以仅是轮廓或在形状中完全填充。
基准标记322和324在掩模320的每侧上提供视觉摄像机可以容易地区分的一对分立标记。根据视觉摄像机是位于掩模320的上方还是下方，视觉摄像机可以使用基准322或324来使掩模与封装150形成θ对准，从而确保接地条171将完全暴露在掩模外并且接点栅格阵列172将完全被掩模覆盖的高可能性。在一个实施例中，拾取和放置机器拾取掩模320，在视觉摄像机之上移动掩模，然后在将掩模设置在接点栅格阵列172上之前，使用来自视觉摄像机的反馈来确认基准324a和324b在y轴上的对准。当在形成屏蔽层260之后去除掩模时，顶部基准322还帮助视觉摄像机识别掩模320。
掩模300的另一个问题是缺乏特征对比度使得教导视觉摄像机识别掩模变得困难。图6示出了具有在腔230内的表面304的掩膜330，其被阳极化以产生阳极化表面332。表面302和缘232的底部在阳极化期间被聚酰亚胺带或其他合适的掩模覆盖，使得工艺着色了腔230的内部，同时留下围绕腔的未着色的掩模330材料的清晰可辨的轮廓。阳极化表面332在重要的视觉教导区域334处产生了容易明显的明暗边界线。阳极化后的教导区域334产生了四条直线，清楚地建立了用于视觉摄像机的掩模330的位置。教导区域334中的对比线使得训练视觉摄像机以识别掩模330变得容易。视觉摄像机的准确训练使掩模330在设置在接点栅格阵列172之上时被适当地θ对准，从而减少了制造缺陷。
可以以任何适当的方式在表面332与周围表面302和232之间提供接触。可以通过在一侧、另一侧或两侧上阳极化或以其他方式沉积材料来提供接触。阳极化可以产生可见的颜色对比度或人眼不可见但机器可检测的对比度。对比度可以是表面或下层材料的颜色、纹理、材料或任何其他特性的差异。
具有阳极化和基准标记324的掩模可以通过向表面332中钻孔或蚀刻来形成，并且在阳极化之后仅部分地穿过顶部228。钻孔去除了阳极化表面的一部分，露出原始掩模330材料的下层颜色，使得基准标记由于下层原始掩模330材料而具有颜色和阴影的对比度。在其他实施例中，基准标记324可以在阳极化之前形成，然后被掩模，使得标记不会被覆盖。基准标记324也可在阳极化之后形成在阳极化表面304的顶部上。
图7示出了在阳极化表面332上添加二维条形码342的掩模340。快速响应（QR）码是可以使用的一种类型的二维条形码的示例。在其他实施例中，可以使用将数据嵌入到表面332上的视觉表示中的其他方法。条形码342向掩模340增加了可追溯性。每个掩模340都可以具有嵌入在条形码342中的唯一标识号，其用于跟踪。计算机***可以编程地扫描条形码并且记录掩模340及其使用的扫描历史、位置、使用、应用和其他方面。利用条形码342的跟踪可以监视每个掩模340已经通过的使用次数，使得可以容易地实施重复使用限制。重复使用限制降低了掩模340将被重复使用到导致故障的磨损点的可能性。条形码342形成在腔230中的表面332上，但是可以替代地或附加地形成在顶部228上。条形码342可以直接印刷在表面332或304上，或者印刷在贴纸上然后粘附到掩模340的表面。条形码342可以与任何上述公开的实施例一起使用。
图8a和8b示出了将上述的屏蔽封装（例如，具有屏蔽层260的封装150）结合到电子设备中。图8a示出了作为电子设备400一部分的安装到印刷电路板（PCB）或其他基板402上的封装150的局部截面。凸点406形成在基板152底部上的导电层156上。导电凸点406可在制造工艺的任何阶段形成，例如，在模制封装物168之前、在单片化之前、或在形成屏蔽层260之后。凸点406回流至PCB 402的导电层404上，以将封装150物理附接并电连接至PCB。在其他实施例中，使用热压或其他合适的附接和连接方法。在一些实施例中，在封装150和PCB402之间使用粘合剂或底部填充层。半导体管芯104通过基板152和凸点406电耦合到导电层404。
图8b示出了包括PCB 402的电子设备400，其中，多个半导体封装安装在PCB的表面上，包括具有屏蔽层260和接点栅格阵列172的封装150。接点栅格阵列172可以具有焊接到或压靠接点栅格阵列的互连结构，以将封装150连接到PCB 402、PCB 402上的另一封装、相同或不同电子设备的另一PCB、另一PCB上的另一封装、另一电子设备、测试设备等。接点栅格阵列172也可以简单地暴露，以便随后临时电连接到封装150。作为替选，代替接点栅格阵列172的其他组件保持暴露以提供它们的预期功能，而没有屏蔽层260干扰。电子设备400可以具有一种类型的半导体封装、或者多种类型的半导体封装，这取决于应用。
电子设备400可以是使用半导体封装来执行一个或多个电功能的独立***。或者，电子设备400可以是较大***的子组件。例如，电子设备400可以是平板计算机、蜂窝电话、数码摄像机、通信***或其他电子设备的一部分。电子设备400还可以是图形卡、网络接口卡或***计算机的另一信号处理卡。半导体封装可包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立有源或无源器件、或其他半导体管芯或电组件。
在图8b中，PCB 402提供了用于安装在PCB上的半导体封装的结构支撑和电互连的通用基板。使用蒸发、电解电镀、化学电镀、丝网印刷或其他合适的金属沉积工艺在PCB402的表面之上或层内形成导电信号迹线404。信号迹线404提供了半导体封装、所安装的组件和其他外部***或组件之间的电通信。迹线404还根据需要向半导体封装提供了电源和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械且电附接到中间基板的技术。第二级封装涉及将中间基板机械且电附接到PCB 402。在其他实施例中，半导体器件可以仅具有第一级封装，其中，管芯直接被机械且电安装到PCB402。
为了说明的目的，在PCB 402上示出了几种类型的第一级封装，包括接合线封装446和倒装芯片448。此外，几种类型的第二级封装被示出为与封装150一起安装在PCB 402上，包括球栅格阵列（BGA）450、凸点芯片载体（BCC）452、接点栅格阵列（LGA）456、多芯片模块（MCM）458、四方扁平无引线封装（QFN）460、四方扁平封装462和嵌入式晶片级球栅格阵列（eWLB）464。导电迹线404将设置在PCB 402上的各种封装和组件电耦合到封装150，从而将封装150内的组件的使用给予PCB上的其他组件。
根据***要求，配置有第一和第二级封装类型的任何组合的半导体封装的任何组合以及其他电子组件可以连接到PCB 402。在一些实施例中，电子设备400包括单个附接的半导体封装，而其他实施例要求多个互连的封装。通过在单个基板之上组合一个或多个半导体封装，制造商可将预制组件并入到电子器件和***中。因为半导体封装包括了复杂的功能，所以可以使用较便宜的组件和流水线制造工艺来制造电子器件。所得到的器件不太可能会发生故障，并且制造成本更低，从而使消费者的成本更低。
尽管已经详细地说明了本发明的一个或多个实施例，但是本领域技术人员应当理解，在不偏离如所附权利要求中阐述的本发明的范围的情况下，可以对那些实施例进行修改和调整。

Claims (21)

1.一种制造半导体器件的方法，包括：
提供半导体封装，所述半导体封装包括，
包括接点栅格阵列的基板，
设置在所述基板之上的组件，以及
沉积在所述组件之上的封装物，其中，所述接点栅格阵列保持在所述封装物之外；
将所述半导体封装设置在载体上；
使用拾取和放置工艺或机器将包括一对基准标记的金属掩模设置在所述载体上和所述接点栅格阵列之上，其中所述金属掩模包括设置在所述接点栅格阵列之上的腔，所述接点栅格阵列设置在所述腔中；
在所述半导体封装之上形成屏蔽层；
使用所述拾取和放置工艺或机器在形成所述屏蔽层之后，去除所述金属掩模；以及
使用所述拾取和放置工艺或机器将所述金属掩模设置在第二半导体封装之上。
2.根据权利要求1所述的方法，其中，所述基准标记形成在所述金属掩模的顶面上。
3.根据权利要求1所述的方法，其中，所述基准标记形成在所述金属掩模的腔内。
4.根据权利要求1所述的方法，其中，所述金属掩模包括二维条形码。
5.根据权利要求1所述的方法，还包括阳极化所述金属掩模的第一表面，同时围绕所述第一表面的所述金属掩模的第二表面保持没有阳极化。
6.一种制造半导体器件的方法，包括：
提供半导体封装；
在所述半导体封装之上设置包括基准标记的掩模，其中所述基准标记形成在所述掩模的顶面上，并且其中所述半导体封装的一部分设置在所述掩模的腔内；
在所述半导体封装之上形成屏蔽层；以及
去除所述掩模。
7.根据权利要求6所述的方法，其中，所述掩模包括对称定位的一对基准标记。
8.根据权利要求6所述的方法，还包括在带设置在所述掩模的第二表面上的情况下阳极化所述掩模的第一表面。
9.根据权利要求6所述的方法，还包括通过训练视觉摄像机识别所述掩模来将所述掩模对准到所述半导体封装。
10.根据权利要求6所述的方法，还包括形成在所述掩模的腔中的第二基准标记。
11.根据权利要求6所述的方法，其中所述掩模包括二维条形码。
12.一种制造半导体器件的方法，包括：
提供半导体封装，其包括基板和沉积在所述基板的第一部分之上的封装物；
将所述半导体封装设置在载体上；
在所述载体上设置包括基准标记和二维条形码的掩模，其中所述掩模的顶部在所述基板的第二部分之上延伸，在所述掩模的所述顶部和所述基板之间有间隙；
在所述封装物之上形成屏蔽层；以及
去除所述掩模。
13.根据权利要求12所述的方法，其中所述掩模包括对称定位的一对基准标记。
14.根据权利要求12所述的方法，其中所述基准标记形成在所述掩模的顶面上。
15.根据权利要求12所述的方法，其中所述基准标记形成在所述掩模的腔中。
16.根据权利要求12所述的方法，还包括在带设置在所述掩模的第二表面上的情况下阳极化所述掩模的第一表面。
17.根据权利要求12所述的方法，还包括通过训练视觉摄像机识别所述掩模来将所述掩模对准到所述半导体封装。
18.一种制造半导体器件的方法，包括：
提供半导体封装；
在所述半导体封装之上设置掩模，所述掩模包括对称定位的一对基准标记，其中所述掩模包括由所述掩模的顶部、侧部、前部和背部界定的腔，并且其中所述半导体封装的一部分延伸到所述腔中；以及
在所述半导体封装和掩模之上形成屏蔽层。
19.根据权利要求18所述的方法，其中所述掩模包括二维条形码。
20.根据权利要求18所述的方法，还包括在带设置在所述掩模的第二表面上的情况下阳极化所述掩模的第一表面。
21.根据权利要求18所述的方法，还包括通过训练视觉摄像机识别所述掩模来将所述掩模对准到所述半导体封装。
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