CN114556594A

CN114556594A - Chip, preparation method, receiving chip, distance measuring device and movable platform

Info

Publication number: CN114556594A
Application number: CN202080014748.0A
Authority: CN
Inventors: 罗飞宇; 马亮亮; 郑国光; 黄潇; 洪小平
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2020-09-27
Filing date: 2020-09-27
Publication date: 2022-05-27
Also published as: WO2022061817A1

Abstract

A back-illuminated avalanche photodiode chip, a preparation method thereof, a receiving chip, a distance measuring device and a movable platform are provided. The preparation method comprises the following steps: providing a heavily doped substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface (S1); forming a back-illuminated avalanche photodiode array in the epitaxial layer (S2); forming a through-silicon-via that penetrates the epitaxial layer and is partially embedded in the substrate, the sidewall of the through-silicon-via being vertical (S3); forming a wiring layer on the through-silicon via (S4); the substrate is thinned to expose the through-silicon via at the second surface (S5). The back-illuminated avalanche photodiode chip is a high-integration and arrayed receiving chip, namely an area-arrayed APD chip, and has more stable performance and excellent reliability.

Description

Chip, preparation method, receiving chip, distance measuring device and movable platform

Description

Technical Field

The present application relates generally to the field of integrated circuits, and more particularly, to a back-illuminated avalanche photodiode chip, a method for manufacturing the same, a receiving chip, a distance measuring device, and a movable platform.

Background

The laser radar is a radar system that detects a characteristic amount such as a position and a velocity of a target by emitting a laser beam. The photosensitive sensor of the laser radar can convert the acquired optical pulse signal into an electric signal, and the time information corresponding to the electric signal is acquired based on the comparator, so that the distance information between the laser radar and the target object is obtained.

At present, mechanical rotary laser radars are mostly adopted in the technical scheme of the laser radars. It has the following disadvantages: reliability is low, in mechanical rotary lidar systems, a plurality of mechanical parts are introduced, in particular with movable parts. The production efficiency is low, the structure is complex, and each line needs to be respectively aligned, so that the difficulty of automatic assembly is caused. The cost is high, such as 64 line radars, which require 64 Laser diodes (Laser diodes) and 64 Avalanche Photodiodes (APDs), resulting in very high material cost. In addition, there is a high labor cost associated with complicated assembly.

At present, the chips used in the mechanical rotary laser mines for receiving the optical pulse sequence reflected by the detection object are mostly single-line APDs, or small-scale APD line arrays or APD surface arrays (generally within tens of channels, hardly exceeding hundreds of channels). The hardware scheme, mostly a test system composed of discrete APD devices and board-level hardware circuits, is not high in integration level, and once developed to a higher line number, is severely limited by technical difficulties and cost pressure, becomes a bottleneck difficult to solve, and is difficult to further evolve.

It is therefore desirable to provide a different chip for receiving a sequence of optical pulses reflected by a probe to overcome the above problems.

Disclosure of Invention

The application provides a method for preparing a back-illuminated avalanche photodiode chip, which comprises the following steps:

providing a heavily doped substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface;

forming a back-illuminated avalanche photodiode array in the epitaxial layer;

forming a through silicon via, wherein the through silicon via penetrates through the epitaxial layer and is partially embedded into the substrate, and the side wall of the through silicon via is vertical;

forming a wiring layer on the through silicon via;

and thinning the substrate to expose the through silicon via on the second surface.

A second aspect of the present application provides a back-illuminated avalanche photodiode chip, comprising:

a heavily doped substrate comprising a first surface and a second surface disposed opposite one another;

an epitaxial layer disposed on the first surface;

a back-illuminated avalanche photodiode array disposed in the epitaxial layer;

the silicon through hole penetrates through the epitaxial layer and the substrate, and the side wall of the silicon through hole is vertical;

and the wiring layer is arranged on the silicon through hole.

A third aspect of the present application provides a receiving chip, including:

the back-illuminated avalanche photodiode chip is used for receiving the optical pulse sequence reflected by the detected object and converting the received optical pulse sequence into a current signal;

and the signal processing chip is used for receiving and processing the current signal of the back-illuminated avalanche photodiode chip so as to output a time signal.

The present application fourth aspect provides a distance measuring device, the distance measuring device includes:

an optical transmission circuit for emitting a sequence of optical pulses;

the receiving chip is used for receiving the optical pulse sequence emitted by the light emitting circuit and reflected by the detected object, and outputting a time signal based on the received optical pulse sequence;

and the operation circuit is used for calculating the distance between the detected object and the laser radar according to the time signal.

A fifth aspect of the present application provides a movable platform, comprising:

a movable platform body;

the distance measuring device is arranged on the movable platform body.

The application provides a back-illuminated avalanche photodiode chip and a preparation method thereof, wherein a back-illuminated avalanche photodiode array is formed in the back-illuminated avalanche photodiode chip to form a highly sensitive area array APD chip, so that an echo signal of pulse laser which can cover a detection area is received, and the detection and the perception of distance information of the surrounding environment are completed through a mode similar to that of camera shooting. The back-illuminated avalanche photodiode chip is a high-integration and arrayed chip, namely an area-arrayed APD chip, and has more stable performance and excellent reliability.

In the application, through silicon vias are formed in the back-illuminated avalanche photodiode chip, the through silicon vias penetrate through the epitaxial layer and are partially embedded into the substrate so as to be used for leading out signals of the back-illuminated avalanche photodiode array, wherein the side walls of the through silicon vias are vertical, the filling effect is better when the through silicon vias are prepared, a wiring layer with better quality is easier to form above the through silicon vias with vertical side walls, the area of the chip is saved, the through silicon vias are more compatible with a subsequent deposition process, the subsequent process is not limited completely, the compatibility of the process is improved, and the yield of the back-illuminated avalanche photodiode chip is further improved.

Drawings

FIGS. 1A-1K illustrate schematic cross-sectional views of intermediate devices in the fabrication of a back-illuminated avalanche photodiode chip provided herein;

2A-2B illustrate cross-sectional schematic views of isolation structures in a back-illuminated avalanche photodiode chip as provided herein;

fig. 3 shows a schematic flow chart of a method for manufacturing a back-illuminated avalanche photodiode chip provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and that the present application is not limited by the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the application described in the application without inventive step, shall fall within the scope of protection of the application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present application.

It is to be understood that the present application is capable of implementation in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present application, detailed steps and detailed structures will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

In order to solve the foregoing problems, a first aspect of the present application provides a method for manufacturing a back-illuminated avalanche photodiode chip, as shown in fig. 3, where the method specifically includes the following steps:

step S1: providing a heavily doped substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface;

step S2: forming a back-illuminated avalanche photodiode array in the epitaxial layer;

step S3: forming a through silicon via, wherein the through silicon via penetrates through the epitaxial layer and is partially embedded into the substrate, and the side wall of the through silicon via is vertical;

step S4: forming a wiring layer on the through silicon via;

step S5: and thinning the substrate to expose the through silicon via on the second surface.

The fabrication method is described in detail with reference to fig. 1A to 1K, wherein fig. 1A to 1K show schematic cross-sectional views of intermediate devices in the fabrication process of the back-illuminated avalanche photodiode chip provided by the present application.

In the step S1, as shown in fig. 1A, a substrate 101 is provided, wherein the substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein the substrate 101 is a heavily doped substrate with a doping concentration in the range of 5 x 10¹⁸/cm ³-5×10 ²⁰/cm ³。

Alternatively, in an embodiment of the present application, the doping impurities may be implanted by an ion implanter. Specifically, the energy for ion implantation on the surface of the substrate 101 is 5Kev-50 Kev; for example, in one embodiment, the impurities are implanted at an energy of about 10 keV.

Further, after the ion implantation, the method also comprises a step of performing rapid annealing to eliminate defects formed by the ion implantation. In one embodiment of the present application, the temperature of the rapid annealing is 800 ℃ to 1600 ℃; the time of the rapid annealing is 10s-300 s.

In an embodiment of the present application, the substrate 101 is selected from silicon.

The substrate 101 includes a first surface and a second surface, which are oppositely disposed, where the first surface is a front surface and the second surface is a back surface.

An epitaxial layer 102 is formed on the first surface of the substrate 101, wherein the epitaxial layer 102 may be made of a semiconductor material, and in an embodiment of the present application, an epitaxial silicon wafer is used.

The epitaxial layer 102 has a thickness in the range of 20-40 μm to form an array of avalanche photodiodes in the epitaxial layer 102.

The epitaxial layer 102 includes a first surface and a second surface which are oppositely disposed, the second surface of the epitaxial layer is disposed on the substrate 101, and the first surface of the epitaxial layer is far away from the substrate 101. The first surface is a front surface, and the second surface is a back surface.

Optionally, the epitaxial layer 102 has a low doping type, which may be N-type or P-type, and usually the epitaxial layer 102 is P-type doped.

Wherein the doping concentration of the epitaxial layer is less than or equal to 1 × 10¹⁵/cm ³。

In the application, the epitaxial layer is set to be of a low doping type, so that the consumption of photon-generated carriers generated in the APD can be reduced, the photon-generated carriers can rapidly reach an avalanche collecting region of the APD, the corresponding speed of the APD is improved, the trailing problem of the APD is avoided, and the delay of a device is avoided.

In step S2, a back-illuminated avalanche photodiode array is formed on the first surface (front side of epitaxial layer) of the epitaxial layer 102. Wherein the back-illuminated avalanche photodiode array may comprise rows and/or columns of back-illuminated avalanche photodiodes.

Wherein the back-illuminated avalanche photodiode may comprise an arrangement of rows or columns to form a linear array of back-illuminated avalanche photodiodes. In addition, the back-illuminated avalanche photodiode can also include an arrangement of rows and columns to form an area array of back-illuminated avalanche photodiodes. The number of the back-illuminated avalanche photodiodes is not limited to a certain range of values and can be selected according to actual needs.

It should be noted that the array formed by the back-illuminated avalanche photodiode may be arranged in other forms besides the linear array and the planar array, and is not limited to the linear array and the planar array, and may also be arranged in an irregular manner, and the like, and may be set according to actual needs.

Forming a photoresist mask layer on the first surface of the epitaxial layer 102, performing photolithography to expose a region to be subjected to ion implantation, and performing an ion implantation process to sequentially form each functional region of the avalanche photodiode from bottom to top on the first surface of the epitaxial layer 102, wherein each functional region of the avalanche photodiode comprises a buffer layer, a diffusion barrier layer, an avalanche multiplication layer, an absorption layer and a contact layer.

Further, an electric field control layer and a graded layer may be further formed between the avalanche multiplication layer and the absorption layer.

In an embodiment of the application, the avalanche photodiode sequentially comprises a p-InP buffer layer, a p-AlInAs diffusion barrier layer, a low-doped n-InP avalanche multiplication layer, an n-InP electric field control layer, an n-InGaAsP gradual change layer, an nInGaAs light absorption layer, a semi-insulating InP window layer and an InGaAs contact layer from bottom to top.

The doping concentration and thickness of each functional layer of the avalanche photodiode can be conventional doping concentration and thickness, and are not listed here.

In step S3, as shown in fig. 1C, a through silicon via 103 is formed in the epitaxial layer and the semiconductor, and the through silicon via 103 penetrates through the epitaxial layer and is partially embedded in the substrate.

Wherein, the sidewall of the through silicon via 103 is vertical to realize the vertical connection between the two electrodes of the back-illuminated avalanche photodiode in the back-illuminated avalanche photodiode chip, wherein the through silicon via 103 leads out a high voltage signal.

The side wall of the through silicon via is vertical, the filling effect is better when the through silicon via is prepared, a wiring layer with better quality is easier to form above the through silicon via with the vertical side wall, the area of a chip is saved, the through silicon via is more compatible with a subsequent deposition process, the subsequent process is not limited completely, the compatibility of the process is improved, and the yield of the back-illuminated avalanche photodiode chip is further improved.

Optionally, the through-silicon via 103 is disposed in the epitaxial layer 102 and the edge region of the substrate 101, so as to facilitate isolation between the high-voltage pin of the through-silicon via 103 and each output pin of the back-illuminated avalanche photodiode, and the voltage of the output pin of the back-illuminated avalanche photodiode is low, so that a relatively large voltage difference is formed, so as to prevent the distance between the through-silicon via 103 and the back-illuminated avalanche photodiode from being too close, thereby avoiding coupling with each pin of the back-illuminated avalanche photodiode and reducing the risk of failure.

Wherein, 2 or more through silicon vias 103 are formed at the edges of the epitaxial layer 102 and the substrate 101 to prevent a large difference in high voltage between two sides of the back-illuminated avalanche photodiode chip.

In an embodiment of the present application, the through silicon vias 103 are symmetrically distributed around the epitaxial layer 102 and the substrate 101, for example, when the substrate 101 is circular, 2 through silicon vias 103 are formed at the edge of the substrate, and the through silicon vias 103 are oppositely disposed at the edge and located at two ends of the diameter in the substrate.

The forming method of the through silicon via 103 comprises the following steps:

step S31: as shown in fig. 1B, patterning the epitaxial layer 102 to form a through silicon via recess 10 in the epitaxial layer 102;

step S32: as shown in fig. 1C, the through-silicon via recess 10 is at least partially filled with a first conductive material to form the through-silicon via 103.

In step S31, a mask layer, such as a photoresist layer, is first formed on the epitaxial layer 102 and the substrate 101, and the mask layer is subjected to photolithography or etching to form a groove pattern in the mask layer.

Then, the epitaxial layer 102 and a part of the substrate 101 are etched by taking the mask layer as a mask, so that a pattern is transferred into the epitaxial layer 102 and a part of the substrate 101 to penetrate through the epitaxial layer 102 to the top of the substrate 101, and the through silicon via groove 10 is formed.

Wherein the depth of the through-silicon via groove 10 in the substrate 101 can be determined according to the final thickness of the substrate 101.

Wherein the sidewalls of the tsv recesses 10 are also vertical.

In the step S32, a first conductive material is formed in the through silicon via groove 10 to at least partially fill the through silicon via groove 10. The first conductive material may be tungsten, InGaAs (indium gallium arsenide), or a hollow copper tube.

The first conductive material may completely fill the through silicon via groove 10, and the first conductive material may be disposed on a sidewall of the through silicon via groove 10, for example, in an embodiment of the present application, tungsten or InGaAs (indium gallium arsenide) is selected to completely fill the through silicon via groove 10, or a hollow copper tube is inserted into the through silicon via groove 10, so as to form the through silicon via 103.

Further, the method still further comprises: isolation structures 112 are formed between adjacent back-illuminated avalanche photodiodes, as shown in fig. 2A, to avoid signal interference and/or bridging between adjacent back-illuminated avalanche photodiodes, which can cause device failure.

Optionally, the shape of the top view of the isolation structure 112 is circular or elliptical, which is not listed here.

The isolation structure 112 may be formed after the formation of the through silicon via 103, or the isolation structure may also be formed at the same time as the formation of the through silicon via 103.

In an embodiment of the present application, the method of forming the isolation structure 112 specifically includes:

patterning the epitaxial layer 102 to form an isolation groove;

the isolation recess is at least partially filled with a second conductive material to form the isolation structure 112.

The first conductive material and the second conductive material may be the same or different, and may be selected according to actual requirements.

Optionally, the second conductive material may be tungsten paste, a hollow copper tube, or polysilicon.

Wherein the isolation structure 112 is filled with the second conductive material for optical isolation between adjacent ones of the back-illuminated avalanche photodiodes.

In another embodiment of the present application, the forming of the isolation structure 112 simultaneously with the forming of the through silicon via 103 specifically includes:

patterning the epitaxial layer 102 to form the through silicon via groove 10, and simultaneously forming an isolation groove in the epitaxial layer;

the first conductive material is filled in the tsv grooves 10, and meanwhile, the first conductive material is filled in the isolation grooves to form the isolation structure 112. The isolation structure 112 is formed at the same time of forming the through silicon via 103, so that the preparation process is simpler and the manufacturing cost is reduced.

Optionally, as shown in fig. 2B, before the first conductive material or the second conductive material is filled in the tsv recess 10, the method further includes a step of forming an insulating layer 113 on the sidewall of the tsv recess to avoid interference of optical signals between adjacent back-illuminated avalanche photodiodes, so as to improve the performance of the device.

The insulating layer 113 may be made of an oxide material, such as silicon dioxide.

When the isolation structure 112 includes the insulating layer 113 and the second conductive material, the isolation structure is not only used for performing optical isolation between adjacent back-illuminated avalanche photodiodes, but also used for further achieving electrical isolation between adjacent back-illuminated avalanche photodiodes.

In step S4, as shown in fig. 1D, a wiring layer 104 is formed on the through silicon via 103 to form an electrical connection with the back-illuminated avalanche photodiode to extract a signal of the back-illuminated avalanche photodiode.

The method for forming the wiring layer 104 on the through silicon via 103 comprises the following steps:

step S41: a wiring material layer is formed on the epitaxial layer to completely cover the epitaxial layer 102 and the through-silicon via 103. The wiring material layer may be made of a metal material, such as metal Al, but is not limited to Al.

In a specific embodiment of the present application, the wiring material layer may be formed by a deposition method.

Step S42: after the wiring material layer is formed, the wiring material layer is patterned to form a plurality of connection structures spaced apart from each other, thereby forming a wiring layer 104 to electrically connect the through-silicon via 103 and the back-illuminated avalanche photodiode array, respectively.

After forming the wiring layers 104, the method may further include the step of forming a passivation layer 105 on the wiring layers 104 to cover the wiring layers 104 and fill the gaps between the wiring layers 104, as shown in fig. 1E.

After the passivation layer 105 is formed, a further etching step is further included to etch the passivation layer 105, so as to form a passivation layer opening in the passivation layer 105, exposing the wiring layer 104 for subsequent electrical connection, leading out signals of the back-illuminated avalanche photodiode.

In the step S5, when the substrate 101 is thinned, the substrate 101 may be protected to prevent damage to the substrate, which specifically includes the following steps:

step S51: as shown in fig. 1F, a carrier wafer 106 is provided, and the carrier wafer 106 is temporarily bonded to the first surface of the substrate 101. The carrier wafer 106 may be made of a semiconductor material commonly used in the art, and is not limited herein, as long as the carrier wafer can support and protect the substrate in the subsequent thinning process, so as to prevent the substrate from cracking or breaking;

in this step, the carrier wafer 106 and the substrate 101 are temporarily bonded, for example, by using an adhesive, without an excessively strong bond, so as to facilitate subsequent debonding.

Step S52: as shown in fig. 1G, the substrate 101 is thinned, and the thinned substrate 101 is used as an electrode of a back-illuminated avalanche photodiode.

Wherein, the thinning process may include one or a combination of chemical mechanical polishing, planarization processing and polishing. After thinning the substrate, the through-silicon-via 103 is exposed.

The thickness of the thinned substrate 101 is in a range from 0.1 μm to 5 μm, for example, in an embodiment of the present application, the thickness of the thinned substrate 101 is in a range from 3 μm to 5 μm, so as to ensure that light entering from the first surface of the substrate 101 is absorbed by an absorption layer in the back-illuminated avalanche photodiode.

The thickness of the substrate 101 is reduced to about 3-5 um, so that the minimum light absorbed by the substrate 101 can be ensured, and most of the light is absorbed by the absorption layer of the back-illuminated avalanche photodiode, so that the performance of the back-illuminated avalanche photodiode is improved.

Step S53: as shown in fig. 1H, after thinning the substrate 101, a support wafer 107 is provided, and the support wafer 107 is bonded to the second surface of the substrate 101.

When the substrate 101 is thinned, the substrate 101 is bonded with the transparent supporting wafer 107 through bonding (wafer bond) or resin (such as epoxy resin), so that the light transmittance is ensured, the strength of the whole chip is improved, the chip is prevented from being broken in the thinning process, and the yield is further improved.

In this step, the support wafer 107 may be a wafer of transparent material to enable light to enter the back-illuminated avalanche photodiode through the support wafer 107. In an embodiment of the present application, the support wafer 107 may be a glass wafer.

In this step, the support wafer 107 and the thinned substrate 101 may be bonded together by a resin adhesive 114.

Step S54: as shown in fig. 1I, after bonding the support wafer 107 to the substrate 101, the carrier wafer 106 is removed. In an embodiment of the present application, the carrier wafer 106 and the substrate 101 may be debonded by dropping a chemical reagent, so as to separate the carrier wafer 106 from the substrate 101.

After removing the carrier wafer 106, the method further includes step S6: connection bumps are formed on the wiring layer 104 to make electrical connection with other chips, for example, a processing chip, through the connection bumps.

Specifically, in an embodiment of the present application, a method of forming the connection bump includes:

step S61: as shown in fig. 1I, a buffer material layer 108 is formed on the passivation layer 105 and the wiring layer 104 exposed by the opening to cover the passivation layer 105 while filling the opening;

step S62: then patterning the buffer material layer 108 to form an opening and expose the passivation layer opening and the wiring layer 104 in the opening;

step S63: as shown in fig. 1J, the connection bump 110 is formed in the opening.

In the step S61, the buffer material layer 108 may be a Polyimide (Polyimide) material, and the buffer material layer 108 may be formed by spin coating. The buffer material layer 108 can play a role of buffering in the subsequent process of forming the connection bump, so as to prevent damage to the wiring layer 104 or the substrate.

In step S62, the patterning method is to form a mask layer on the buffer material layer 108, and then form an opening in the mask layer above the opening of the passivation layer 105 to expose the wiring layer 104.

In step S63, as shown in fig. 1I, an Under Bump Metal (UBM) layer 109 is deposited in the opening to cover the opening for forming the connection bump in the subsequent process.

The Under Bump Metal (UBM) 109 may include at least one of a copper (Cu) layer, a tin (Sn) layer, and a nickel (Ni) layer. In an embodiment of the present application, the Under Bump Metal (UBM) 109 is a copper (Cu) layer.

Wherein, the under bump metal layer 109 (UBM) with uniform thickness is deposited on the exposed wiring layer 104 in a common manner.

The connection bump 110 is then formed on the under bump metallurgy 109 in the opening, as shown in fig. 1J. The connection bump 110 includes a copper pillar, wherein a projection of the copper pillar on a horizontal plane may be a cylindrical structure such as a circle, a square, or a polygon.

A buffer material layer 108 is deposited between the connection bump 110 and the epitaxial layer 102, so as to buffer the stress on the connection bump 110 in a vibration or impact scene, thereby improving the reliability of interconnection between the connection bump 110 and the epitaxial layer 102.

After forming the connection bump 110, the method further includes: a pad layer 111 is formed on the upper surface of the connection bump 110, as shown in fig. 1K, for subsequent bonding between chips.

The distance between the connecting bump 110 located at the edge region of the substrate 101 and the adjacent connecting bump 110 is greater than the distance between the adjacent connecting bumps 110 located at the center region of the substrate 101, so as to prevent the high voltage difference between the two sides from being great.

The forming method of the solder joint layer 111 comprises the following steps:

a solder pad material layer is formed on the connection bump 110 to cover the connection bump 110, wherein the solder pad material layer is used for soldering in subsequent die bonding, and the solder pad material layer is a material that can be melted and soldered, such as, but not limited to, a tin (Sn) layer.

After the solder material layer is formed, a reflow step is performed to cover the connection bump 110 more uniformly.

The application provides a back-illuminated avalanche photodiode chip and a preparation method thereof, wherein a back-illuminated avalanche photodiode array is formed in the back-illuminated avalanche photodiode chip to form a highly sensitive area array APD chip, so that an echo signal of pulse laser which can cover a detection area is received, and the detection and the perception of distance information of the surrounding environment are completed through a mode similar to that of camera shooting. The back-illuminated avalanche photodiode chip is a high-integration and arrayed receiving chip, namely an area-arrayed APD chip, and has more stable performance and excellent reliability.

In the application, a through silicon via is formed in the back-illuminated avalanche photodiode chip, the through silicon via penetrates through the epitaxial layer and is partially embedded into the substrate so as to be used for leading out signals of the back-illuminated avalanche photodiode array, wherein the side wall of the through silicon via is vertical, the filling effect is better when the through silicon via is prepared, a wiring layer with better quality is easier to form above the through silicon via with the vertical side wall, the area of the chip is saved, the through silicon via is more compatible with a subsequent deposition process, the subsequent flow is not limited completely, the compatibility of the process is improved, and the yield of the back-illuminated avalanche photodiode chip is further improved.

A second aspect of the present application provides a back-illuminated avalanche photodiode chip, as shown in fig. 1K, comprising:

a heavily doped substrate 101, the substrate 101 comprising a first surface and a second surface disposed opposite to each other;

an epitaxial layer disposed on the first surface;

a back-illuminated avalanche photodiode array disposed in the epitaxial layer;

a through silicon via 103, wherein the through silicon via 103 penetrates through the epitaxial layer and the substrate 101, and the side wall of the through silicon via 103 is vertical;

and the wiring layer 104 is arranged on the through silicon via 103.

Wherein the substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein the thickness of the substrate 101 is in a range of 0.1 μm to 5 μm, for example, in an embodiment of the present application, the thickness of the substrate 101 is in a range of 3 μm to 5 μm, in order to ensure that light entering from the first surface of the substrate 101 is absorbed by an absorption layer in the back-illuminated avalanche photodiode.

The thickness of the substrate 101 is about 3-5 um, which can ensure that the light absorbed by the substrate 101 is minimum, and most of the light is absorbed by the absorption layer of the back-illuminated avalanche photodiode, so as to improve the performance of the back-illuminated avalanche photodiode.

The epitaxial layer 102 includes a first surface and a second surface that are oppositely disposed, the second surface of the epitaxial layer is disposed on the substrate 101, and the first surface of the epitaxial layer is far away from the substrate 101. The first surface is a front surface, and the second surface is a back surface.

Wherein the final doping concentration of the epitaxial layer 102 is less than or equal to 1 × 10¹⁵/cm ³。

In the present application, the epitaxial layer 102 is set to be of a low doping type, so that the consumption of photon-generated carriers generated in the APD can be reduced, the photon-generated carriers can rapidly reach an avalanche collecting region of the APD, the corresponding speed of the APD is increased, the problem of trailing of the APD is avoided, and the delay of a device is avoided.

A back-illuminated avalanche photodiode array, specifically an area array structure of avalanche photodiodes, is formed on the first surface (front surface of the epitaxial layer) of the epitaxial layer 102. Wherein the plurality of back-illuminated avalanche photodiode arrays may include an arrangement of rows and columns. The number of the back-illuminated avalanche photodiode arrays is not limited to a certain range of values, and can be selected according to actual needs.

Each functional region of the avalanche photodiode comprises a buffer layer, a diffusion barrier layer, an avalanche multiplication layer, an absorption layer and a contact layer. Further, an electric field control layer and a graded layer may be further formed between the avalanche multiplication layer and the absorption layer.

Wherein the through silicon via 103 penetrates the epitaxial layer 102 and is partially embedded in the substrate 101. The side wall of the through silicon via 103 is vertical to realize vertical connection between two electrodes of the back-illuminated avalanche photodiode in the back-illuminated avalanche photodiode chip, wherein the through silicon via 103 leads out a high voltage signal.

Optionally, the through-silicon via 103 is disposed in the epitaxial layer 102 and the edge region of the substrate 101, so as to isolate a high voltage pin of the through-silicon via 103 from output pins of the back-illuminated avalanche photodiode, and a voltage of the output pins of the back-illuminated avalanche photodiode is low, so that a relatively large voltage difference is formed, so as to prevent the through-silicon via 103 from being too close to the back-illuminated avalanche photodiode, and avoid coupling with the pins of the back-illuminated avalanche photodiode, which may cause a failure risk.

In an embodiment of the present application, the through silicon vias 103 are symmetrically distributed around the epitaxial layer 102 and the substrate 101, for example, when the substrate 101 is circular, 2 through silicon vias 103 are formed at the edge of the substrate, and the through silicon vias 103 are oppositely disposed at the edge and located at two ends of the substrate middle diameter respectively.

The through silicon via 103 comprises a through silicon via recess 10 and a first conductive material at least partially filling the through silicon via recess 10. Wherein the depth of the through-silicon via groove 10 in the substrate 101 can be determined according to the final thickness of the substrate 101. The sidewalls of the through-silicon-via recess 10 are also vertical.

The first conductive material may be tungsten, InGaAs (indium gallium arsenide), or a hollow copper tube. The first conductive material may completely fill the through silicon via groove, and the first conductive material may be disposed on a sidewall of the through silicon via groove, for example, in an embodiment of the present application, tungsten or InGaAs (indium gallium arsenide) is selected to completely fill the through silicon via groove, or a hollow copper tube is inserted into the through silicon via groove, so as to form the through silicon via 103.

The back-illuminated avalanche photodiode chip further includes: isolation structures 112 are provided between adjacent back-illuminated avalanche photodiodes to prevent signal interference and/or bridging between adjacent back-illuminated avalanche photodiodes, which can result in device failure.

Wherein the isolation structure 112 may be formed after the formation of the through silicon via 103, or the isolation structure may also be formed at the same time as the formation of the through silicon via 103.

The isolation structure comprises an isolation groove; and a second conductive material at least partially filling the isolation recess.

In another embodiment of the present application, the isolation structure further includes an insulating layer 113 on a surface of the isolation groove, and the conductive material is formed on the insulating layer. The insulating layer 113 may be made of an oxide material, such as silicon dioxide.

A wiring layer 104 is also formed on the through silicon via 103 to form an electrical connection with the back-illuminated avalanche photodiode to extract a signal of the back-illuminated avalanche photodiode.

The wiring layer 104 may be made of a metal material, such as metal Al, but is not limited to Al.

A passivation layer 105 is also formed on the wiring layer 104, and a passivation layer opening is formed in the passivation layer 105 to expose the wiring layer 104 for subsequent electrical connection to extract signals of the back-illuminated avalanche photodiode.

The back-illuminated avalanche photodiode chip further includes a support wafer 107, the support wafer 107 being bonded to the second surface of the substrate 101. The support wafer 107 may be a wafer of transparent material to enable light to enter the back-illuminated avalanche photodiode through the support wafer 107. In one embodiment of the present application, the support wafer 107 may be a glass wafer.

The back-illuminated avalanche photodiode chip comprises a thinned substrate 101 in the preparation process, and when the substrate 101 is thinned, the substrate is bonded with a transparent supporting wafer 107 through bonding (wafer bond) or resin (such as epoxy resin), so that the light transmittance is ensured, the strength of the whole chip is improved, the chip is prevented from being broken in the thinning process, and the yield is further improved.

The back-illuminated avalanche photodiode chip further includes a connection bump 110 formed on the wiring layer 104 to be electrically connected with other chips, for example, a process chip, through the connection bump 110.

Optionally, the back-illuminated avalanche photodiode chip further includes a buffer material layer 108 on the passivation layer 105 and the wiring layer 104 exposed by the opening to cover the passivation layer 105 while filling the opening.

Wherein the buffer material layer 108 has an opening and exposes the passivation layer opening and the wiring layer 104 in the opening, and the connection bump 110 is formed in the opening.

The buffer material layer 108 may be a Polyimide (Polyimide) material, and the buffer material layer 108 may be formed by a spin coating method. The buffer material layer 108 may serve as a buffer in a subsequent process of forming the connection bump 110, so as to prevent damage to the wiring layer 104 or the substrate 101.

An Under Bump Metal (UBM) layer 109 is also formed in the opening to cover the opening, and the connection bump 110 is formed on the Under Bump Metal (UBM) layer 109.

The connection bump 110 includes a copper pillar, wherein a projection of the copper pillar on a horizontal plane may be a cylindrical structure of a circle, a square, a polygon, or the like.

A solder pad layer is further formed on the upper surface of the connection bump 110 for subsequent bonding between chips.

The solder joint layer is a material that can be fused and soldered, such as but not limited to a tin (Sn) layer, and the solder joint layer uniformly covers the connection bump 110.

The third aspect of the present application further provides a receiving chip, wherein the receiving chip includes:

the back-illuminated avalanche photodiode chip is configured to receive the optical pulse sequence reflected by the detected object, and convert the received optical pulse sequence into a current signal;

In an embodiment of the present application, the avalanche photodiode chip includes a plurality of back-illuminated avalanche photodiodes and a plurality of first connection bumps electrically connected to the back-illuminated avalanche photodiodes;

the signal processing chip comprises a plurality of signal processing units and a plurality of second connecting bumps, and the second connecting bumps are electrically connected with the signal processing units;

the avalanche photodiodes corresponding to each other up and down are connected with the signal processing unit through the first connecting bumps and the second connecting bumps.

The avalanche photodiode and the signal processing unit are connected with each other through the first connecting bump and the second connecting bump, the connection mode is more beneficial to miniaturization of the connection of the first connecting bump and the second connecting bump, for example, the diameter of the first connecting bump and the second connecting bump can be 50 micrometers and the pitch of the second connecting bump can be 100 micrometers, and the problems that the solder balls are seriously melted and flowed when being connected with the connecting pad at present, the pitch is difficult to be reduced (the minimum is 200 micrometers) and the problem that the solder balls are easily broken when being reduced can be avoided.

The method for mutually connecting the first connecting bump and the second connecting bump in the application has higher reliability, the height of the first connecting bump and the height of the second connecting bump can be more than 100 mu m, the tensile strength is increased, and the reliability can be effectively improved.

Wherein the first connection bump comprises a first copper pillar;

the second connection bump includes a second copper pillar.

And a welding point layer is formed on the first connecting bump and/or the second connecting bump.

The receiving chip further comprises a transfer plate which is arranged between the avalanche photodiode chip and the signal processing chip and is respectively and electrically connected with the avalanche photodiode chip and the signal processing chip.

Specifically, the interposer comprises a through silicon via interconnection structure penetrating through the upper and lower surfaces of the interposer and a conductive layer located on the upper and lower surfaces of the interposer and electrically connected with the through silicon via interconnection structure;

the first connecting bump and the second connecting bump are electrically connected with the conductive layers on the upper surface and the lower surface of the adapter plate respectively.

Wherein the sidewalls of the through silicon via interconnect structure are vertical.

Wherein the signal processing chip includes:

a trans-group amplifier for converting the current signal into a voltage signal;

a comparator for comparing the voltage signal with a preset voltage threshold;

and the time-to-digital converter is used for outputting a time signal according to the comparison result of the comparator.

In an embodiment of the present application, the signal processing unit is integrated with a plurality of circuits, and in an embodiment of the present application, for example, the signal processing unit is integrated with a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPA, a comparator, and a time-to-digital converter circuit (circuit that converts time into a digital signal) or an analog-to-digital conversion circuit (ADC circuit), and a subsequent data processing circuit (DSP circuit). The TIA circuit is an analog front-stage circuit for converting APD photocurrent into voltage.

When the back-illuminated avalanche photodiodes convert optical signals into current signals, external high-voltage power supply is needed, and the APD can provide stable internal gain, improve the signal-to-noise ratio and output the current signals.

In the signal processing unit, the TIA circuit is electrically connected with the back-illuminated avalanche photodiode, converts a current signal of the APD into a voltage signal and provides conversion gain; and the multi-stage operational amplifier OPA is electrically connected with the TIA circuit and used for amplifying the signal output by the TIA circuit so as to meet the comparison amplitude requirement of the comparator. The comparator is electrically connected with the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, the analog signal is converted into a digital signal, the digital signal is transmitted to the TDC circuit, and the TDC circuit is used for converting the digital signal into a time signal and calculating the distance. For the plurality of signal processing units, one TDC circuit may be shared, that is, the number of signal processing units and the number of TDC circuits may not correspond to each other.

The signal processing unit can be further provided with a storage system for caching data, providing an input/output cache space for an interface and providing a space for internal calculation.

An interface can be further arranged in the signal processing unit to be used as a data input and output channel for outputting the measurement data.

In an embodiment of the present application, a first input terminal of the comparator is configured to receive an electrical signal input from the trans-group amplifier, that is, an electrical signal after an amplification operation, a second input terminal of the comparator is configured to receive a preset threshold, and an output terminal of the comparator is configured to output a result of the comparison operation, where the result of the comparison operation includes time information corresponding to the electrical signal. It will be appreciated that the preset threshold received at the second input of the comparator may be an electrical signal having a strength of the preset threshold. The result of the comparison operation may be a digital signal corresponding to the amplified electrical signal.

Optionally, the Time-to-Digital Converter (TDC) is electrically connected to an output end of the comparator, and is configured to extract Time information corresponding to the electrical signal according to a comparison operation result output by the comparator.

The fourth aspect of the present application further provides a distance measuring device, where the back-illuminated avalanche photodiode chip or the receiving chip provided in the embodiments of the present invention may be applied to a distance measuring device, and the distance measuring device may be an electronic device such as a laser radar and a laser distance measuring device. In one embodiment, the ranging device is used to sense external environmental information, such as distance information, orientation information, reflected intensity information, velocity information, etc. of environmental targets. In one implementation, the ranging device may detect the distance of the probe to the ranging device by measuring the Time of Flight (TOF), which is the Time-of-Flight Time, of light traveling between the ranging device and the probe. Alternatively, the distance measuring device may detect the distance from the probe to the distance measuring device by other techniques, such as a distance measuring method based on phase shift (phase shift) measurement or a distance measuring method based on frequency shift (frequency shift) measurement, which is not limited herein.

The distance measuring device adopts the back-illuminated avalanche photodiode chip, is a solid laser radar, can directly emit pulse laser covering a detection area in a short time, receives echo signals by a highly sensitive area array APD chip, and completes detection and perception of distance information of the surrounding environment through a mode similar to camera shooting. Compared with a mechanical scanning type laser radar, the solid-state laser radar has the advantages of smaller size, lower cost, more stable performance, excellent reliability and easier passing through a gauge.

For ease of understanding, the following describes the operation flow of ranging by the ranging apparatus as an example.

The ranging apparatus may include a transmitting circuit, a receiving chip, and an operation circuit 440.

The transmit circuit may transmit a sequence of light pulses (e.g., a sequence of laser pulses). The receiving chip can receive the optical pulse sequence emitted by the optical transmitting circuit and reflected by the detected object, and output a time signal based on the received optical pulse sequence. The arithmetic circuitry may determine a distance between the ranging device and the detected object based on the time signal.

Optionally, the distance measuring apparatus may further include a control circuit, and the control circuit may implement control of other circuits, for example, may control an operating time of each circuit and/or perform parameter setting on each circuit, and the like.

The distance and the orientation detected by the distance measuring device can be used for remote sensing, obstacle avoidance, mapping, modeling, navigation and the like, for example, sensing of the surrounding environment is realized, and two-dimensional or three-dimensional mapping is carried out on the external environment. In one embodiment, the distance measuring device of the present application may be applied to the movable platform.

Based on this, the fifth aspect of the present application also provides a movable platform, wherein the distance measuring device described above can be applied to the movable platform, and the distance measuring device can be installed on the movable platform body of the movable platform.

In certain embodiments, the movable platform comprises at least one of an unmanned aerial vehicle, an automobile, a remote control car, a robot, a camera. When the distance measuring device is applied to the unmanned aerial vehicle, the movable platform body is a fuselage of the unmanned aerial vehicle. When the distance measuring device is applied to an automobile, the movable platform body is the automobile body of the automobile. The vehicle may be an autonomous vehicle or a semi-autonomous vehicle, without limitation. When the distance measuring device is applied to the remote control car, the movable platform body is the car body of the remote control car. When the distance measuring device is applied to a robot, the movable platform body is the robot. When the distance measuring device is applied to a camera, the movable platform body is a camera body.

The movable platform can further comprise a power system for driving the movable platform body to move. For example, when the movable platform is a vehicle, the power system may be an engine inside the vehicle, which is not listed here.

Although the example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above-described example embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the present application, various features of the present application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present application should not be construed to reflect the intent: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some of the modules according to embodiments of the present application. The present application may also be embodied as apparatus programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the specific embodiments of the present application or the description thereof, and the protection scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope disclosed in the present application, and shall be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A preparation method of a back-illuminated avalanche photodiode chip is characterized by comprising the following steps:

providing a heavily doped substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface;

forming a back-illuminated avalanche photodiode array in the epitaxial layer;

forming a through silicon via, wherein the through silicon via penetrates through the epitaxial layer and is partially embedded into the substrate, and the side wall of the through silicon via is vertical;

forming a wiring layer on the through silicon via;

and thinning the substrate to expose the through silicon via on the second surface.
The method of manufacturing according to claim 1, further comprising:

forming a connection bump on the wiring layer.
The method for manufacturing according to claim 2, wherein a distance between the connection bump located at the edge region of the substrate and an adjacent connection bump is greater than a distance between the connection bumps located adjacent to the center region of the substrate.
The production method according to claim 1, wherein 2 or more through-silicon-vias are formed at edges of the epitaxial layer and the substrate.
The method of claim 1, wherein the method of forming the through silicon via comprises:

patterning the epitaxial layer and a part of the substrate to form a through silicon via groove in the epitaxial layer and the substrate;

at least partially filling the through-silicon-via recess with a first conductive material to form the through-silicon-via.
The method of manufacturing according to claim 1, further comprising:

an isolation structure is formed between adjacent back-illuminated avalanche photodiodes.
The method of claim 6, wherein the isolation structure is formed at the same time as the through-silicon-via is formed.
The method of manufacturing according to claim 6, further comprising:

patterning the epitaxial layer to form an isolation groove;

at least partially filling the isolation recess with a second conductive material to form the isolation structure.
The method for manufacturing according to claim 8, wherein before the step of filling the conductive material in the isolation groove, the method further comprises:

and forming an insulating layer on the surface of the isolation groove.
The method of manufacturing according to claim 1, wherein the forming a wiring layer on the through-silicon via includes:

forming a wiring material layer on the epitaxial layer to cover the epitaxial layer and the through silicon via;

patterning the wiring material layer to form wiring layers to electrically connect the through silicon vias and the back-illuminated avalanche photodiode array, respectively.
The manufacturing method according to claim 10, wherein after the wiring layer is formed, the method further comprises:

a passivation layer having an opening is formed on the wiring layer to expose a portion of the wiring layer.
The method of manufacturing according to claim 1, further comprising:

providing a bearing wafer, and temporarily bonding the bearing wafer and the first surface of the substrate;

thinning the substrate;

providing a support wafer, and bonding the support wafer and the second surface of the substrate;

and removing the bearing wafer.
The method of claim 12, wherein the substrate is thinned to 3um to 5 um.
The method of claim 13, wherein the support wafer comprises a glass wafer.
The manufacturing method according to claim 1, wherein forming a connection bump on the wiring layer includes:

forming a buffer material layer on the wiring layer to cover the wiring layer;

patterning the buffer material layer to form a buffer layer with an opening and expose part of the wiring layer;

forming the connection bump in the opening.
The method of manufacturing according to claim 15, further comprising:

forming an under bump metal layer in the opening to cover the opening;

and forming the connecting bump on the under bump metal layer.
The method of claim 15, wherein the connection bump comprises a copper pillar.
The method of manufacturing according to claim 1, further comprising:

and forming a welding spot layer on the connecting bump.
The method of manufacturing of claim 18, wherein forming the solder joint layer comprises:

forming a solder joint material layer on the connecting bump to cover the connecting bump;

and performing a reflow step to form the solder joint layer.
A back-illuminated avalanche photodiode chip, comprising:

a heavily doped substrate comprising a first surface and a second surface disposed opposite one another;

an epitaxial layer disposed on the first surface;

a back-illuminated avalanche photodiode array disposed in the epitaxial layer;

the silicon through hole penetrates through the epitaxial layer and the substrate, and the side wall of the silicon through hole is vertical;

and the wiring layer is arranged on the silicon through hole.
The back-illuminated avalanche photodiode chip of claim 20, further comprising:

and the connecting bump is arranged on the wiring layer.
The back-illuminated avalanche photodiode chip as claimed in claim 21, wherein the distance between the connection bump located at the edge region of the substrate and an adjacent connection bump is greater than the distance between the adjacent connection bumps located at the central region of the substrate.
The back-illuminated avalanche photodiode chip of claim 20, wherein the back-illuminated avalanche photodiode array includes a plurality of back-illuminated avalanche photodiodes with isolation structures formed between adjacent ones of the back-illuminated avalanche photodiodes.
The back-illuminated avalanche photodiode chip of claim 23, wherein the isolation structure comprises an isolation recess and an electrically conductive material in the isolation recess.
The back-illuminated avalanche photodiode chip of claim 24 wherein the isolation structure further includes an insulating layer on a surface of the isolation recess, the electrically conductive material being formed on the insulating layer.
The back-illuminated avalanche photodiode chip of claim 20 wherein the wiring layer is formed with a passivation layer having an opening therein, the opening exposing a portion of the wiring layer.
The back-illuminated avalanche photodiode chip of claim 20 wherein a support wafer is bonded to the second surface, the support wafer being bonded to the second surface.
The back-illuminated avalanche photodiode chip of claim 27 wherein the support wafer comprises a glass wafer.
The back-illuminated avalanche photodiode chip according to claim 21, wherein a buffer layer having an opening is formed on the wiring layer, the opening exposing a part of the wiring layer;

the connection bump is formed on the wiring layer exposed from the opening.
The back-illuminated avalanche photodiode chip according to claim 29, wherein an under bump metallization layer is further provided between the wiring layer and the connection bump.
The back-illuminated avalanche photodiode chip according to claim 21, wherein the connection bump comprises a copper pillar.
The back-illuminated avalanche photodiode chip of claim 21 wherein a solder joint layer is formed on the connection bump.
A receiving chip, comprising:

the back-illuminated avalanche photodiode chip as claimed in one of the claims 20 to 32, for receiving the optical pulse train reflected by the inspected object and converting the received optical pulse train into a current signal;

and the signal processing chip is used for receiving and processing the current signal of the back-illuminated avalanche photodiode chip so as to output a time signal.
A ranging apparatus, comprising:

an optical transmission circuit for emitting a sequence of optical pulses;

the receiving chip of claim 33, for receiving the optical pulse train emitted by the optical transmitting circuit and reflected by the detected object, and outputting a time signal based on the received optical pulse train;

and the operation circuit is used for calculating the distance between the detected object and the laser radar according to the time signal.
A movable platform, comprising:

a movable platform body;

a ranging apparatus as claimed in claim 34 wherein the ranging apparatus is provided on the moveable platform body.
The movable platform of claim 35, wherein the movable platform comprises a drone, an autonomous automobile, or a robot.