CN104637870A - TSV (through silicon via) back side hole leaking technology without CMP (chemical mechanical grinding) technology - Google Patents
TSV (through silicon via) back side hole leaking technology without CMP (chemical mechanical grinding) technology Download PDFInfo
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- CN104637870A CN104637870A CN201510090226.XA CN201510090226A CN104637870A CN 104637870 A CN104637870 A CN 104637870A CN 201510090226 A CN201510090226 A CN 201510090226A CN 104637870 A CN104637870 A CN 104637870A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The invention provides a TSV (through silicon via) back side hole leaking technology without CMP (chemical mechanical grinding) technology. The TSV back side hole leaking technology comprises the following steps of S1, providing a device wafer which completes a front side technology, wherein the device wafer comprises a substrate and a TSV (through silicon via) blind hole, and the TVS blind hole is formed in the substrate; S2, providing a carrier wafer, and bonding the front side of the device wafer and the carrier wafer by a temporary bonding technology, so as to obtain a temporary bonding body; S3, mechanically grinding the back side of the substrate of the device wafer, and thinning; S4, etching the back side of the substrate, and enabling the TSV blind hole to expose out of the back side of the substrate; S5, coating a back side medium layer at the back side of the substrate of the device wafer, and completely covering the exposing part of the TSV blind hole in the step S4; S6, utilizing a mechanical grinding technology to process the back side medium layer, and enabling the TSV blind hole to expose out of the back side medium layer. The TSV back side hole leaking technology has the advantages that the CMP process in the TSV back side end exposing process is avoided, the technological cost is greatly reduced, the output efficiency is obviously improved, and the self-aligning effect of the back side medium layer hole via is realized.
Description
Technical field
The present invention relates to wafer level packaging technique, especially a kind of silicon through hole back side small opening process program of alternative CMP.
Background technology
Along with people are to the development of the requirement of electronic product to directions such as miniaturized, multi-functional, environment-friendly types, people make great efforts to seek electronic system to do less and less, integrated level is more and more higher, function is done more and more, more and more by force, is paid close attention to widely because 2.5D encapsulation and 3D encapsulation have high packaging density.
In 2.5D encapsulation, interim bonding techniques is utilized to realize the bonding of slide glass wafer and device wafers.Interim bonding has following advantage: first, and slide glass wafer is the supportive protection that thin device wafers provides mechanically, so just can carry out back process by the equipment of normal component wafer fabrication.For ultra thin device wafer, the PROCESS FOR TREATMENT of device wafers level can be realized.Therefore, by interim bonding techniques, utilize every platform equipment of device wafers factory can both process thin device wafers, and without the need to conversion unit again, and do not need special termination effector, fixture or device wafers box.
In prior art device wafers back process, for back side RDL(wiring layer again) prepare, the technique such as thinning, wet etching/dry etching, passivating back, back side CMP need be carried out, mention in Chinese patent CN103943557 A, utilize CMP to realize RDL surface aggregate thing passivation layer flatening process.But CMP has complex process, the problem such as the high and production capacity of cost is lower.
CMP refers to CMP (Chemical Mechanical Polishing) process.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of silicon through hole back side small opening technique exempting from CMP is provided, in 2.5D encapsulation, by the reasonable combination of rational technique Integrated design by interim bonding, the grinding of back side silicon, the coating of back side silicon etching, back side dielectric layer, back side dielectric layer grinding technics, realize the self-registered technology of back side TSV small opening and back side dielectric layer via hole when not adopting CMP.The technical solution used in the present invention is:
Exempt from a silicon through hole back side small opening technique for CMP, comprise the steps:
S1., the device wafers that completes front technique is provided; Device wafers comprises the TSV blind hole in substrate and substrate;
S2., one slide glass wafer is provided, utilizes interim bonding technology that bonding is carried out in device wafers front and slide glass wafer, form ephemeral key fit;
S3. mechanical lapping is carried out to the substrate back of device wafers, thus carry out thinning;
S4. substrate back is etched, make TSV blind hole expose substrate back;
S5. at the substrate back coated back surface dielectric layer of device wafers, TSV blind hole exposed portion in step S4 is covered completely;
S6. utilize mechanical milling tech process back side dielectric layer, TSV blind hole is exposed from the dielectric layer of the back side.
Further, in step S2, the thickness evenness of the slide glass wafer provided is less than 5 μm.
Further, in step 3, after substrate back grinding, the thickness evenness of ephemeral key zoarium is less than 8 μm.
Further, in step S4, etching technics is wet-etching technology or dry etch process.
Further, in step S4, TSV blind hole exposes the height h<5 μm of substrate back.
The invention has the advantages that: the silicon through hole back side small opening process program of exempting from CMP that the present invention proposes, the CMP of appearing in process at the silicon through hole back side is avoided by Optimization Technology Integrated Solution, process costs is significantly reduced, and output efficiency is significantly improved.
Technique integrated optimization is utilized to improve the fit thickness evenness of ephemeral key, it is made to reach the requirement of backgrinding process treatment media layer, utilize backgrinding process to process back side dielectric layer, thus reach the autoregistration effect of back side TSV small opening and back side dielectric layer via hole.
Accompanying drawing explanation
Fig. 1 is the device wafers schematic diagram completing front technique of the present invention.
Fig. 2 is device wafers front of the present invention and the interim bonding schematic diagram of slide glass wafer.
Fig. 3 is that device wafers substrate back of the present invention carries out mechanical lapping schematic diagram.
Fig. 4 is device wafers substrate back of the present invention etching schematic diagram.
Fig. 5 is substrate back coated back surface dielectric layer schematic diagram of the present invention.
Fig. 6 is dielectric layer mechanical lapping schematic diagram in the back side of the present invention.
Fig. 7 is flow chart of the present invention.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
The silicon through hole back side small opening process program of exempting from CMP that the present embodiment proposes, comprises the steps:
S1., the device wafers 100 that completes front technique is provided; As shown in Figure 1, device wafers 100 completes the making of Facad structure according to existing common process; Device wafers 100 comprises the TSV blind hole 2 in substrate 1, substrate 1, the insulating barrier on TSV blind hole 2 hole wall and Seed Layer (this two-layer indicate with mark 3), front RDL layer 4, front dielectric layer 6 and the connecting salient points 6 etc. being connected front RDL layer; Conducting metal is filled with, such as copper in TSV blind hole 2.
Substrate 1 is silicon substrate.TSV hole and silicon through hole, in step sl, due to also dew hole, the unrealized back side, TSV hole, be therefore referred to as TSV blind hole.RDL i.e. wire structures again.
S2. as shown in Figure 2, provide a slide glass wafer 200, utilize interim bonding technology that bonding is carried out in device wafers 100 front and slide glass wafer 200, form ephemeral key fit;
In this step, the material of slide glass wafer 200 can be silicon or glass, and the thickness evenness of slide glass wafer 200 is less than 5 μm; Interim bonding technology can be the interim bonding technology of Zonebond, heat tears interim bonding technology open, laser tears the interim bonding technology of bonding etc. open.
S3. as shown in Figure 3, mechanical lapping is carried out to substrate 1 back side of device wafers 100, thus carries out thinning;
This step is carried out thinning to substrate 1 back side, but TSV blind hole 2 is not exposed from substrate 1 back side.After substrate 1 grinding back surface, the thickness evenness of ephemeral key zoarium is less than 8 μm.
S4. as shown in Figure 4, use wet-etching technology or dry etch process to etch substrate 1 back side, make TSV blind hole 2 expose substrate 1 back side, the height h<5 μm exposed;
S5. as shown in Figure 5, at the substrate 1 backside coating back side dielectric layer 7 of device wafers 100, TSV blind hole 2 exposed portion in step S4 is covered completely;
The material of back side dielectric layer 7 can adopt the organic material such as polyimides, PBO, also can adopt the material such as silicon nitride, silicon oxynitride, needs back side dielectric layer 7 thickness to be 3 ~ 30 μm according to technique.
S6. as shown in Figure 6, utilize mechanical milling tech process back side dielectric layer 7, TSV blind hole 2 is exposed from back side dielectric layer 7, thus become silicon through hole (TSV hole).
Existing technique will make back side dielectric layer open, and needs to utilize photoetching process to realize the graphical of back side dielectric layer, and the hole pattern for making via hole needs to aim at TSV blind hole, makes the last dielectric layer via hole formed aim at TSV blind hole completely.And in this step S6, utilize mechanical milling tech process back side dielectric layer 7, while silicon through hole exposes from the dielectric layer of the back side, achieve the autoregistration of back side dielectric layer via hole.
Claims (5)
1. exempt from a silicon through hole back side small opening technique for CMP, it is characterized in that, comprise the steps:
S1., the device wafers (100) that completes front technique is provided; Device wafers (100) comprises the TSV blind hole (2) in substrate (1) and substrate (1);
S2., one slide glass wafer (200) is provided, utilizes interim bonding technology that bonding is carried out in device wafers (100) front and slide glass wafer (200), form ephemeral key fit;
S3. mechanical lapping is carried out to substrate (1) back side of device wafers (100), thus carry out thinning;
S4. substrate (1) back side is etched, make TSV blind hole (2) expose substrate (1) back side;
S5. at substrate (1) backside coating back side dielectric layer (7) of device wafers (100), TSV blind hole (2) exposed portion in step S4 is covered completely;
S6. utilize mechanical milling tech process back side dielectric layer (7), TSV blind hole (2) is exposed from back side dielectric layer (7).
2. exempt from the silicon through hole back side small opening technique of CMP as claimed in claim 1, it is characterized in that:
In step S2, the thickness evenness of the slide glass wafer (200) provided is less than 5 μm.
3. exempt from the silicon through hole back side small opening technique of CMP as claimed in claim 1, it is characterized in that:
In step 3, after substrate (1) grinding back surface, the thickness evenness of ephemeral key zoarium is less than 8 μm.
4. exempt from the silicon through hole back side small opening technique of CMP as claimed in claim 1, it is characterized in that:
In step S4, etching technics is wet-etching technology or dry etch process.
5. exempt from the silicon through hole back side small opening technique of CMP as claimed in claim 1, it is characterized in that:
In step S4, TSV blind hole (2) exposes the height h<5 μm at substrate (1) back side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510090226.XA CN104637870A (en) | 2015-02-27 | 2015-02-27 | TSV (through silicon via) back side hole leaking technology without CMP (chemical mechanical grinding) technology |
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| CN201510090226.XA CN104637870A (en) | 2015-02-27 | 2015-02-27 | TSV (through silicon via) back side hole leaking technology without CMP (chemical mechanical grinding) technology |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858536A (en) * | 2018-08-24 | 2020-03-03 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN111554647A (en) * | 2020-05-19 | 2020-08-18 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| CN113161306A (en) * | 2021-04-15 | 2021-07-23 | 浙江集迈科微电子有限公司 | High-efficiency heat dissipation structure of chip and preparation process thereof |
| WO2022061817A1 (en) * | 2020-09-27 | 2022-03-31 | 深圳市大疆创新科技有限公司 | Chip and manufacturing method therefor, receiving chip, ranging device, and movable platform |
Citations (4)
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| US20080203526A1 (en) * | 2007-02-26 | 2008-08-28 | Casio Computer Co., Ltd. | Semiconductor device equipped with thin-film circuit elements |
| CN102349140A (en) * | 2009-03-12 | 2012-02-08 | 美光科技公司 | Method for fabricating semiconductor components using maskless back side alignment to conductive vias |
| CN102468229A (en) * | 2010-11-15 | 2012-05-23 | 南亚科技股份有限公司 | Integrated circuit structure and method of forming the same |
| CN103390580A (en) * | 2013-08-20 | 2013-11-13 | 华进半导体封装先导技术研发中心有限公司 | Back exposing method of TSV (through silicon via) |
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2015
- 2015-02-27 CN CN201510090226.XA patent/CN104637870A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080203526A1 (en) * | 2007-02-26 | 2008-08-28 | Casio Computer Co., Ltd. | Semiconductor device equipped with thin-film circuit elements |
| CN102349140A (en) * | 2009-03-12 | 2012-02-08 | 美光科技公司 | Method for fabricating semiconductor components using maskless back side alignment to conductive vias |
| CN102468229A (en) * | 2010-11-15 | 2012-05-23 | 南亚科技股份有限公司 | Integrated circuit structure and method of forming the same |
| CN103390580A (en) * | 2013-08-20 | 2013-11-13 | 华进半导体封装先导技术研发中心有限公司 | Back exposing method of TSV (through silicon via) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858536A (en) * | 2018-08-24 | 2020-03-03 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN111554647A (en) * | 2020-05-19 | 2020-08-18 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| CN111554647B (en) * | 2020-05-19 | 2022-04-19 | 上海先方半导体有限公司 | Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method |
| WO2022061817A1 (en) * | 2020-09-27 | 2022-03-31 | 深圳市大疆创新科技有限公司 | Chip and manufacturing method therefor, receiving chip, ranging device, and movable platform |
| CN113161306A (en) * | 2021-04-15 | 2021-07-23 | 浙江集迈科微电子有限公司 | High-efficiency heat dissipation structure of chip and preparation process thereof |
| CN113161306B (en) * | 2021-04-15 | 2024-02-13 | 浙江集迈科微电子有限公司 | Efficient heat dissipation structure of chip and preparation process thereof |
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Application publication date: 20150520 |