CN114546090A - Adaptive voltage frequency adjustment method and device - Google Patents
Adaptive voltage frequency adjustment method and device Download PDFInfo
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Abstract
The invention provides a self-adaptive voltage frequency adjusting method and a device, wherein the method comprises the following steps: obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance; judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule; and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment. The invention drives the counter to count through the clock signal acquired in advance and the delay information of each monitoring path acquired in advance, judges whether the frequency needs to be adjusted and judges whether the voltage needs to be adjusted according to the obtained counting result and the preset voltage frequency adjustment rule, so as to carry out corresponding adjustment according to the judgment result, avoid the delay caused by one-to-one detection of each monitoring path, thereby effectively improving the response speed, simplifying the process of voltage frequency adjustment control and ensuring that the energy consumption is reduced as much as possible under the condition that the chip normally operates.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a self-adaptive voltage frequency adjusting method and a self-adaptive voltage frequency adjusting device.
Background
With the development of Dynamic Voltage Frequency Scaling (DVFS) technology, DVFS is widely applied to various processors nowadays, so as to effectively manage power consumption of an electronic system to avoid waste.
The current voltage and frequency regulation scheme mainly detects the frequency regulation requirement sent by each path in a chip or an external interrupt through a detection unit, retrieves a new frequency and a new voltage through a pre-built voltage-frequency upper limit relation, and then respectively configures the new frequency and the new voltage to a voltage regulation unit and a clock regulation unit.
However, since the voltage and frequency adjustment scheme needs to detect each path in the chip one by one, the detection workload is large, and the response speed is slow, which easily causes the situation of large performance loss or large power loss; in addition, because the DVFS policy requires that the frequency be reduced first and then the voltage be reduced when optimizing the power consumption, and requires that the voltage be increased first and then the frequency be increased when optimizing the performance, so as to safely realize the optimal performance power consumption optimization, a complex time sequence control is required to ensure safety, and the response speed is limited by the frequency stabilization speed of the clock module and the output stabilization speed of the power module, the response is slow, and the control complexity is high.
Disclosure of Invention
The invention provides a self-adaptive voltage frequency adjusting method and a self-adaptive voltage frequency adjusting device, which are used for solving the defect of slow response speed caused by one-to-one detection of each path in the prior art, simplifying the voltage frequency adjusting control process and improving the response speed.
The invention provides a self-adaptive voltage frequency adjusting method, which comprises the following steps: obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance; judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule; and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment.
According to the adaptive voltage frequency adjustment method provided by the invention, the obtaining of the counting result based on the clock signal acquired in advance and the delay information of each monitoring path acquired in advance comprises the following steps: performing AND gate logic operation on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance to obtain a first operation result; carrying out frequency conversion processing on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance, and carrying out AND gate logic operation on the delay subjected to frequency conversion processing to obtain a second operation result; and performing logical operation of an exclusive OR gate on the first operation result and the second operation result to obtain a logical operation result, and driving a counter to count according to the logical operation result to obtain a counting result.
According to the adaptive voltage frequency adjusting method provided by the invention, the step of judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and the preset voltage frequency adjusting rule comprises the following steps: determining standard voltage and standard frequency corresponding to each monitoring path by utilizing a preset voltage frequency regulation rule based on the counting result; acquiring monitoring voltage and monitoring frequency of a corresponding monitoring path based on the counting result; comparing the monitoring voltage with the standard voltage, and judging whether to adjust the voltage; and comparing the monitoring frequency with the standard frequency to judge whether to adjust the frequency.
According to the invention, the method for adjusting the frequency of the adaptive voltage, which is provided by the invention, comprises the following steps: comparing the monitoring voltage obtained in advance based on the counting result with a preset voltage, and correspondingly increasing the voltage step based on the monitoring voltage being smaller than the preset voltage; otherwise, reducing the voltage step;
the adjusting the frequency comprises: comparing the monitoring frequency obtained in advance based on the counting result with a preset frequency, and correspondingly increasing the frequency stepping based on that the monitoring frequency is smaller than the preset frequency; otherwise, the frequency step is decreased.
According to the adaptive voltage frequency adjusting method provided by the invention, before obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance, the method comprises the following steps: and acquiring clock signals corresponding to each monitoring path.
According to the adaptive voltage frequency adjustment method provided by the invention, the acquiring of the clock signal corresponding to each monitoring path comprises the following steps: the acquisition register generates clock signals corresponding to each monitoring path based on input signals; and returning the clock signal output by the register based on the inverter, and carrying out AND gate logic operation by combining with a pre-acquired trigger signal to obtain an input signal of the register.
According to the adaptive voltage frequency adjustment method provided by the invention, before the obtaining of the input signal of the register, the method further comprises the following steps: obtaining a trigger signal based on a preset adaptive voltage frequency adjustment parameter, wherein the adaptive voltage frequency adjustment parameter comprises at least one of a starting signal, a system clock signal, configuration time and reset times.
According to the adaptive voltage frequency adjustment method provided by the present invention, before obtaining a counting result based on the clock signal obtained in advance and the delay information of each monitoring path obtained in advance, the method further includes: acquiring delay information of each monitoring path in a delay packet based on the clock information; or monitoring each monitoring path based on the clock information, and storing the delay information obtained by monitoring to a delay packet.
The present invention also provides a device for adjusting a frequency of a self-adaptive voltage, comprising: the value detection module is used for obtaining a counting result corresponding to each monitoring path based on a clock signal obtained in advance and monitoring information obtained by monitoring each monitoring path in advance; the system control module judges whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule; and the adjusting module correspondingly adjusts the voltage and/or the frequency according to the judgment result obtained by the judgment.
The present invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the adaptive voltage frequency adjustment method as described in any of the above when executing the program.
The self-adaptive voltage frequency adjusting method and the self-adaptive voltage frequency adjusting device drive the counter to count through the clock signal acquired in advance and the delay information of each monitoring path acquired in advance, judge whether the frequency needs to be adjusted and judge whether the voltage needs to be adjusted according to the obtained counting result and the preset voltage frequency adjusting rule, so that the corresponding adjustment is carried out according to the judging result, the delay caused by one-to-one detection of each monitoring path is avoided, the response speed is effectively improved, the voltage frequency adjusting control process is simplified, and the energy consumption is ensured to be reduced as far as possible under the condition that a chip normally operates.
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In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic flow chart of an adaptive voltage frequency adjustment method provided by the present invention;
FIG. 2 is a circuit diagram illustrating an adaptive voltage frequency adjustment method according to the present invention;
FIG. 3 is a second schematic circuit diagram of the adaptive voltage frequency adjustment method according to the present invention;
FIG. 4 is a schematic structural diagram of an adaptive voltage frequency adjustment apparatus provided in the present invention;
fig. 5 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a schematic flow chart of an adaptive voltage frequency adjustment method according to the present invention, which includes:
s11, obtaining a counting result based on the clock signal and the delay information of each monitoring path;
s12, judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and the preset voltage frequency adjustment rule;
and S13, adjusting the voltage and/or frequency according to the judgment result obtained by the judgment.
It should be noted that S1N in this specification does not represent the sequence of the adaptive voltage frequency adjustment method, and the adaptive voltage frequency adjustment method of the present invention is described below with reference to fig. 2 to 3.
In step S11, a count result is obtained based on the clock signal acquired in advance and the delay information of each monitoring path acquired in advance.
In this embodiment, obtaining a count result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance includes: performing AND gate logic operation on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance to obtain a first operation result; carrying out frequency conversion processing on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance, and carrying out AND gate logic operation on the delay subjected to frequency conversion processing to obtain a second operation result; and performing logical operation of an exclusive OR gate on the first operation result and the second operation result to obtain a logical operation result, and driving a counter to count according to the logical operation result to obtain a counting result.
It should be noted that, when obtaining the first operation result, the and gate logic operation needs to be performed on the delay information of all the monitoring paths acquired in advance to obtain the first operation result; and when the second operation result is obtained, performing frequency conversion processing on the delay information of all the monitoring paths acquired in advance, and performing and gate logic operation on the delay information after the frequency conversion processing to obtain the second operation result.
In addition, the logic operation result is obtained by performing exclusive OR gate logic operation on the second operation result obtained by frequency conversion and the first operation result not subjected to frequency conversion, and the exclusive OR gate logic operation is performed on the operation results obtained by frequency conversion and not subjected to frequency conversion, so that a monitoring path with the largest time delay is obtained from each monitoring path, and the subsequent frequency and/or voltage judgment of the monitoring path is facilitated.
In this embodiment, the first operation result is obtained by performing and gate logic operation on the delay information corresponding to all the obtained monitoring paths, if the delay information corresponding to all the obtained monitoring paths is 1, the obtained first operation result is 1, otherwise, the obtained first operation result is 0; similarly, the second operation result is that all the delay information after frequency conversion is subjected to and gate logic operation, if the delay information corresponding to all the obtained monitoring paths is 1, the obtained second operation result is 1, otherwise, the obtained second operation result is 0.
And the logical operation result is that the first operation result and the second operation result are subjected to exclusive OR gate logical operation, if the first operation result and the second operation result are different, the obtained logical operation result is 0, and otherwise, the obtained logical operation result is 1.
It should be added that the critical path may be a path with a delay greater than a preset threshold among chip paths selected in advance based on a priori or experience, and the specific selection of the critical path may be set according to actual design requirements, which is not further limited herein.
In an alternative embodiment, before obtaining the counting result based on the pre-acquired clock signal and the pre-acquired delay information of each monitoring path, the method includes: and acquiring clock signals corresponding to each monitoring path. It should be noted that the clock signal in the present embodiment may be derived from a register or other circuits, such as a clock signal of a system, and is not further limited herein, and the clock signal is derived from a register in the following examples, specifically:
acquiring clock signals corresponding to each monitoring path, including: the acquisition register generates clock signals corresponding to each monitoring path based on the input signals; and returning the clock signal output by the register based on the inverter, and carrying out AND gate logic operation by combining with the pre-acquired trigger signal to obtain the input signal of the register.
In an optional embodiment, before obtaining the count result based on the pre-acquired clock signal and the pre-acquired delay information of each monitoring path, the method further includes: acquiring delay information of each monitoring path in the delay packet based on the clock information; or monitoring each monitoring path based on the clock information, and storing the delay information obtained by monitoring to the delay packet.
Specifically, referring to fig. 2, the register generates a clock signal based on the input signal and sends the clock signal to the delay packet, so as to associate the clock signal with the obtained delay information of each monitoring path in the following; when the register sends the clock signal to the delay packet, the inverter returns the clock signal transmitted to the delay packet by the register to the AND gate logic circuit, meanwhile, the AND gate logic circuit also receives the trigger signal sent by the control logic circuit, the AND gate logic circuit carries out AND gate logic operation based on the trigger signal and the returned clock signal to obtain an input signal of the register and inputs the input signal to the register so as to trigger the register, and the register generates the clock signal based on the input signal.
In an alternative embodiment, referring to fig. 3, before obtaining the input signal of the register, that is, before the and logic circuit receives the trigger signal sent by the control logic circuit, the method further includes: the control logic circuit obtains a trigger signal based on an input Adaptive Voltage Frequency Scaling (AVFS) parameter. It should be noted that, in this embodiment, the adaptive voltage frequency adjustment parameter includes at least one of an AVFS start signal, a system clock signal, an AVFS configuration time, and an AVFS reset time, and a specific parameter configuration may be set according to an actual design requirement, which is not further limited herein.
Step S12, determining whether to adjust the voltage and whether to adjust the frequency according to the counting result and the preset voltage and frequency adjustment rule.
Specifically, the method for judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and the preset voltage and frequency adjustment rule includes: based on the counting result, determining standard voltage and standard frequency corresponding to each monitoring path by using a preset voltage frequency regulation rule; acquiring monitoring voltage and monitoring frequency of a corresponding monitoring path based on the counting result; comparing the monitored voltage with the standard voltage, and judging whether to adjust the voltage; and comparing the monitoring frequency with the standard frequency, and judging whether to adjust the frequency.
It should be noted that, comparing the monitored voltage with the standard voltage includes: if the monitored voltage meets the standard voltage, the voltage is not adjusted, otherwise, the voltage is adjusted; likewise, comparing the monitored frequency to the standard frequency includes: based on the monitored frequency meeting the standard frequency, the frequency is not adjusted, otherwise, the frequency is adjusted.
In addition, the voltage frequency adjustment rule includes a count value and a standard voltage and a standard frequency corresponding to the count value, for example, the voltage frequency adjustment rule refers to the following table:
| count value counts value | Voltage of standard voltage | Standard frequency |
| 1000 | 0.85v | 1GHZ |
| 900 | 0.82v | 900MHZ |
| 850 | 0.8v | 800MHZ |
| 1100 | 0.89v | 1100MHZ |
| 1150 | 0.92v | 1150MHZ |
Based on the counting result, the standard voltage and the standard frequency corresponding to each monitoring path are determined by utilizing a preset voltage frequency regulation rule, and the method comprises the following steps: based on the counting result, searching a counting value which accords with the counting result in the voltage and frequency adjustment rule; and determining the standard frequency and the standard voltage corresponding to the count value obtained by searching.
It should be noted that the count value, the standard frequency and the standard voltage in the voltage frequency adjustment rule may be set according to actual design or use requirements, and are only exemplary references herein, and the voltage frequency adjustment rule is not further limited.
In step S13, the voltage and/or frequency is adjusted according to the judgment result obtained by the judgment.
In this embodiment, adjusting the voltage includes: comparing the monitoring voltage obtained in advance based on the counting result with a preset voltage, and correspondingly increasing the voltage step based on the monitoring voltage being smaller than the preset voltage; otherwise, the voltage step is reduced. It should be noted that the preset voltage may be preset based on experience, a priori condition, actual design requirement or use requirement, and is not further limited herein.
Additionally, adjusting the frequency includes: comparing the monitoring frequency obtained in advance based on the counting result with a preset frequency, and correspondingly increasing the frequency stepping based on the monitoring frequency being smaller than the preset frequency; otherwise, the frequency step is reduced. Likewise, the preset frequency may be set in advance based on experience, a priori condition, actual design requirement or use requirement, and is not further limited herein.
In an alternative embodiment, an adaptive voltage frequency adjustment method includes:
acquiring a clock signal generated by a register, wherein the clock signal returns to the register for storage based on an inverter;
acquiring delay information of each monitoring path based on clock information;
obtaining a counting result based on the clock signal and the delay information;
and judging the adjustment voltage and/or the adjustment frequency according to the counting result and a preset voltage frequency adjustment rule to obtain a judgment result, and correspondingly adjusting the voltage and/or the frequency according to the judgment result.
In summary, the embodiment of the present invention drives the counter to count through the clock signal obtained in advance and the delay information of each monitoring path obtained in advance, and determines whether the frequency needs to be adjusted and whether the voltage needs to be adjusted according to the obtained count result and the preset voltage frequency adjustment rule, so as to perform corresponding adjustment according to the determination result, thereby avoiding the delay caused by detecting each monitoring path one by one, effectively improving the response speed, simplifying the voltage frequency adjustment control process, and ensuring that the energy consumption is reduced as much as possible under the condition that the chip normally operates.
The following describes the adaptive voltage frequency adjusting apparatus provided by the present invention, and the adaptive voltage frequency adjusting apparatus described below and the adaptive voltage frequency adjusting method described above may be referred to in correspondence with each other.
Fig. 4 is a schematic diagram of an adaptive voltage frequency adjustment apparatus, which includes:
the value detection module 41 obtains a counting result corresponding to each monitoring path based on a clock signal obtained in advance and monitoring information obtained by monitoring each monitoring path in advance;
the system control module 42 judges whether to adjust the voltage and whether to adjust the frequency according to the monitoring information, the counting result and a preset voltage frequency adjustment rule;
and the adjusting module 43 correspondingly adjusts the voltage and/or the frequency according to the judgment result obtained by the judgment.
In this embodiment, the value detection module 41 includes: the first AND gate logic calculation unit is used for carrying out AND gate logic operation on the delay information of each monitoring path acquired in advance based on the clock signal acquired in advance to obtain a first operation result; the second AND gate logic calculation unit is used for carrying out frequency conversion processing on the delay information of each monitoring path acquired in advance based on the clock signal acquired in advance and carrying out AND gate logic operation on the delay subjected to frequency conversion processing to obtain a second operation result; and the exclusive OR gate logic calculation unit is used for carrying out exclusive OR gate logic operation on the first operation result and the second operation result to obtain a logic operation result, and driving the counter to count according to the logic operation result to obtain a counting result.
It should be noted that the first operation result is obtained by performing and gate logic operation on the delay information corresponding to all the obtained monitoring paths, if the delay information corresponding to all the obtained monitoring paths is 1, the obtained first operation result is 1, otherwise, the obtained first operation result is 0; similarly, the second operation result is that all the delay information after frequency conversion is subjected to and gate logic operation, if the delay information corresponding to all the obtained monitoring paths is 1, the obtained second operation result is 1, otherwise, the obtained second operation result is 0.
In addition, the logical operation result is that the first operation result and the second operation result are subjected to the logical operation of an exclusive or gate, if the first operation result and the second operation result are different, the obtained logical operation result is 0, otherwise, the obtained logical operation result is 1.
It should be added that the critical path may be a path with a delay greater than a preset threshold among chip paths selected in advance based on a priori or experience, and the specific selection of the critical path may be set according to actual design requirements, which is not further limited herein.
In an optional embodiment, the apparatus further comprises: and the clock acquisition module acquires clock signals corresponding to each monitoring path. It should be noted that the clock obtaining module in this embodiment may be a register or other circuit, that is, a clock signal may be derived from the register or other circuit, such as a clock signal of a system, and the like, which is not further limited herein, and the following is exemplified by the clock signal being derived from the register, and specifically, the clock obtaining module includes: the signal acquisition unit is used for acquiring clock signals which are generated by the register and correspond to each monitoring path based on the input signals; and the signal storage unit returns the clock signal output by the register based on the inverter and performs AND gate logic operation by combining with the pre-acquired trigger signal to obtain an input signal of the register.
In an optional embodiment, the apparatus further comprises: and the delay information acquisition module is used for acquiring the delay information of each monitoring path. Specifically, the delay information obtaining module includes: the delay information acquisition unit is used for acquiring the delay information of each monitoring path in the delay packet based on the clock information; or, the delay information obtaining module includes: and the monitoring unit monitors each monitoring path based on the clock information and stores the delay information obtained by monitoring to the delay packet.
In an optional embodiment, the apparatus further comprises: the trigger signal obtaining module obtains a trigger signal based on an input Adaptive Voltage Frequency Scaling (AVFS) parameter. It should be noted that the trigger signal obtaining module may adopt a control logic circuit, the adaptive voltage frequency adjustment parameter includes at least one of an AVFS start signal, a system clock signal, an AVFS configuration time, and an AVFS reset time, and a specific parameter configuration may be set according to an actual design requirement, which is not further limited herein.
A system control module 42, comprising: the standard determining unit is used for determining standard voltage and standard frequency corresponding to each monitoring path by utilizing a preset voltage frequency adjusting rule based on the counting result; the voltage frequency acquisition unit is used for acquiring the monitoring voltage and the monitoring frequency of the corresponding monitoring path based on the counting result; the first comparison unit is used for comparing the monitored voltage with the standard voltage and judging whether to adjust the voltage or not; and the second comparison unit is used for comparing the monitoring frequency with the standard frequency and judging whether to adjust the frequency.
Wherein, the standard determining unit includes: the searching subunit searches a count value which accords with the counting result in the voltage and frequency adjustment rule based on the counting result; and according to the found counting value, the standard acquisition subunit determines the standard frequency and the standard voltage corresponding to the standard acquisition subunit.
A first comparison unit comprising: the first comparison subunit does not adjust the voltage based on the monitoring voltage meeting the standard voltage, and otherwise, adjusts the voltage; likewise, the second comparison unit includes: and the second comparison subunit does not adjust the frequency based on the monitoring frequency meeting the standard frequency, and otherwise, adjusts the frequency.
It should be noted that the count value, the standard frequency and the standard voltage in the voltage frequency adjustment rule may be set according to actual design or use requirements, and are only exemplary references herein, and the voltage frequency adjustment rule is not further limited.
An adjustment module 43, comprising: the voltage adjusting unit correspondingly adjusts the voltage according to the judgment result; and the frequency adjusting unit correspondingly adjusts the frequency according to the judgment result.
Specifically, the voltage adjustment unit includes: the first adjusting subunit compares the monitoring voltage obtained in advance based on the counting result with a preset voltage, and correspondingly increases the voltage step based on the monitoring voltage being smaller than the preset voltage; otherwise, the voltage step is reduced.
In addition, the frequency adjustment unit includes: the second adjusting subunit compares the monitoring frequency obtained in advance based on the counting result with the preset frequency, and correspondingly increases the frequency stepping based on that the monitoring frequency is smaller than the preset frequency; otherwise, the frequency step is reduced.
It should be noted that the detection voltage and the monitoring frequency are obtained by a voltage frequency obtaining unit based on the system control module 42 in advance.
In an alternative embodiment, the adaptive voltage frequency adjustment apparatus comprises:
the clock acquisition module generates a clock signal and sends the clock signal to the value detection module, and returns the clock signal to the register for storage based on the phase inverter;
the delay information acquisition module is used for acquiring delay information of each monitoring path based on clock information;
the value detection module is used for obtaining a counting result based on the clock signal and the delay information;
the system control module judges the adjusting voltage and/or the adjusting frequency according to the counting result and a preset voltage frequency adjusting rule to obtain a judging result;
and the adjusting module correspondingly adjusts the voltage and/or the frequency according to the judgment result.
In summary, the embodiment of the present invention drives the counter to count through the clock signal obtained in advance and the delay information of each monitoring path obtained in advance, and determines whether the frequency needs to be adjusted and whether the voltage needs to be adjusted according to the obtained count result and the preset voltage frequency adjustment rule, so as to perform corresponding adjustment according to the determination result, thereby avoiding the delay caused by detecting each monitoring path one by one, effectively improving the response speed, simplifying the voltage frequency adjustment control process, and ensuring that the energy consumption is reduced as much as possible under the condition that the chip normally operates.
Fig. 5 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 5: a processor (processor)51, a communication Interface (communication Interface)52, a memory (memory)53 and a communication bus 54, wherein the processor 51, the communication Interface 52 and the memory 53 complete communication with each other through the communication bus 54. The processor 51 may invoke logic instructions in the memory 53 to perform an adaptive voltage frequency adjustment method comprising: obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance; judging whether to adjust the voltage and whether to adjust the frequency according to the monitoring information, the counting result and a preset voltage frequency adjustment rule; and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment.
In addition, the logic instructions in the memory 53 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product comprising a computer program, the computer program being storable on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, a computer is capable of executing the adaptive voltage frequency adjustment method provided by the above methods, the method comprising: obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance; judging whether to adjust the voltage and whether to adjust the frequency according to the monitoring information, the counting result and a preset voltage frequency adjustment rule; and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements an adaptive voltage frequency adjustment method provided by the above methods, the method comprising: obtaining a counting result based on a clock signal obtained in advance and delay information of each monitoring path obtained in advance; judging whether to adjust the voltage and whether to adjust the frequency according to the monitoring information, the counting result and a preset voltage frequency adjustment rule; and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An adaptive voltage frequency adjustment method, comprising:
obtaining a counting result based on a clock signal acquired in advance and delay information of each monitoring path acquired in advance;
judging whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule;
and correspondingly adjusting the voltage and/or the frequency according to the judgment result obtained by the judgment.
2. The adaptive voltage frequency adjustment method according to claim 1, wherein the obtaining a count result based on a pre-acquired clock signal and pre-acquired delay information of each monitoring path comprises:
performing AND gate logic operation on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance to obtain a first operation result;
carrying out frequency conversion processing on the delay information of each monitoring path acquired in advance based on a clock signal acquired in advance, and carrying out AND gate logic operation on the delay subjected to frequency conversion processing to obtain a second operation result;
and performing logical operation of an exclusive OR gate on the first operation result and the second operation result to obtain a logical operation result, and driving a counter to count according to the logical operation result to obtain a counting result.
3. The adaptive voltage frequency adjustment method according to claim 1, wherein the determining whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule comprises:
determining standard voltage and standard frequency corresponding to each monitoring path by utilizing a preset voltage frequency regulation rule based on the counting result;
acquiring monitoring voltage and monitoring frequency of a corresponding monitoring path based on the counting result;
comparing the monitoring voltage with the standard voltage, and judging whether to adjust the voltage;
and comparing the monitoring frequency with the standard frequency, and judging whether to adjust the frequency.
4. The adaptive voltage frequency adjustment method of claim 1, wherein adjusting the voltage comprises:
comparing the monitoring voltage obtained in advance based on the counting result with a preset voltage, and correspondingly increasing the voltage step based on the monitoring voltage being smaller than the preset voltage; otherwise, reducing the voltage step;
the adjusting the frequency comprises:
comparing the monitoring frequency obtained in advance based on the counting result with a preset frequency, and correspondingly increasing the frequency stepping based on that the monitoring frequency is smaller than the preset frequency; otherwise, the frequency step is decreased.
5. The adaptive voltage frequency adjustment method according to claim 1, wherein before obtaining the count result based on the pre-acquired clock signal and the pre-acquired delay information of each monitoring path, the method comprises:
and acquiring clock signals corresponding to each monitoring path.
6. The adaptive voltage frequency adjustment method of claim 5, wherein said obtaining a clock signal for each of the monitor paths comprises:
the acquisition register generates clock signals corresponding to each monitoring path based on input signals;
and returning the clock signal output by the register based on the inverter, and carrying out AND gate logic operation by combining with a pre-acquired trigger signal to obtain an input signal of the register.
7. The adaptive voltage frequency adjustment method according to claim 6, further comprising, before said deriving the input signal to the register:
obtaining a trigger signal based on a preset adaptive voltage frequency adjustment parameter, wherein the adaptive voltage frequency adjustment parameter comprises at least one of a starting signal, a system clock signal, configuration time and reset times.
8. The adaptive voltage frequency adjustment method according to claim 1, further comprising, before obtaining the count result based on the pre-acquired clock signal and the pre-acquired delay information of each monitoring path:
acquiring delay information of each monitoring path in a delay packet based on the clock information; alternatively, the first and second electrodes may be,
and monitoring each monitoring path based on the clock information, and storing the delay information obtained by monitoring to a delay packet.
9. An adaptive voltage frequency adjustment apparatus, comprising:
the value detection module is used for obtaining a counting result corresponding to each monitoring path based on a clock signal obtained in advance and monitoring information obtained by monitoring each monitoring path in advance;
the system control module judges whether to adjust the voltage and whether to adjust the frequency according to the counting result and a preset voltage frequency adjustment rule;
and the adjusting module correspondingly adjusts the voltage and/or the frequency according to the judgment result obtained by the judgment.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the adaptive voltage frequency adjustment method according to any of claims 1 to 8 are implemented when the processor executes the program.
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