CN112667024A

CN112667024A - Time delay calculation circuit, chip operation frequency acquisition method and device and electronic equipment

Info

Publication number: CN112667024A
Application number: CN202011623520.XA
Authority: CN
Inventors: 刘勋; 魏洁; 陈佰儒
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-04-16
Anticipated expiration: 2040-12-31
Also published as: CN112667024B

Abstract

The application relates to a time delay calculation circuit, a method and a device for acquiring chip operating frequency and electronic equipment. The delay calculation circuit comprises a selection control module, a traveling wave counter and a plurality of oscillation signal generation modules, wherein the oscillation signal generation modules are used for being connected with a plurality of target critical paths in a one-to-one correspondence mode. And each oscillation signal generation module is used for generating an oscillation signal under the time delay action of the corresponding target critical path. The selection control module is used for respectively selecting the oscillation signals generated by each oscillation signal generation module in the plurality of oscillation signal generation modules and sending the oscillation signals to the traveling wave counter. The traveling wave counter is used for counting each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generation module in the plurality of oscillation signal generation modules within a target counting time length. The delay calculating circuit can reduce the difficulty of obtaining the whole operation frequency of the target chip.

Description

Time delay calculation circuit, chip operation frequency acquisition method and device and electronic equipment

Technical Field

The application relates to the technical field of chip manufacturing, in particular to a delay calculation circuit, a method and a device for acquiring chip operating frequency and electronic equipment.

Background

In the design and manufacturing process of the chip, the whole operating frequency of the chip is often required to be obtained, after the whole operating frequency of the chip is obtained, if the whole operating frequency of the chip is lower than the target operating frequency, the whole frequency of the chip is improved in a mode of increasing the working voltage, and if the whole operating frequency of the chip is higher than the target operating frequency, the purpose of saving power consumption is achieved in a mode of reducing the working voltage, so that the normal operation of the chip is ensured.

In the prior art, each path in a chip is usually copied accurately, and then the path delay of each copied path is calculated, so that the overall operating frequency of the chip is obtained according to the path delay of each path. In the process, each path in the chip needs to be accurately copied, so that the design difficulty of the delay calculation circuit is high, and the difficulty and the efficiency of obtaining the whole operation frequency of the chip are increased.

Disclosure of Invention

An object of the present application is to provide a delay calculating circuit, a method and an apparatus for obtaining a chip operating frequency, and an electronic device, so as to solve the above problems.

In a first aspect, the delay calculating circuit provided by the present application includes a selection control module, a traveling wave counter, and a plurality of oscillation signal generating modules, where the plurality of oscillation signal generating modules are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, and the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip;

each oscillation signal generation module is used for generating an oscillation signal under the time delay effect of a corresponding target critical path;

the selection control module is used for respectively selecting the oscillation signals generated by each oscillation signal generation module in the plurality of oscillation signal generation modules and sending the oscillation signals to the traveling wave counter;

the traveling wave counter is used for counting each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generation module in a target counting time length, and the signal count value is used for representing the path delay of a target critical path corresponding to the oscillation signal generation module.

With reference to the first aspect, an embodiment of the present application further provides a first optional implementation manner of the first aspect, where in the plurality of oscillation signal generation modules, each oscillation signal generation module includes a first selector, an inverter, and a first controller;

a first input end of the first selector is used for accessing an initial signal value, an output end of the first selector is used as a first external port of the oscillation signal generation module, and the first external port is used for accessing an input end of a target critical path corresponding to the oscillation signal generation module;

the input end of the phase inverter is used as the output end of the oscillation signal generation module and a second external port, the second external port is used for accessing the output end of the target critical path corresponding to the oscillation signal generation module, and the output end of the phase inverter is connected with the second input end of the first selector;

the first controller is connected with the control input end of the first selector.

With reference to the first optional implementation manner of the first aspect, an embodiment of the present application further provides a second optional implementation manner of the first aspect, and the oscillation signal generating module further includes a first flip-flop;

the clock control end of the first trigger is connected with the system clock, the input end of the first trigger is connected with the starting indication signal, and the output end of the first trigger is connected with the first input end of the first selector and used for outputting an initial signal value.

With reference to the first aspect, an embodiment of the present application further provides a third optional implementation manner of the first aspect, where the selection control module includes a second selector and a second controller;

the second selector comprises a plurality of input ends, the input ends of the second selector are correspondingly connected with the output ends of the oscillation signal generating modules one by one, and the output end of the second selector is used as the output end of the selection control module;

the second controller is connected with the control input end of the second selector.

In combination with the first aspect, an embodiment of the present application further provides a fourth optional implementation manner of the first aspect, where the ripple counter includes a count controller and a plurality of second flip-flops, the plurality of second flip-flops are connected in sequence, and in the plurality of second flip-flops, a clock control end of a first-stage flip-flop is connected to an output end of the selection control module through the count controller, and in the plurality of second flip-flops, an output end of a last-stage flip-flop is used as a high-order output end of the ripple counter.

With reference to the fourth optional implementation manner of the first aspect, this embodiment of the present application further provides a fifth optional implementation manner of the first aspect, for any two adjacent second flip-flops in the plurality of second flip-flops, an output terminal of a second flip-flop in a front position is connected to a clock control terminal of a second flip-flop in a back position, and for each second flip-flop in the plurality of second flip-flops, an inverted output terminal of the second flip-flop is connected to an input terminal of the second flip-flop.

With reference to the fourth optional implementation manner of the first aspect, an embodiment of the present application further provides a sixth optional implementation manner of the first aspect, where the counting controller includes a counter and an and gate;

the input end of the counter is connected with a system clock, and the output end of the counter is connected with the first input end of the AND gate;

and the second input end of the AND gate is used as the input end of the traveling wave counter and connected with the output end of the selection control module, and the output end of the AND gate is connected with the clock control end of the first-stage trigger.

In a second aspect, an embodiment of the present application further provides a method for obtaining a chip operating frequency, including:

the method comprises the steps of obtaining a plurality of signal count values obtained through a delay calculation circuit, wherein the delay calculation circuit comprises a travelling wave counter and a plurality of oscillation signal generation modules, the plurality of oscillation signal generation modules are used for being in one-to-one correspondence connection with a plurality of target key paths included in a target chip, the plurality of target key paths are a plurality of key paths selected from a plurality of paths included in the target chip, and for each signal count value in the plurality of signal count values, the signal count value is obtained by counting oscillation signals generated by the oscillation signal generation modules under the delay action of the target key paths correspondingly connected through the travelling wave counter;

aiming at each target critical path in a plurality of target critical paths, acquiring a single frequency value representation parameter of the entry mark critical path according to a signal count value corresponding to the entry mark critical path;

and obtaining the integral operating frequency of the target chip according to the single frequency value representation parameter of each target critical path in the plurality of target critical paths.

With reference to the second aspect, an embodiment of the present application further provides a first optional implementation manner of the second aspect, where the obtaining, according to a signal count value corresponding to a target critical path, a single frequency value characterizing parameter of the target critical path includes:

acquiring the period length of a counting time window of a travelling wave counter in a delay calculation circuit;

and substituting a signal count value and the counting time window period length corresponding to the target critical path into a preset single frequency value representation parameter calculation formula, and taking a calculation result output by the single frequency value representation parameter calculation formula as a single frequency value representation parameter of the target critical path.

With reference to the first optional implementation manner of the second aspect, the present application provides a second optional implementation manner of the second aspect, and the calculation formula of the characteristic parameter of the univocal frequency value is as follows:

and CPO _ normal [ i ] is a single frequency value characterization parameter of the target critical path, CPOi is a signal count value corresponding to the target critical path, and N is the period length of a counting time window.

With reference to the second aspect, an embodiment of the present application further provides a third optional implementation manner of the second aspect, where obtaining an overall operating frequency of a target chip according to a single frequency value characterization parameter of each target critical path in multiple target critical paths includes:

calculating median and standard deviation of a plurality of single frequency value representation parameters corresponding to a plurality of target critical paths;

and obtaining the integral operating frequency of the target chip according to the median and the standard deviation.

With reference to the third aspect, this application example further provides a fourth optional implementation manner of the second aspect, where before calculating median and standard deviation of multiple single frequency value characterization parameters corresponding to multiple target critical paths, the method obtains an overall operating frequency of a target chip according to the single frequency value characterization parameter of each target critical path in the multiple target critical paths, and further includes:

and normalizing the single frequency value characterization parameters of each target critical path in the plurality of target critical paths.

With reference to the second aspect, an embodiment of the present application further provides a fifth optional implementation manner of the second aspect, where for each of multiple target critical paths, before obtaining a single frequency value characterization parameter of the target critical path according to a signal count value corresponding to the target critical path, the method for obtaining a chip operating frequency further includes:

and selecting a plurality of target critical paths from a plurality of paths included in the target chip.

With reference to the fifth optional implementation manner of the second aspect, this application example further provides a sixth optional implementation manner of the second aspect, where selecting multiple target critical paths from multiple paths included in a target chip includes:

obtaining path characteristics of each path in a plurality of paths included by a target chip;

determining a path to be deleted which does not meet a preset selection rule in the plurality of paths according to the path characteristics of each path in the plurality of paths, so as to take other paths except the path to be deleted in the plurality of paths as the plurality of paths to be selected;

and selecting a plurality of target key paths from the plurality of paths to be selected.

With reference to the sixth optional implementation manner of the second aspect, an embodiment of the present application further provides a seventh optional implementation manner of the second aspect, where the path characteristics include a plurality of pieces of characteristic information, and the extracting a plurality of target critical paths from a plurality of candidate paths includes:

acquiring a plurality of preset quantity values corresponding to a plurality of pieces of characteristic information one by one;

determining a preset quantity value corresponding to the characteristic information as a target quantity for each piece of characteristic information in the plurality of pieces of characteristic information, and selecting a first target quantity characteristic path with the maximum quantity value from the plurality of paths to be selected according to a sub-selection rule corresponding to the characteristic information;

and if the plurality of pieces of feature information are the first target feature information of the plurality of similar first to-be-selected feature paths which do not exist in the corresponding target quantity of first to-be-selected feature paths, using the target quantity of first to-be-selected feature paths corresponding to each piece of first feature information in the plurality of pieces of feature information together as the plurality of target key paths.

With reference to the seventh optional implementation manner of the second aspect, this application embodiment further provides an eighth optional implementation manner of the second aspect, where, for each piece of feature information in the multiple pieces of feature information, a preset quantity value corresponding to the feature information is determined as a target quantity, and according to a sub-selection rule corresponding to the feature information, after selecting a target quantity of first candidate feature paths with a maximum quantity value from the multiple candidate paths, multiple target critical paths are selected from the multiple candidate paths, and the method further includes:

if the plurality of pieces of feature information include second target feature information of a plurality of similar first to-be-selected feature paths in a corresponding target number of first to-be-selected feature paths, reserving one first to-be-selected feature path in the plurality of similar first to-be-selected feature paths corresponding to the second target feature information for each piece of second target feature information in the plurality of pieces of feature information, deleting other first to-be-selected feature paths in the plurality of similar first to-be-selected feature paths, obtaining at least one remaining first to-be-selected feature path, and recording a quantity value of the deleted first to-be-selected feature path as a to-be-supplemented number;

aiming at each piece of second target characteristic information in the plurality of pieces of characteristic information, selecting a quantity of unselected second candidate characteristic paths which have the maximum metric value and are not selected from the plurality of candidate characteristic paths according to a sub-selection rule corresponding to the second target characteristic information, and combining at least one remaining first candidate characteristic path corresponding to the second target characteristic information to jointly serve as a third candidate characteristic path corresponding to the second target characteristic information;

and in the plurality of pieces of feature information, a target number of first to-be-selected feature paths corresponding to each piece of first target feature information and a target number of third to-be-selected feature paths corresponding to each piece of second target feature information are jointly used as a plurality of target key paths.

With reference to the eighth optional implementation manner of the second aspect, this application embodiment further provides a ninth optional implementation manner of the second aspect, where, for each piece of second target feature information in the plurality of pieces of feature information, according to a sub-selection rule corresponding to the second target feature information, a to-be-supplemented number of second candidate feature paths that have the maximum metric value and are not selected are selected from the plurality of candidate paths, and with reference to at least one remaining first to-be-selected feature path corresponding to the second target feature information, before being collectively used as a target number of third candidate feature paths corresponding to the second target feature information, the method further includes:

aiming at any second target characteristic information in the plurality of pieces of characteristic information, if the number of second to-be-selected characteristic paths which have the maximum metric value and are not selected and are to be supplemented cannot be selected from the plurality of to-be-selected paths according to the sub-selection rule corresponding to the second target characteristic information, updating the preset selection rule to obtain a secondary selection rule;

and determining a path to be deleted which does not meet the secondary selection rule in the plurality of paths according to the path characteristics of each path in the plurality of paths, taking the plurality of paths except the path to be deleted in the plurality of paths as the plurality of paths to be selected, and re-executing the step of selecting the plurality of target key paths from the plurality of paths to be selected.

With reference to the fifth optional implementation manner of the second aspect, this application embodiment further provides a tenth optional implementation manner of the second aspect, where after selecting multiple target critical paths from multiple paths included in a target chip, the method for obtaining a chip operating frequency further includes:

and aiming at each target key path in the plurality of target key paths, if the path delay of the target key path exceeds a preset standard range, performing delay supplementary operation on the target key path so as to enable the path delay of the target key path to be within the preset standard range.

In a third aspect, an embodiment of the present application further provides a device for acquiring a chip operating frequency, including:

the time delay calculation circuit comprises a travelling wave counter and a plurality of oscillation signal generation modules, the oscillation signal generation modules are used for being connected with a plurality of target critical paths included in a target chip in a one-to-one correspondence mode, the plurality of target critical paths are a plurality of critical paths selected from the plurality of paths included in the target chip, and for each signal count value in the plurality of signal count values, the signal count value is obtained by counting oscillation signals generated by the oscillation signal generation modules under the time delay effect of the target critical paths connected correspondingly by the travelling wave counter;

the parameter calculation module is used for acquiring a single frequency value representation parameter of the target key path according to a signal count value corresponding to the target key path aiming at each target key path in the plurality of target key paths;

and the frequency calculation module is used for obtaining the integral operating frequency of the target chip according to the single frequency value representation parameter of each target critical path in the plurality of target critical paths.

In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes a controller and a memory, where the memory stores a computer program, and the controller is configured to execute the computer program to implement the method for obtaining a chip operating frequency according to the second aspect, or any optional implementation manner of the second aspect.

In a fifth aspect, the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed, the method for obtaining the operating frequency of the chip provided in the second aspect or any optional implementation manner of the second aspect is implemented.

The delay calculating circuit provided in the embodiment of the present application includes a selection control module, a traveling wave counter, and a plurality of oscillation signal generating modules, where the plurality of oscillation signal generating modules are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, each oscillation signal generating module is used to generate an oscillation signal under a delay action of a corresponding target critical path, the selection control module is used to select an oscillation signal generated by each oscillation signal generating module of the plurality of oscillation signal generating modules, respectively, and send the selected oscillation signal to the traveling wave counter, the traveling wave counter is used to count each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generating module within a target counting duration in the plurality of oscillation signal generating modules, the signal count value is used for representing the path delay of the target critical path corresponding to the oscillation signal generation module. Because the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, and each path in the chip is not accurately copied as in the prior art, the design difficulty of the delay calculation circuit is low, so that the difficulty of obtaining the overall operating frequency of the target chip is reduced, and the efficiency of obtaining the overall operating frequency of the target chip is improved.

The chip operation frequency obtaining method provided by the embodiment of the application can obtain the single frequency value representation parameter of the target key path according to the signal count value corresponding to the target key path aiming at each target key path in a plurality of target key paths included by the target chip, the signal count value corresponding to the target key path can be obtained through the delay calculating circuit, and then the whole operation frequency of the target chip is obtained according to the single frequency value representation parameter of each target key path in the plurality of target key paths. The delay calculation circuit is designed with low difficulty, so that the difficulty of obtaining the overall operating frequency of the target chip can be reduced, and the chip operating frequency obtaining method provided by the embodiment of the application can rapidly obtain the overall operating frequency of the target chip.

The chip operation frequency obtaining device, the electronic device and the computer readable storage medium provided by the application have the same beneficial effects as the chip operation frequency obtaining method, and are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic circuit structure diagram of a delay calculating circuit according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of an application scenario of a delay calculating circuit according to an embodiment of the present application.

Fig. 3 is a flowchart illustrating steps of a method for acquiring a chip frequency according to an embodiment of the present disclosure.

Fig. 4 is a histogram of Hist [ j ] obtained in an implementation process of the chip frequency obtaining method according to the embodiment of the present application.

Fig. 5 is a distribution diagram of Hist [ j ] drawn in an implementation process of the chip frequency obtaining method according to the embodiment of the present application.

Fig. 6 is an auxiliary explanatory diagram of an implementation process of a chip frequency obtaining method according to an embodiment of the present application.

Fig. 7 is a schematic structural block diagram of a device for acquiring a chip operating frequency according to an embodiment of the present application.

Reference numerals: 100-a delay calculation circuit; 110-select control module; mux21 — second selector; 111-a second controller; 120-a ripple counter; 121-a counting controller; 1211-a counter; an And-AND gate; DF 1-second flip-flop; 130-an oscillation signal generation module; mux11 — first selector; a D-inverter; 131-a first controller; DF 0-first flip-flop; 200-chip operating frequency obtaining device; 210-a parameter calculation module; 220-frequency calculation module.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Furthermore, it should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The first embodiment:

referring to fig. 1, a circuit structure of a delay calculating circuit 100 according to an embodiment of the present disclosure is schematically illustrated, in which the delay calculating circuit 100 includes a selection control module 110, a ripple counter 120, and a plurality of oscillation signal generating modules 130, the plurality of oscillation signal generating modules 130 are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, and the plurality of target critical paths are selected from a plurality of paths included in the target chip.

By the concept of "path", it can be understood a signal transmission path corresponding to a real signal flow in a target chip, and the signal transmission path is composed of devices and wires. Taking the signal flow a existing in the target chip as an example, assuming that the signal flow a is output from the port a1 of the functional module a1 in the target chip, delayed by the delay device a2, inverted by the inverter A3, and finally input to the port a2 of the functional module a4, the signal transmission path corresponding to the signal flow a includes a connection line between the port a1 and the delay device a2, a connection line between the delay device a2, a connection line between the delay device a2 and the inverter A3, an inverter A3, and a connection line between the ports of the inverters A3 and a 2.

In the embodiment of the present application, in the plurality of oscillation signal generation modules 130, each oscillation signal generation module 130 is configured to generate an oscillation signal under a delay action of a corresponding target critical path. The selection control module 110 is configured to select an oscillation signal generated by each oscillation signal generation module 130 of the plurality of oscillation signal generation modules 130, and send the selected oscillation signal to the ripple counter 120. The ripple counter 120 is configured to count each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generation module 130 in the plurality of oscillation signal generation modules 130 within a target counting duration, where the signal count value is used to characterize a path delay of a target critical path corresponding to the oscillation signal generation module 130.

Referring to fig. 2, in the embodiment of the present application, each of the oscillation signal generating modules 130 may include a first selector Mux11, an inverter D, and a first controller 131.

A first input end of the first selector Mux11 is configured to access an initial signal value, an output end of the first selector Mux11 is used as a first external port of the oscillation signal generating module 130, and the first external port of the oscillation signal generating module 130 is configured to access an input end of a target critical path corresponding to the oscillation signal generating module 130. The input end of the inverter D serves as the output end of the oscillation signal generating module 130 and a second external port, the second external port of the oscillation signal generating module 130 is used for accessing the output end of the target critical path corresponding to the oscillation signal generating module 130, and the output end of the inverter D is connected to the second input end of the first selector Mux 11. The first controller 131 is connected to a control input of the first selector Mux 11.

It should be noted that, in the embodiment of the present application, the first selector Mux11 may be an alternative data selector. The first selector Mux11 works on the principle: the output terminal of the first selector Mux11 can determine whether to select the signal value inputted from the first input terminal to be outputted through the output terminal or to select the signal value inputted from the second input terminal to be outputted through the output terminal according to the first control signal inputted from the control input terminal. In addition, in the embodiment of the present application, the first controller 131 may be a register, in which the preconfigured first control signal is stored.

To implement the automatic control starting of the selection control module 110, in the embodiment of the present application, the oscillation signal generation module 130 may further include a first trigger DF 0.

The clock control end of the first flip-flop DF0 is connected to the system clock, the input end of the first flip-flop DF0 is connected to the start indication signal, and the output end of the first flip-flop DF0 is connected to the first input end of the first selector Mux11 for outputting the initial signal value.

In the embodiment of the present application, the first flip-flop DF0 may be a D flip-flop, specifically, a D flip-flop triggered by a rising edge, but it should be noted that, in practical implementation, the first flip-flop DF0 may also be a D flip-flop triggered by a falling edge, and the embodiment of the present application does not specifically limit this. In addition, in the embodiment of the present application, the start indication signal may be a signal with any fixed value, for example, a high-level logic signal "1" or a low-level logic signal "0".

As for the selection control module 110, in the embodiment of the present application, as an optional implementation manner, it may include a second selector Mux21 and a second controller 111.

The second selector Mux21 includes a plurality of input terminals, the plurality of input terminals of the second selector Mux21 are connected to the output terminals of the plurality of oscillation signal generation modules 130 in a one-to-one correspondence, and the output terminal of the second selector Mux21 serves as the output terminal of the selection control module 110. The second controller 111 is connected to a control input of the second selector Mux 21.

It is understood that in the embodiment of the present application, the second selector Mux21 is a one-out-of-multiple data selector including a plurality of input terminals, an output terminal and a control input terminal. The working principle of the second selector Mux21 is: the output terminal of the second selector Mux21 is capable of selecting one signal value from the signal values input from the plurality of input terminals to output from the output terminal according to the second control signal input from the control input terminal. For example, the output terminal of the second selector Mux21 can select a signal value input from a first input terminal to be output from the output terminal among signal values input from a plurality of input terminals in a first period of time, select a signal value input from a second input terminal to be output from the output terminal among signal values input from a plurality of input terminals in a second period of time, and select a signal value input from a third input terminal to be output from the output terminal among signal values input from a plurality of input terminals in a third period of time, and so on, according to the second control signal input from the control input terminal. In the first time interval, the second time interval and the third time interval, no cross coincidence time exists between every two time intervals. In addition, in the embodiment of the present application, the second controller 111 may also be a register, in which the preconfigured second control signal is stored.

For the ripple counter 120, as an optional implementation manner in this embodiment of the present application, it may include a count controller 121 and a plurality of second flip-flops DF1, where the plurality of second flip-flops DF1 are connected in sequence, and in the plurality of second flip-flops DF1, a clock control end of a first flip-flop is connected to an output end of the selection control module 110 through the count controller 121, in the plurality of second flip-flops DF1, an output end of a last flip-flop is used as a high-order output end of the ripple counter 120, and correspondingly, in the plurality of second flip-flops DF1, an output end of the first flip-flop is used as a low-order output end of the ripple counter 120.

In the embodiment of the present application, the second flip-flop DF1 may also be a D flip-flop, specifically, a D flip-flop triggered by a rising edge, but it should be noted that in practical implementation, the second flip-flop DF1 may also be a D flip-flop triggered by a falling edge, which is not limited in this embodiment of the present application.

For any two adjacent second flip-flops DF1 of the plurality of second flip-flops DF1 (including the first-stage flip-flop and the last-stage flip-flop), the output terminal of the second flip-flop DF1 positioned at the front is connected to the clock control terminal of the second flip-flop DF1 positioned at the back, and for each second flip-flop DF1 of the plurality of second flip-flops DF1, the inverting output terminal of the second flip-flop DF1 is connected to the input terminal of the second flip-flop DF 1. In addition, in the embodiment of the present application, the first-stage flip-flop is the second flip-flop DF1 (i.e., the leftmost second flip-flop DF1 in fig. 2) located most forward in the signal transmission path, among the plurality of second flip-flops DF1, and the last-stage flip-flop is the second flip-flop DF1 (i.e., the rightmost second flip-flop DF1 in fig. 2) located most backward in the signal transmission path.

In the second flip-flops DF1, the signal value output by the output terminal of each second flip-flop DF1 is used as the 1-bit output of the ripple counter 120, and the multi-bit outputs corresponding to the second flip-flops DF1 are used as the signal count value finally output by the ripple counter 120, and the signal count value is a binary number value, the highest bit of the signal count value is the signal value output by the output terminal of the last flip-flop, and the lowest bit of the signal count value is the signal value output by the output terminal of the first flip-flop. Taking the specific number of the second flip-flops DF1 in the ripple counter 120 as 12 as an example, according to the sequence of the signal transmission paths, the signal values output from the output terminals of the first-stage flip-flop (the first second flip-flop of the 12 second flip-flops DF1) to the last-stage flip-flop (the twelfth second flip-flop) are respectively recorded as Out1, Out2, Out3, Out4, Out5, Out6, Out7, Out8, Out9, Out10, and Out11, so that the signal count value finally output by the ripple counter 120 is binary value "Out 11 Out10 Out9Out8, Out7 Out6 Out5 Out4, Out3 Out2 Out1 Out 0".

Further, in the embodiment of the present application, the counting controller 121 may include a counter 1211 And an And gate And.

The input terminal of the counter 1211 is connected to the system clock, And the output terminal of the counter 1211 is connected to the first input terminal of the And gate And. A second input terminal of the And gate ad is connected to the output terminal of the selection control module 110 as an input terminal of the ripple counter 120, that is, to the output terminal of the second selector Mux21, And an output terminal of the And gate ad is connected to the clock control terminal of the first stage flip-flop.

Hereinafter, the operation principle of the delay calculating circuit 100 shown in fig. 1 and 3 will be described.

For each oscillation signal generation module 130 in the plurality of oscillation signal generation modules 130, the clock control end of the first flip-flop DF0 included therein is connected to the system clock, the input end of the first flip-flop DF0 is connected to the start indication signal, when the rising edge of the system clock arrives, the first flip-flop DF0 latches the start indication signal input through the input end of the first flip-flop DF0 at the current moment, and outputs the start indication signal to the output end of the first flip-flop DF0 as an initial signal value. Thereafter, the first controller 131 controls the first selector Mux11 to select a signal value input from the first input terminal and output from the output terminal according to the preconfigured first control signal, that is, select an initial signal value and output from the output terminal. Taking the start instruction signal as the high logic signal "1", the initial signal value is the same as the start instruction signal and is also the high logic signal "1", and therefore, the signal value output from the output terminal of the first selector Mux11 is also the high logic signal "1". Thereafter, the high level logic signal "1" is output after being delayed by the target critical path, and at the same time, the high level logic signal "1" after being delayed is converted into the low level logic signal "0" after being inverted by the inverter D, and then, the first controller 131 controls the first selector Mux11 to select a signal value input from the second input terminal from the first input terminal and the second input terminal and output it from the output terminal according to the preconfigured first control signal, that is, to select the low level logic signal "0" and output it from the output terminal, and the low level logic signal "0" is output after being delayed by the target critical path, and at the same time, the low level logic signal "0" after being delayed is converted into the high level logic signal "1" after being inverted by the inverter D, and then, the first controller 131 controls the output terminal of the first selector Mux11 to continue from the first input terminal and the second input terminal according to the preconfigured first control signal, and selecting the signal value input from the second input end and outputting the signal value from the output end, namely, selecting a high-level logic signal '1' and outputting the signal value from the output end, wherein the high-level logic signal '1' is output after the delay of the target critical path and continues to circulate.

While each oscillation signal generation block 130 of the plurality of oscillation signal generation blocks 130 performs the above-described operation, the second controller 111 controls the second selector Mux21 to select the signal value inputted from each input terminal in turn from the signal values inputted from the plurality of input terminals, respectively, according to a second control signal configured in advance, and outputs the signal value from the output terminal, for example, the second selector Mux21 is controlled to select a signal value input from a first input terminal among the plurality of input terminals for a first period of time, and is outputted from the output terminal, controls the second selector Mux21 to select a signal value inputted from a second input terminal among the plurality of input terminals for a second period, and is outputted from the output terminal, controls the second selector Mux21 to select a signal value inputted from a third input terminal among the plurality of input terminals for a third period, and is outputted from the output terminal, and so on, wherein the first time period precedes the second time period, which in turn precedes the third time period.

Similarly, the second controller 111 and the second selector Mux21 perform the above operations, and the counter 1211 counts the input system clock, and outputs a high-level logic signal "1" through the output terminal to start or continue counting by the ripple counter 120 if the count value is within the preset counting range, and outputs a low-level logic signal "0" through the output terminal to stop counting by the ripple counter 120 if the count value exceeds the preset counting range.

It can be understood that, in the embodiment of the present application, a time length corresponding to a process in which a count value obtained by counting a system clock reaches a maximum value within a preset count range from 1 is a target counting time length. In addition, in the embodiment of the present application, the preset counting range may be set according to the specific number of the second flip-flops DF1 in the ripple counter 120, for example, the preset counting range may be [1, 2 ]^M]Where M is the specific number of second flip-flops DF1 in the ripple counter 120, then if M is 12, the preset count range may be [1, 4096 ]]. Based on this, it can be understood that in the embodiment of the present application, the ripple counter 120 is mainly 2 of the system clock after being started^MThe oscillation generated by the oscillation signal generation module 130 selected by the selection control module 110 during one periodThe oscillation signal is counted, and 2 of the system clock^MThe length of each period is the target counting time length.

In addition, in the embodiment of the present application, if the second controller 111 switches the value of the signal output from the output terminal according to the second control signal configured in advance, the counter 1211 is reset to zero, that is, the counter 1211 restarts to count the input system clock. For example, the second controller 111 controls the second selector Mux21 to select the signal value inputted from the first input terminal of the plurality of input terminals (i.e., the oscillation signal generated by the first oscillation signal generation module 130) during the first period according to the pre-configured second control signal, and is outputted from the output terminal, if the count value of the counter 1211 exceeds the predetermined count range, the counter 1211 is reset to zero and outputs a low logic signal '0' through the output terminal to stop the ripple counter 120 from counting, and thereafter, after the second controller 111 switches to control the second selector Mux21 to select the signal value input from the second input terminal of the plurality of input terminals (i.e., the oscillation signal generated by the second oscillation signal generation module 130) in the second period according to the preconfigured second control signal and output the signal value from the output terminal, the second counter 1211 is reset and cleared.

Finally, the ripple counter 120 counts the received oscillation signals generated by each oscillation signal generation module 130 in the plurality of oscillation signal generation modules 130 to obtain a signal count value of the oscillation signal generated by each oscillation signal generation module 130 in the plurality of oscillation signal generation modules 130 within the target counting time duration, where the signal count value may be used to represent the path delay of the target critical path corresponding to the oscillation signal generation module 130, that is, the path delay of the target critical path corresponding to the oscillation signal generation module 130 may be calculated according to the signal count value. Furthermore, it can be understood that, for the target chip, the path delay of the plurality of target critical paths included therein may ultimately affect the overall operating frequency of the target chip.

Because the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, and each path in the chip is not accurately copied as in the prior art, the design difficulty of the delay calculation circuit is low, so that the difficulty of obtaining the overall operating frequency of the target chip is reduced, and the efficiency of obtaining the overall operating frequency of the target chip is improved.

Second embodiment:

please refer to fig. 3, which is a flowchart illustrating a method for obtaining a chip operating frequency according to an embodiment of the present disclosure. It should be noted that the chip operating frequency obtaining method provided in the embodiment of the present application is not limited by the sequence shown in fig. 3 and the following, and the specific flow and steps of the chip operating frequency obtaining method are described below with reference to fig. 3.

Step S100, obtaining a plurality of signal count values obtained by a delay calculating circuit, where the delay calculating circuit includes a traveling wave counter and a plurality of oscillation signal generating modules, the plurality of oscillation signal generating modules are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, and for each signal count value in the plurality of signal count values, the signal count value is obtained by counting, by the traveling wave counter, oscillation signals generated by the oscillation signal generating modules under a delay action of the target critical paths connected correspondingly. It is to be understood that, in step S100, the delay time calculation circuit may be provided by the first embodiment.

Step S200, aiming at each target key path in a plurality of target key paths, obtaining a single frequency value representation parameter of the target key path according to a signal count value corresponding to the target key path.

Regarding step S200, in the embodiment of the present application, as an optional implementation manner, it may include step S210 and step S220.

Step S210, obtaining the counting time window period length of the ripple counter in the delay calculating circuit.

And step S220, substituting a signal count value and a counting time window period length corresponding to the target critical path into a preset single frequency value representation parameter calculation formula, and taking a calculation result output by the single frequency value representation parameter calculation formula as a single frequency value representation parameter of the target critical path.

In the embodiment of the present application, the calculation formula of the single-term frequency value representation parameter may be:

wherein, CPO _ normal [ i ]]Marking a single frequency value characterization parameter, CPO, of the critical path for the ith entry in a plurality of target critical paths_iFor the plurality of target critical paths, the ith entry marks a signal count value corresponding to the critical path, and N is a count time window period length, that is, the target count duration in the first embodiment, however, specifically, in the single-term frequency value characterization parameter calculation formula, N is substantially the number of clock periods corresponding to the target count duration, for example, if the target count duration is equal to 4096 system clock periods, the value of N is 4096.

In addition, it can be understood that, in the embodiment of the present application, for a plurality of target critical paths, an ith entry marks a single frequency value characterizing parameter of the critical path, and the single frequency value characterizing parameter has the following logical relationship with a frequency of an oscillating signal generated by an ith oscillating signal generating module under a delay action of a corresponding target critical path in a plurality of oscillating signal generating modules:

wherein, CPO _ normal [ i ]]Marking a single frequency value characterization parameter, CPO, of the critical path for the ith entry in a plurality of target critical paths_iMarking the signal count value corresponding to the key path for the ith item in a plurality of target key paths, wherein N is the cycle length of a counting time window, F_CPOiFor the frequency, F, of the oscillation signal generated by the ith oscillation signal generation module under the delay action of the corresponding target critical path in the plurality of oscillation signal generation modules_CclkFor the frequency of the system clock。

Step S300, obtaining the integral operating frequency of the target chip according to the single frequency value representation parameter of each target critical path in the plurality of target critical paths.

In the embodiment of the application, because the single frequency value characterization parameters of the multiple target critical paths conform to normal distribution, the overall operating frequency of the target chip can be obtained according to the median and the standard deviation of the single frequency value characterization parameters of the multiple target critical paths. Based on this, in the embodiment of the present application, step S300 may include step S310 and step S320.

Step S310, calculating the median and standard deviation of a plurality of single frequency value characterization parameters corresponding to a plurality of target critical paths.

And step S320, obtaining the integral operating frequency of the target chip according to the median and the standard deviation.

In the embodiment of the present application, before the step S310 is executed, a step S301 may be further included to reduce the calculation difficulty of the step S310.

Step S301, performing normalization processing on the single frequency value representation parameter of each target key path in the plurality of target key paths.

In this embodiment, after step S310 is executed, the normalization value-taking interval may be divided into a plurality of equal-sized sub-intervals according to the number of the target critical paths, for example, if the number of the target critical paths is 32, the normalization value-taking interval may be divided into 32 equal-sized sub-intervals.

Referring to fig. 4, assuming that after step S310 is executed, the single frequency value characterizing parameter of each target critical path in the plurality of target critical paths falls within the normalized value Range [0.30, 1.23], the normalized value Range [0.30, 1.23] is divided into 32 equal-sized sub-ranges (ranges) denoted as BucketRange [ i ] (j is 0, 1, 2 … … 31), where BucketRange [ i ] is 0.30+ j is 0.03(j is 0, 1, 2 … … 31). After that, it is determined to which subinterval (Range) CPO _ normal [ i ] belongs, and if CPO _ normal [ i ] belongs to the jth subinterval (Range), there is (BucketRange [ j-1] < CPO _ normal [ i ] < ═ BucketRange [ j ]), the frequency falling into the jth subinterval (Range) is increased by 1, that is, Hist [ j ], which is the frequency of the jth subinterval (Range), and finally, the histogram of Hist [ j ] is obtained. After the histogram of Hist [ j ] is obtained, the Median and the standard deviation of a plurality of single frequency value characterization parameters corresponding to a plurality of target critical paths can be calculated according to the histogram of Hist [ j ], and then Fcpo is calculated according to the Median and the standard deviation.

Referring to FIGS. 5 and 6, first, a histogram of Hist [ j ] may be plotted from the histogram of Hist [ j ], and for each entry in the histogram, there is:

HistDistributate [31] in the histogram is the summation of all values in the histogram, MedianNum 0.5 HistDistributate [31] is the Y value of the median in the histogram, and the X value corresponding to Y medianNum can be calculated according to the difference method, so as to calculate the median, and the specific calculation process can be as follows:

since the normally distributed Median-Sigma is located at the point of 0.16 area of the normally distributed probability density function, the value sigmarnum of Median-Sigma on the Y-axis in the distribution map may be:

SigmaNum＝HistDistribute[31]*0.16

like the method for calculating Median, the X-axis coordinate of sigmarnum in the distribution map can be calculated by linear interpolation, and is written as X:

because Sigma ═ media-X exists, finally, the overall operating frequency of the target chip is obtained:

F_CPO＝(a*Median+b*Sigma)*F_cclk

wherein a is a coefficient of Median, b is a coefficient of Sigma, and a and b can be obtained by simulation test specifically, which is not limited in this application.

Further, in the embodiment of the present application, the plurality of target critical paths need to be pre-selected from the plurality of paths included in the target chip, and the steps S100, S200, and S300 can be executed only after the plurality of target critical paths are selected from the plurality of paths included in the target chip. Based on this, the method for obtaining the operating frequency of the chip provided in the embodiment of the present application may further include step S001 before step S100 is executed.

Step S001, selecting a plurality of target critical paths from the plurality of paths included in the target chip.

In this embodiment of the application, for each of the paths described in step S001, it may be understood that, among all signal transmission paths included in the target chip, a signal transmission path capable of embodying the characteristics of the circuit module in which the target chip is located, but whether the characteristics of the circuit module in which the target chip is located are capable of embodying the characteristics of the circuit module in which the target chip is located may mainly be determined by determining whether the target chip meets a preset characteristic standard.

In the embodiment of the present application, the characteristic criteria include at least the following four types:

(1) a master clock domain belonging to a target chip;

(2) belonging to a monocycle path;

(3) a function-related path belonging to the circuit module;

(4) the path delay needs to be satisfied: (1-5%) clock cycle < path delay <1 clock cycle.

It should be noted that, in the embodiment of the present application, for a certain path, its clock cycle may be understood as the clock cycle of the target chip. In addition, it should be noted that, in the embodiment of the present application, the characteristic standard may be adjusted according to the actual design requirement of the target chip, and the embodiment of the present application does not specifically limit this.

While determining the plurality of paths included in the target chip, for each of the plurality of paths, the position of the path in the path selection pool may be set according to the degree of conformity with the characteristic standard, for example, the higher the degree of conformity with the characteristic standard, the higher the position in the path selection pool. After determining the multiple paths included in the target chip, step S001 may be executed to select multiple target critical paths from the multiple paths included in the target chip, and as for step S001, in this embodiment of the present application, as an optional implementation manner, step S0011, step S0012, and step S0013 may be included.

Step S0011, a path feature of each path in the plurality of paths included in the target chip is obtained.

In the embodiment of the present application, the path characteristics may include characteristic parameters and Design Rule Check (DRC) characteristics.

The characteristic parameters at least comprise the following six types:

(1) the sum of the number of buffers and inverters on the path;

(2) the sum of the distances between two adjacent circuit units on the path, wherein the circuit units are combinational logic units;

(3) the combinational logic delay of the path, that is, the sum of the delays of all the combinational logic units on the path and the connection delays between all the combinational logic units on the path;

(4) the sum of the delays of all circuit units on the path;

(5) the sum of the connection delays among all circuit units on the path;

(6) the device type of the smallest logic block in all circuit units on a path can be further distinguished, for example, buffers, inverters, adders, and gates, etc., to further understand the characteristics of each path.

The DRC characteristics may include at least: the maximum transition Time (Max-Trans-Time) of all circuit elements on a path, where "transition" can be understood as a transition of logic level High/Low, i.e. a transition between a High logic signal "1" and a Low logic signal "0".

And S0012, determining paths to be deleted which do not meet preset selection rules in the multiple paths according to path characteristics of each path in the multiple paths, so that the paths except the paths to be deleted in the multiple paths are used as the multiple paths to be selected.

In this embodiment of the application, the path characteristics include a plurality of pieces of characteristic information, and in combination with the relevant description of step S0011, the plurality of pieces of characteristic information may include at least the following seven kinds:

(1) the sum of the number of buffers and inverters on the path is recorded as first characteristic information;

(2) the sum of the distances between two adjacent circuit units on the path is recorded as second characteristic information;

(3) the combinational logic delay of the path is recorded as third characteristic information;

(4) the sum of the time delays of all circuit units on the path is recorded as fourth sign information;

(5) the sum of the connection delays among all circuit units on the path is recorded as fifth sign information;

(6) recording the device type of the minimum logic block in all circuit units on the path as sixth characteristic information;

(7) the maximum transition Time (Max-Trans-Time) of all circuit units on the path is taken as the seventh characteristic information.

After it is determined that the path feature includes a plurality of pieces of feature information, for each piece of feature information in the plurality of pieces of feature information, a sub-selection rule corresponding to the feature information may be set, that is, the preset selection rule includes a plurality of sub-selection rules, and in the plurality of pieces of feature information, each piece of feature information corresponds to one sub-selection rule in the plurality of sub-selection rules, and of course, two pieces of feature information may also correspond to one sub-selection rule in the plurality of sub-selection rules, which is not particularly limited in this embodiment of the present application.

For example, for the first feature information, the corresponding sub-selection rule may be: the sum of the number of the buffers and the number of the inverters on the path is greater than a preset value, and the specific number of the preset value can be adjusted according to the actual design requirement of the target chip, which is not specifically limited in the embodiment of the present application, and the sub-selection rule corresponding to the first feature information may also be: the specific number of the paths with the larger sum of the numbers of the buffers and the inverters on the path can be adjusted according to the actual design requirement of the target chip, and the embodiment of the present application does not specifically limit this.

For another example, for the second feature information, the corresponding sub-selection rule may be: the sum of the distances between two adjacent circuit units on the path is located in a preset distance interval, and the specific range of the preset distance interval can be adjusted according to the actual design requirement of the target chip, which is not specifically limited in the embodiment of the present application.

For another example, for the third feature information, the corresponding sub-selection rule may be: the combined logic delay of 80% clock cycle < path < 120% clock cycle.

For another example, for the fourth feature information and the fifth feature information, they may correspond to a sub-selection rule: and the sum of the time delays of all circuit units on the path is less than 2 times the sum of the connection time delays between all circuit units on the path.

For another example, for the sixth feature information, the corresponding sub-selection rule may be: the smallest logic block with the device type of an analog module exists in all circuit units on the path.

For another example, for the seventh feature information, the corresponding sub-selection rule may be: the maximum transition Time (Max-Trans-Time) of all circuit cells on a path is < 20% clock period.

Based on the above description, when step S0012 is executed, a path to be deleted that does not satisfy any preset selection rule of the seven sub-selection rules among the multiple paths may be determined according to the path characteristics of each path among the multiple paths, so that multiple paths other than the path to be deleted among the multiple paths are used as multiple paths to be selected.

And S0013, selecting a plurality of target key paths from the plurality of paths to be selected.

In the embodiment of the present application, after the multiple candidate paths are acquired, step S0013 needs to be further executed to select multiple target critical paths from the multiple candidate paths, and for step S0013, as an optional implementation manner, the embodiment of the present application may include step S00131, step S00132, and step S00133.

Step S00131, a plurality of preset quantity values corresponding to the plurality of pieces of feature information one to one are obtained.

In the embodiment of the present application, for each piece of feature information in the plurality of pieces of feature information, the corresponding preset quantity value may be adjusted according to an actual design requirement of the target chip, which is not specifically limited in the embodiment of the present application.

And S00132, determining a preset quantity value corresponding to the characteristic information as a target quantity for each piece of characteristic information in the plurality of pieces of characteristic information, and selecting a first target quantity characteristic path with the maximum quantity value from the plurality of candidate paths according to a sub-selection rule corresponding to the characteristic information.

In the embodiment of the application, for each piece of feature information in the plurality of pieces of feature information, the plurality of paths to be selected may be arranged in a descending order in advance according to the sub-selection rule corresponding to the piece of feature information. It is assumed that the multiple candidate paths include path 1, path 2, path 3, path 4, path 5, path 6, path 7, path 8, path 9, and path 10 (in an actual implementation process, the number of the multiple candidate paths is much greater than 10), and a corresponding relationship between the multiple candidate paths and the first feature information, that is, a corresponding relationship between the multiple candidate paths and the sum of the numbers of the buffers and the inverters on the paths is shown in table 1.

TABLE 1

Then, after the multiple paths to be selected are arranged in a descending order according to the sub-selection rule corresponding to the first feature information, the obtained arrangement order is as follows: path 4 > Path 10 > Path 2 > Path 9 > Path 6 > Path 7 > Path 1 > Path 5 > Path 8 > Path 3.

Thus, when step S00132 is executed, for the first feature information, if the preset quantity value corresponding to the first feature information is 3, that is, the target quantity is 3, then according to the above arrangement sequence, the 3 first candidate feature paths having the largest quantity value in terms of the first feature information may be selected from the multiple candidate paths, that is, the path 4, the path 10, and the path 2 are selected as the first candidate feature paths.

Step S00133, if the plurality of pieces of feature information are the first target feature information of the plurality of similar first to-be-selected feature paths that do not exist in the corresponding target number of first to-be-selected feature paths, using the target number of first to-be-selected feature paths corresponding to each piece of first feature information in the plurality of pieces of feature information together as the plurality of target critical paths.

Similarly, taking the multiple candidate routes including route 1, route 2, route 3, route 4, route 5, route 6, route 7, route 8, route 9, and route 10 as an example, if the multiple candidate routes are sorted in descending order according to the sub-selection rule corresponding to the first feature information, the obtained sort order is: path 4 > path 10 > path 2 > path 9 > path 6 > path 7 > path 1 > path 5 > path 8 > path 3, and the preset quantity value corresponding to the first feature information is 3, that is, the target quantity is 3, then the 3 first candidate feature paths corresponding to the first feature information are path 4, path 10 and path 2, where the first feature information of path 4 is 16, the first feature information of path 10 is 15, and the first feature information of path 4 is 12. Based on this, it can be determined that the first feature information is the first target feature information of a plurality of similar first to-be-selected feature paths which do not exist in the corresponding target number of first to-be-selected feature paths.

Similarly, it may be determined whether other feature information in the plurality of pieces of feature information is first target feature information in which no similar plurality of first candidate feature paths exist in corresponding target number pieces of first candidate feature paths, and if all other feature information in the plurality of pieces of feature information is first target feature information in which no similar plurality of first candidate feature paths exist in corresponding target number pieces of first candidate feature paths, the target number pieces of first candidate feature paths corresponding to each piece of first feature information in the plurality of pieces of feature information are collectively used as the plurality of target key paths. Of course, in an actual implementation process, the plurality of pieces of feature information usually include second target feature information of a plurality of similar first candidate feature paths among the corresponding target number of first candidate feature paths. Based on this, for step S0013, as an optional implementation manner, in the embodiment of the present application, after step S00132, step S00134, step S00135, and step S00136 may also be included.

Step S00134, if the plurality of pieces of feature information include second target feature information of a plurality of similar first candidate feature paths in the corresponding target number of first candidate feature paths, for each piece of second target feature information in the plurality of pieces of feature information, leaving one first candidate feature path in the plurality of similar first candidate feature paths corresponding to the second target feature information, deleting other first candidate feature paths in the plurality of similar first candidate feature paths, obtaining at least one remaining first candidate feature path, and recording a quantity value of the deleted first candidate feature path as a to-be-supplemented number.

Continuing with the example that the multiple candidate paths include path 1, path 2, path 3, path 4, path 5, path 6, path 7, path 8, path 9, and path 10, if the multiple candidate paths correspond to the first characteristic information, that is, the sum of the numbers of buffers and inverters on the paths, as shown in table 2.

TABLE 2

Then, after the multiple paths to be selected are arranged in a descending order according to the sub-selection rule corresponding to the first feature information, the obtained arrangement order is as follows: path 4 > path 2 > path 9 > path 6 > path 7 > path 1 > path 5 > path 8 > path 3.

If the preset quantity value corresponding to the first feature information is 3, that is, the target quantity is 3, then the 3 first candidate feature paths corresponding to the first feature information are path 4, path 10 and path 2, where the first feature information of path 4 is 16, the first feature information of path 10 is 16, and the first feature information of path 4 is 12. Based on this, it may be determined that the first feature information is second target feature information of a plurality of similar first candidate feature paths among the corresponding target number of first candidate feature paths, and specifically there are two similar first candidate feature paths, that is, path 4 and path 10.

In the above situation, for the second target feature information, it is necessary to leave a first candidate feature path in the path 4 and the path 10, delete another first candidate feature path in the path 4 and the path 10, obtain at least one remaining first candidate feature path, and record a quantity value of the deleted first candidate feature path as a quantity to be supplemented. In actual implementation, the first candidate feature path that may be reserved is a path with a relatively previous position in the candidate pool, and the deleted first candidate feature path is a path with a relatively later position in the candidate pool, and assuming that path 4 is just a path with a relatively previous position in the candidate pool and path 10 is just a path with a relatively later position in the candidate pool, the remaining at least one first candidate feature path is finally obtained and includes path 4 and path 2, and the quantity value of the deleted first candidate feature path is 1, that is, the quantity to be supplemented is 1.

And S00135, selecting, according to a sub-selection rule corresponding to the second target feature information, a number of unselected second candidate feature paths which have the largest metric and are not selected from the plurality of candidate paths according to each piece of second target feature information in the plurality of pieces of feature information, and taking the second candidate feature paths as a number of third candidate feature paths corresponding to the second target feature information together with at least one remaining first candidate feature path corresponding to the second target feature information.

Continuing with the example in step S00134, the first feature information is substantially the second target feature information, and according to the sub-selection rule corresponding to the second target feature information, the second candidate feature paths with the maximum metric value are selected from the multiple candidate paths, and the number of unselected candidate feature paths to be supplemented may be: and selecting the path 9 from the path 9, the path 6, the path 7, the path 1, the path 5, the path 8 and the path 3, and then combining the remaining at least one first candidate feature path corresponding to the piece of second target feature information, that is, the path 4 and the path 2, to jointly serve as 3 third candidate feature paths corresponding to the piece of second target feature information.

It should be noted that, in this embodiment of the application, after selecting, according to a sub-selection rule corresponding to second target feature information, a number of second candidate feature paths that have the largest metric value and are not selected and are to be supplemented from the number of second candidate feature paths according to each piece of second target feature information in the number of second target feature information, and taking at least one remaining first candidate feature path corresponding to the second target feature information as a number of third candidate feature paths corresponding to the second target feature information together, it is substantially necessary to determine whether there are multiple similar third candidate feature paths in the number of third candidate feature paths. And if the target quantity of third candidate feature paths do not have the similar third candidate feature paths, executing a step S00136, and if the target quantity of third candidate feature paths have the similar third candidate feature paths, continuously deleting and complementarily selecting the candidate feature paths according to the invention concepts of the step S00134 and the step S00135 until the selected target quantity of third candidate feature paths do not have the similar third candidate feature paths.

Step S00136, a target number of first candidate feature paths corresponding to each piece of first target feature information in the plurality of pieces of feature information, and a target number of third candidate feature paths corresponding to each piece of second target feature information in the plurality of pieces of feature information are collectively used as a plurality of target critical paths.

It should be noted that, in this embodiment of the application, for each piece of feature information in the plurality of pieces of feature information, the step S00131, the step S00132, and the step S00133 are executed, or the step S00131, the step S00132, the step S00134, the step S00135, and the step S00136 are executed, so that a process of selecting a target number of to-be-selected feature paths corresponding to the piece of feature information finally from the plurality of to-be-selected paths is not performed simultaneously, that is, the foregoing step is executed for each piece of feature information in the plurality of pieces of feature information, so that a process of selecting a target number of to-be-selected feature paths corresponding to the piece of feature information finally from the plurality of to-be-selected paths is in a sequential order. Thus, for a certain piece of feature information in the multiple pieces of feature information, after the foregoing step is executed to select a target quantity piece of feature information corresponding to the feature information finally from the multiple pieces of feature information to be selected, the currently selected target quantity piece of feature information to be selected may be deleted from the path selection pool, that is, the target quantity piece of feature information to be selected from the multiple pieces of feature information to be selected is deleted to avoid subsequent re-selection, so that the situation that the same path exists in the multiple target critical paths occurs.

In addition, it should be noted that, in the embodiment of the present application, when step S00135 is executed, there may be a case that: for any second target characteristic information in the plurality of pieces of characteristic information, the number of second candidate characteristic paths which have the maximum metric value and are not selected and to be supplemented cannot be selected from the plurality of candidate paths according to the sub-selection rule corresponding to the second target characteristic information, and then the preset selection rule adopted when the step S0012 is executed is too limited. Based on this, in the embodiment of the present application, before executing step S00135, step S0013 may further include step S00137 and step S00138, where the step S00137 and the step S00138 are used to update a preset selection rule, so as to improve a success rate of selecting the multiple target critical paths.

Step S00137, for any second target feature information in the plurality of pieces of feature information, if the second target feature information cannot be selected according to the sub-selection rule corresponding to the second target feature information, the second candidate feature path having the largest metric value and not selected yet is selected, updating the preset selection rule, and obtaining a secondary selection rule.

And S00138, determining a path to be deleted, which does not meet the secondary selection rule, from the multiple paths according to the path characteristics of each path in the multiple paths, so as to take the multiple paths except the path to be deleted as multiple paths to be selected, and re-executing the step of selecting multiple target key paths from the multiple paths to be selected.

In the embodiment of the present application, when the preset selection rule is updated, the preset selection rule may be specifically updated according to the actual design requirement of the target chip, which is not specifically limited in the embodiment of the present application.

Further, the method for obtaining the operating frequency of the chip provided in the embodiment of the present application may further include step S002 after step S001 is executed, so as to ensure the availability of the selected multiple target critical paths.

Step S002, for each target critical path of the plurality of target critical paths, if the path delay of the target critical path exceeds the preset standard range, performing a delay supplementary operation on the target critical path, so that the path delay of the target critical path is within the preset standard range.

In this embodiment, the preset standard range may be a delay interval (80% clock cycle, 100% clock cycle), that is, a critical path is marked for a certain entry in the target critical paths, and if the path delay does not satisfy 80% clock cycle < path delay < 100% clock cycle, for example, is located in the delay interval (40% clock cycle, 80% clock cycle), it is considered that the path delay exceeds the preset standard range. For convenience of description, in the embodiment of the present application, a target critical path whose path delay exceeds a preset standard range may be defined as a path to be supplemented. In addition, it should be noted that, in the embodiment of the present application, performing a delayed replenishment operation on the path to be replenished, that is, performing an Engineering Change Order (ECO) operation on the path to be replenished. In the embodiment of the present application, a process of performing a delayed replenishment operation on a to-be-replenished path will be described below.

And determining the characteristic information corresponding to the path to be supplemented as the third target characteristic information, namely determining the path to be supplemented according to which characteristic information is selected from the multiple paths to be selected, and then using the characteristic information as the third target characteristic information. And then, determining the devices to be added for performing the time-delay supplement operation on the path to be supplemented according to the third target characteristic information, for example, determining whether the devices to be added are inverters, adders or and gates. After determining the device to be added, the load delay table of the corresponding device is obtained, for example, after determining that the device to be added is an and gate, the load delay table of the and gate may be obtained.

For a certain device, the acquisition of the load delay table needs to be comprehensively obtained by combining the front-stage driving and the rear-stage load of the device. Taking an and gate as an example, first, a first delay complementary path including a 5-stage and gate may be constructed, and, assuming that, in the first delay complementary path, the drive of the third stage AND gate is an AND gate, the load of the third stage AND gate is another AND gate, the device delay of the third stage and gate in this case is obtained as first delay information by the timing analysis tool, and thereafter, and a second delay complementary path comprising a plurality of stages of AND gates is constructed again, and the load of the third stage of AND gates in the second delay complementary path is assumed to be expanded into 5 AND gates, obtaining the device delay of the third-level AND gate under the condition through a time sequence analysis tool, and repeating the operation to construct a plurality of delay complementary paths under different conditions, and obtaining corresponding delay information, and storing all delay information related to the AND gate in a preset table to obtain a load delay table of the AND gate. Similarly, a load delay table of devices such as an inverter, an adder, a not gate, and the like can be obtained, which is not described in detail in the embodiments of the present application.

And after determining the devices required to be added for the delayed supplementing operation of the path to be supplemented and obtaining the load delay table of the devices, taking the load delay table as a target delay table. And then calculating a delay difference value between the original path delay of the path to be supplemented and a preset standard range, selecting target delay information which is closest to or even equal to the delay difference value from a target delay table, determining a target delay supplementary path corresponding to the target delay information, and adding the target delay supplementary path to the path to be added obtained by copying the path to be supplemented so as to obtain a new target key path corresponding to the path to be supplemented, wherein the path delay meets 80% of the clock cycle < the path delay < 100% of the clock cycle. In addition, it should be noted that, in the embodiment of the present application, a target delay complementary path is added to a path to be added obtained by copying a path to be supplemented, so as to obtain a new target critical path corresponding to the path to be supplemented, that is, a process of generating a corresponding circuit netlist.

In order to improve the execution efficiency of the chip operation frequency obtaining method, in the embodiment of the present application, when the path to be supplemented is copied, an incomplete copying mode may be adopted. For example, in the path 1 to be supplemented, a plurality of loads, L1, L2, and L3 … …, are connected to the output port Z of the and gate to be copied, and if an incomplete copying method is adopted, the loads are not completely copied, but quantized to obtain a delay value, and assuming that the delay value is 15 and the load quantization of one inverter is 3, then 5 inverters are connected to the output port Z of the and gate to be copied, which is equivalent to the equivalent loads L1, L2, and L3 … …. The incomplete replication method may be specifically understood that, because the load quantization given by the timing analysis tool is often pessimistic, if the original load quantization is 15, the original load quantization may be multiplied by a coefficient smaller than 1, for example, 0.85, to obtain the actually required load quantization: 12.75, when the path 1 to be complemented is copied, the output port Z of the and gate to be copied can be directly connected with 4 inverters. In addition, when the path to be supplemented is copied, the invalid port of the device in the path to be supplemented can be deleted, that is, the port which is not connected with the load is deleted, so that the reliability of the chip operation frequency obtaining method is improved.

After the final multiple target critical paths are obtained through steps S001 and S002, a corresponding normal distribution table may be generated according to the final multiple target critical paths to characterize the final path delay distribution of the multiple target critical paths, and determine whether the target critical path proportion of the path delay distribution in the delay median effective interval exceeds a preset proportion value, if the target critical path proportion of the path delay distribution in the effective delay interval exceeds the preset proportion value, the final multiple target critical paths are characterized to have availability, and if the target critical path proportion of the path delay distribution in the delay median effective interval does not exceed the preset proportion value, a relevant policy in the execution process of step S002 may be adjusted, for example, an obtaining manner of the load delay table, and step S002 is re-executed. In addition, in this embodiment of the present application, the effective delay interval may be (X-Y, X + Y), where X is a median of the path delay in the final multiple target critical paths, and Y is a preset delay floating value, which may be adjusted according to an actual design requirement of the target chip, and this embodiment of the present application does not specifically limit this.

In summary, the chip operation frequency obtaining method provided in the embodiment of the present application can obtain, for each target critical path in a plurality of target critical paths included in a target chip, a single frequency value characterization parameter of the target critical path according to a signal count value corresponding to the target critical path, where the signal count value corresponding to the target critical path can be obtained through a delay time calculation circuit, and then obtain an overall operation frequency of the target chip according to the single frequency value characterization parameter of each target critical path in the plurality of target critical paths. The delay calculation circuit is designed with low difficulty, so that the difficulty of obtaining the overall operating frequency of the target chip can be reduced, and the chip operating frequency obtaining method provided by the embodiment of the application can rapidly obtain the overall operating frequency of the target chip.

The third embodiment:

based on the same inventive concept as the chip operation frequency obtaining method provided in the second embodiment, the embodiment of the present application further provides a chip operation frequency obtaining apparatus 200. Referring to fig. 7, the apparatus 200 for acquiring a chip operating frequency according to an embodiment of the present disclosure includes a count value acquiring module 210, a parameter calculating module 220, and a frequency calculating module 230.

The count value obtaining module 210 is configured to obtain a plurality of signal count values obtained by a delay calculating circuit, where the delay calculating circuit includes a traveling wave counter and a plurality of oscillation signal generating modules, the plurality of oscillation signal generating modules are configured to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, and for each signal count value in the plurality of signal count values, the signal count value is obtained by the traveling wave counter counting oscillation signals generated by the oscillation signal generating modules under a delay action of the target critical paths connected correspondingly.

The parameter calculation module 220 is configured to, for each target critical path in the multiple target critical paths, obtain a single frequency value characterization parameter of the target critical path according to a signal count value corresponding to the target critical path.

The frequency calculation module 230 is configured to obtain an overall operating frequency of the target chip according to a single frequency value characterization parameter of each of the plurality of target critical paths.

In this embodiment, the parameter calculating module 220 may include a window length obtaining unit and a single frequency value characterizing parameter calculating unit.

And the window length acquisition unit is used for acquiring the counting time window period length of the travelling wave counter in the delay calculation circuit.

And the single frequency value representation parameter calculation unit is used for substituting the signal count value and the counting time window period length corresponding to the target critical path into a preset single frequency value representation parameter calculation formula, and taking a calculation result output by the single frequency value representation parameter calculation formula as a single frequency value representation parameter of the target critical path.

In the embodiment of the present application, the calculation formula of the single-term frequency value characterization parameter may be:

wherein, CPO _ normal [ i ]]Characterizing parameters for the univocal frequency value of the target critical path, CPO_iAnd N is the period length of a counting time window.

In the embodiment of the present application, the frequency calculation module 230 may include a first overall operating frequency calculation unit and a second overall operating frequency calculation unit.

And the first integral operation frequency calculation unit is used for calculating the median and the standard deviation of a plurality of single frequency value representation parameters corresponding to a plurality of target critical paths.

And the second overall operating frequency calculating unit is used for obtaining the overall operating frequency of the target chip according to the median and the standard deviation.

In this embodiment, the frequency calculation module 230 further includes a normalization processing unit.

And the normalization processing unit is used for performing normalization processing on the single frequency value representation parameter of each target key path in the plurality of target key paths.

The apparatus 200 for obtaining the operating frequency of the chip according to the embodiment of the present application may further include a target critical path selecting module.

And the target critical path selecting module is used for selecting a plurality of target critical paths from a plurality of paths included in the target chip.

In this embodiment, the target critical path selecting module may include a path feature obtaining unit, a first to-be-selected path determining unit, and a target critical path selecting unit.

The path feature acquiring unit is used for acquiring the path feature of each path in a plurality of paths included in the target chip.

The first path determining unit to be selected is used for determining paths to be deleted, which do not meet the preset selection rule, in the multiple paths according to the path characteristics of each path in the multiple paths, so that the other multiple paths except the paths to be deleted in the multiple paths are used as the multiple paths to be selected.

And the target key path selecting unit is used for selecting a plurality of target key paths from the plurality of paths to be selected.

The path characteristics may include a plurality of pieces of characteristic information, the preset selection rule includes a plurality of sub-selection rules, and each piece of characteristic information in the plurality of pieces of characteristic information corresponds to one sub-selection rule in the plurality of sub-selection rules. Based on this, in the embodiment of the present application, the target critical path selecting unit may include a preset quantity value obtaining subunit, a first to-be-selected feature path selecting subunit, and a first target critical path selecting subunit.

And the preset quantity value acquisition subunit is used for acquiring a plurality of preset quantity values which correspond to the plurality of pieces of characteristic information one by one.

And the first to-be-selected feature path selection subunit is used for determining a preset quantity value corresponding to the feature information as a target quantity for each piece of feature information in the plurality of pieces of feature information, and selecting a target quantity of first to-be-selected feature paths with the maximum quantity value from the plurality of pieces of to-be-selected feature paths according to a sub-selection rule corresponding to the feature information.

And the target key path selecting subunit is configured to, when the plurality of pieces of feature information are all the corresponding target number pieces of first to-be-selected feature paths, use the target number pieces of first to-be-selected feature paths corresponding to each piece of first feature information in the plurality of pieces of feature information together as the plurality of target key paths when the first target feature information of the similar plurality of first to-be-selected feature paths does not exist.

In this embodiment, the target critical path selecting unit may further include a second candidate feature path selecting subunit, a third candidate feature path selecting subunit, and a second target critical path selecting subunit.

And the second candidate characteristic path selecting subunit is configured to, when the plurality of pieces of characteristic information include second target characteristic information of a plurality of similar first candidate characteristic paths among corresponding target quantity first candidate characteristic paths, for each piece of second target characteristic information of the plurality of pieces of characteristic information, reserve one first candidate characteristic path among the plurality of similar first candidate characteristic paths corresponding to the second target characteristic information, delete other first candidate characteristic paths among the plurality of similar first candidate characteristic paths, obtain at least one remaining first candidate characteristic path, and record a quantity value of the deleted first candidate characteristic path as the quantity to be supplemented.

And the third candidate characteristic path selecting subunit is used for selecting, according to a sub-selection rule corresponding to the second target characteristic information, to-be-supplemented number of second candidate characteristic paths which have the maximum metric value and are not selected from the plurality of candidate paths for each piece of second target characteristic information in the plurality of pieces of characteristic information, and taking the second candidate characteristic paths as the number of target number of third candidate characteristic paths corresponding to the second target characteristic information together with at least one remaining first candidate characteristic path corresponding to the second target characteristic information.

And the second target key path selecting subunit is used for taking a target number of first to-be-selected feature paths corresponding to each piece of first target feature information in the plurality of pieces of feature information and a target number of third to-be-selected feature paths corresponding to each piece of second target feature information in the plurality of pieces of feature information as the plurality of target key paths together.

In this embodiment, the target critical path selecting unit may further include a preset selecting rule updating unit and a second candidate path determining unit.

And the preset selection rule updating unit is used for updating the preset selection rule to obtain a secondary selection rule if the second candidate characteristic paths which have the maximum metric value and are not selected and are to be supplemented cannot be selected according to the sub-selection rule corresponding to the second target characteristic information aiming at any second target characteristic information in the plurality of pieces of characteristic information.

And the second candidate path determining unit is used for determining paths to be deleted, which do not meet the secondary selection rule, in the multiple paths according to the path characteristics of each path in the multiple paths, so that the multiple paths except the paths to be deleted in the multiple paths are used as the multiple paths to be selected, and the step of selecting the multiple target key paths from the multiple paths to be selected is executed again.

The chip operating frequency acquisition device provided by the embodiment of the application can further comprise a time-delay supplementary operation module.

And the time delay supplement operation module is used for performing time delay supplement operation on the target key path aiming at each target key path in the plurality of target key paths, if the path delay of the target key path exceeds a preset standard range, so that the path delay of the target key path is within the preset standard range.

Since the chip operating frequency obtaining apparatus 200 provided in the embodiment of the present application is implemented based on the same inventive concept as the chip operating frequency obtaining method provided in the second embodiment, specific descriptions of each software module in the chip operating frequency obtaining apparatus 200 may refer to the related descriptions of the corresponding steps in the second embodiment, which are not described herein again.

The fourth embodiment:

the embodiment of the present application further provides an electronic device, which includes a controller and a memory, where the memory stores a computer program, and the controller is configured to execute the computer program to implement the method for obtaining the operating frequency of the chip provided in the second embodiment.

In this embodiment of the application, the electronic device may be a terminal device, for example, a computer, a Personal Digital Assistant (PAD), and the electronic device may also be a server, which is not limited in this embodiment of the application.

Structurally, an electronic device may include a processor and a memory.

The processor and the memory are electrically connected, directly or indirectly, to enable data transfer or interaction, e.g., the components may be electrically connected to each other via one or more communication buses or signal lines. The chip operation frequency acquisition device comprises at least one software module which can be stored in a memory in the form of software or Firmware (Firmware). The processor is used for executing executable modules stored in the memory, such as software functional modules and computer programs included in the chip operating frequency acquisition device, so as to realize the chip operating frequency acquisition method.

The processor may execute the computer program upon receiving the execution instruction. The processor may be an integrated circuit chip having signal processing capabilities. The Processor may also be a general-purpose Processor, for example, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a discrete gate or transistor logic device, a discrete hardware component, which may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application, and furthermore, the general-purpose Processor may be a microprocessor or any conventional Processor.

The Memory may be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is used for storing a program, and the processor executes the program after receiving the execution instruction.

Fifth embodiment:

an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed, the method for obtaining a chip operating frequency according to the second embodiment is implemented, which may be specifically referred to as the second embodiment, and details of the method are not repeated here.

To sum up, the delay calculating circuit provided in the embodiment of the present application includes a selection control module, a traveling wave counter, and a plurality of oscillation signal generating modules, where the plurality of oscillation signal generating modules are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, each oscillation signal generating module is used to generate an oscillation signal under a delay action of the corresponding target critical path, the selection control module is used to select an oscillation signal generated by each oscillation signal generating module of the plurality of oscillation signal generating modules and send the selected oscillation signal to the traveling wave counter, the traveling wave counter is used to count each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generating module within a target counting duration, the signal count value is used for representing the path delay of the target critical path corresponding to the oscillation signal generation module. Since the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, the design difficulty of the delay calculation circuit is low, so that the difficulty of obtaining the overall operating frequency of the target chip is reduced, and the efficiency of obtaining the overall operating frequency of the target chip is improved.

Further, the chip operation frequency obtaining device, the electronic device and the computer readable storage medium provided by the present application have the same beneficial effects as the above chip operation frequency obtaining method, and are not described herein again.

In the several embodiments provided in the examples of the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, the functional modules in each embodiment of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

Further, the functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in each embodiment of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

It is further noted that, herein, relational terms such as "first," "second," "third," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A delay calculating circuit is characterized by comprising a selection control module, a traveling wave counter and a plurality of oscillation signal generating modules, wherein the oscillation signal generating modules are used for being in one-to-one correspondence connection with a plurality of target critical paths included in a target chip, and the plurality of target critical paths are a plurality of critical paths selected from the plurality of paths included in the target chip;

each oscillation signal generation module is used for generating an oscillation signal under the time delay action of a corresponding target critical path;

the traveling wave counter is configured to count each received oscillation signal to obtain a signal count value of the oscillation signal generated by each oscillation signal generation module in the plurality of oscillation signal generation modules within a target counting duration, where the signal count value is used to characterize a path delay of a target critical path corresponding to the oscillation signal generation module.

2. The delay calculation circuit of claim 1, wherein each of the plurality of oscillation signal generation blocks comprises a first selector, an inverter, and a first controller;

3. The delay calculation circuit of claim 2, wherein the oscillation signal generation module further comprises a first flip-flop;

the clock control end of the first trigger is connected to a system clock, the input end of the first trigger is connected to a start indication signal, and the output end of the first trigger is connected to the first input end of the first selector and used for outputting the initial signal value.

4. The delay calculation circuit of claim 1, wherein the selection control module comprises a second selector and a second controller;

the second selector comprises a plurality of input ends, the plurality of input ends of the second selector are connected with the output ends of the plurality of oscillation signal generating modules in a one-to-one correspondence manner, and the output end of the second selector is used as the output end of the selection control module;

5. The delay calculating circuit of claim 1, wherein the ripple counter comprises a count controller and a plurality of second flip-flops, the plurality of second flip-flops are connected in sequence, and a clock control terminal of a first flip-flop of the plurality of second flip-flops is connected to the output terminal of the selection control module through the count controller, and an output terminal of a last flip-flop of the plurality of second flip-flops serves as a high-order output terminal of the ripple counter.

6. The delay calculation circuit of claim 5, wherein for any two adjacent ones of the plurality of second flip-flops, the output of a preceding second flip-flop is connected to the clocked terminal of a succeeding second flip-flop, and wherein for each of the plurality of second flip-flops, the inverted output of the second flip-flop is connected to the input of the second flip-flop.

7. The delay calculation circuit of claim 5, wherein the count controller comprises a counter and an AND gate;

and the second input end of the AND gate is used as the input end of the traveling wave counter and connected with the output end of the selection control module, and the output end of the AND gate is connected with the clock control end of the primary trigger.

8. A method for acquiring a chip operating frequency is characterized by comprising the following steps:

the method comprises the steps of obtaining a plurality of signal count values obtained through a delay calculation circuit, wherein the delay calculation circuit comprises a travelling wave counter and a plurality of oscillation signal generation modules, the oscillation signal generation modules are used for being in one-to-one correspondence connection with a plurality of target key paths included in a target chip, the target key paths are key paths selected from the plurality of paths included in the target chip, and for each signal count value in the signal count values, the signal count value is obtained by counting oscillation signals generated by the oscillation signal generation modules under the delay action of the target key paths correspondingly connected through the travelling wave counter;

aiming at each target critical path in the plurality of target critical paths, acquiring a single frequency value representation parameter of the target critical path according to a signal count value corresponding to the target critical path;

and obtaining the integral operating frequency of the target chip according to the single frequency value characterization parameter of each target critical path in the plurality of target critical paths.

9. The method for obtaining the operating frequency of the chip according to claim 8, wherein the obtaining a single frequency value characterizing parameter of the target critical path according to the signal count value corresponding to the target critical path includes:

acquiring the period length of a counting time window of a travelling wave counter in the delay calculation circuit;

and substituting the signal count value corresponding to the target critical path and the period length of the counting time window into a preset single frequency value representation parameter calculation formula, and taking a calculation result output by the single frequency value representation parameter calculation formula as a single frequency value representation parameter of the target critical path.

10. The method for obtaining the operating frequency of the chip according to claim 9, wherein the calculation formula of the characteristic parameter of the single-term frequency value is as follows:

wherein, CPO _ normal [ i ]]Characterizing a parameter, CPO, for the univocal frequency value of the target critical path_iAnd N is the cycle length of the counting time window.

11. The method for obtaining the operating frequency of the chip according to claim 8, wherein the obtaining the overall operating frequency of the target chip according to the single frequency value characterizing parameter of each target critical path in the plurality of target critical paths includes:

calculating median and standard deviation of a plurality of single frequency value representation parameters corresponding to the plurality of target critical paths;

12. The method of claim 11, wherein before calculating the median and standard deviation of the single frequency value characterization parameters corresponding to the target critical paths, the obtaining the overall operating frequency of the target chip according to the single frequency value characterization parameter of each target critical path in the target critical paths further comprises:

13. The method for obtaining the chip operating frequency according to claim 8, wherein before obtaining the single frequency value characterizing parameter of the target critical path according to the signal count value corresponding to the target critical path for each of the plurality of target critical paths, the method for obtaining the chip operating frequency further comprises:

and selecting the plurality of target critical paths from the plurality of paths included in the target chip.

14. The method for obtaining the operating frequency of the chip according to claim 13, wherein the selecting the plurality of target critical paths from the plurality of paths included in the target chip includes:

obtaining path characteristics of each path in a plurality of paths included in the target chip;

determining a path to be deleted which does not meet a preset selection rule in the plurality of paths according to the path characteristics of each path in the plurality of paths, so as to take other paths except the path to be deleted in the plurality of paths as a plurality of paths to be selected;

and selecting the target key paths from the candidate paths.

15. The method for obtaining the chip operating frequency according to claim 14, wherein the path characteristics include a plurality of pieces of characteristic information, the preset selection rule includes a plurality of sub-selection rules, each piece of characteristic information in the plurality of pieces of characteristic information corresponds to one sub-selection rule in the plurality of sub-selection rules, and the selecting the plurality of target critical paths from the plurality of paths to be selected includes:

acquiring a plurality of preset quantity values corresponding to the characteristic information one by one;

and if the plurality of pieces of feature information are the first target feature information of the plurality of similar first to-be-selected feature paths which do not exist in the corresponding target quantity of first to-be-selected feature paths, taking the target quantity of first to-be-selected feature paths corresponding to each piece of first feature information in the plurality of pieces of feature information as the plurality of target key paths together.

16. The method for obtaining the chip operating frequency according to claim 15, wherein the determining, for each piece of feature information in the plurality of pieces of feature information, a preset quantity value corresponding to the feature information as a target quantity, and selecting, according to a sub-selection rule corresponding to the feature information, a target quantity of first to-be-selected feature paths having a maximum quantity value from the plurality of to-be-selected paths, and then selecting the plurality of target critical paths from the plurality of to-be-selected paths, further comprises:

if the plurality of pieces of feature information include second target feature information of a plurality of similar first to-be-selected feature paths in a corresponding target number of first to-be-selected feature paths, for each piece of second target feature information in the plurality of pieces of feature information, reserving one first to-be-selected feature path in the plurality of similar first to-be-selected feature paths corresponding to the second target feature information, deleting other first to-be-selected feature paths in the plurality of similar first to-be-selected feature paths, obtaining at least one remaining first to-be-selected feature path, and recording a quantity value of the deleted first to-be-selected feature path as a to-be-supplemented number;

for each piece of second target characteristic information in the plurality of pieces of characteristic information, according to a sub-selection rule corresponding to the second target characteristic information, selecting a number of unselected second candidate characteristic paths which have the maximum metric value and are not selected from the plurality of candidate paths, and combining the remaining at least one first candidate characteristic path corresponding to the second target characteristic information to jointly serve as a number of target third candidate characteristic paths corresponding to the second target characteristic information;

and in the plurality of pieces of feature information, a target number of first to-be-selected feature paths corresponding to each piece of first target feature information and a target number of third to-be-selected feature paths corresponding to each piece of second target feature information are jointly used as the plurality of target key paths.

17. The method for obtaining the chip operating frequency according to claim 16, wherein the selecting, for each piece of second target feature information in the plurality of pieces of feature information, a to-be-supplemented number of second candidate feature paths that have a maximum metric value and are not selected from the plurality of candidate paths according to a sub-selection rule corresponding to the second target feature information, and the selecting, in combination with the remaining at least one first candidate feature path corresponding to the second target feature information, the plurality of target critical paths from the plurality of candidate paths before collectively serving as a target number of third candidate feature paths corresponding to the second target feature information, further comprises:

aiming at any second target characteristic information in the plurality of pieces of characteristic information, if the number of second to-be-selected characteristic paths which have the maximum metric value and are not selected and to be supplemented cannot be selected according to the sub-selection rule corresponding to the second target characteristic information, updating the preset selection rule to obtain a secondary selection rule;

and determining a path to be deleted which does not meet the secondary selection rule in the plurality of paths according to the path characteristics of each path in the plurality of paths, taking other paths except the path to be deleted in the plurality of paths as a plurality of paths to be selected, and re-executing the step of selecting the plurality of target key paths from the plurality of paths to be selected.

18. The method for obtaining the operating frequency of the chip according to claim 13, wherein after the plurality of target critical paths are selected from the plurality of paths included in the target chip, the method for obtaining the operating frequency of the chip further comprises:

and for each target critical path in the plurality of target critical paths, if the path delay of the target critical path exceeds a preset standard range, performing delay supplementary operation on the target critical path so as to enable the path delay of the target critical path to be within the preset standard range.

19. A chip operation frequency acquisition apparatus, comprising:

a count value obtaining module, configured to obtain a plurality of signal count values obtained by a delay calculating circuit, where the delay calculating circuit includes a traveling wave counter and a plurality of oscillation signal generating modules, the plurality of oscillation signal generating modules are used to be connected to a plurality of target critical paths included in a target chip in a one-to-one correspondence manner, the plurality of target critical paths are a plurality of critical paths selected from a plurality of paths included in the target chip, and for each signal count value in the plurality of signal count values, the signal count value is obtained by counting, by the traveling wave counter, an oscillation signal generated by the oscillation signal generating module under a delay action of the target critical path connected correspondingly;

the parameter calculation module is used for acquiring a single frequency value representation parameter of each target critical path in the plurality of target critical paths according to a signal count value corresponding to the target critical path;

and the frequency calculation module is used for obtaining the overall operating frequency of the target chip according to the single frequency value characterization parameter of each target critical path in the plurality of target critical paths.

20. An electronic device, comprising a controller and a memory, wherein the memory stores a computer program, and the controller is configured to execute the computer program to implement the chip operating frequency obtaining method according to any one of claims 8 to 18.

21. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed, the method for obtaining the operating frequency of the chip according to any one of claims 8 to 18 is implemented.