WO2016101099A9

WO2016101099A9 - Techniques for power management associated with processing received packets at a network device

Info

Publication number: WO2016101099A9
Application number: PCT/CN2014/094515
Authority: WO
Inventors: Danny Y. ZHOU; Mark D. GRAY; John J. BROWNE
Original assignee: Intel Corporation
Priority date: 2014-12-22
Filing date: 2014-12-22
Publication date: 2016-11-10
Also published as: KR102284467B1; EP3238403A1; JP6545802B2; CN107005531A; JP2018507457A; WO2016101099A1; KR20170097615A; EP3238403A4

Abstract

Examples may include techniques for power management associated with processing received packets at a NW device. Receive queues for network input/out (NW I/O) devices or network interface cards (NICs) may be monitored to determine activity levels of data plane development kit (DPDK) polling threads. Various power or performance management actions are taken based on information obtained from monitoring the receive queues.

Description

Techniques for Power Management Associated with Processing Received Packets at a Network Device

TECHNICAL FIELD

Examples described herein are generally related to network packet processing.

BACKGROUND

[Rectified under Rule 91, 15.01.2015]
A data plane development kit (DPDK) is set of software libraries and drivers that may be used to accelerate user space packet processing for network computing platforms based on processor architecture such as the

processor architecture. DPDK has been deployed in datacenter networks worldwide to support high performance network packet processing applications. These network packet processing applications may include, but are not limited to, firewall, virtual private network (VPN) , network address translation (NAT) , deep packet inspection (DPI) or load balancer applications. These firewall, VPN, NAT, DPI or load balancer applications, for example, may be implemented on a standard x86 server platform that may include, but is not limited to

Processors coupled to Intel 10 gigabit/40 gigabit (10G/40G) network interface cards (NICs) . Use of DPDK to support high performance network packet processing applications may replaceat least some expensive and less-flexible physical components of a network device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates anexample system.

FIG. 2 illustrates an example first logic flow.

FIG. 3 illustrates an example first process.

FIG. 4 illustrates an example second process.

FIG. 5 illustrates an example third process.

FIG. 6 illustrates an example block diagram for an apparatus.

FIG. 7 illustrates an examplesecondlogic flow.

FIG. 8 illustrates an example third logic flow.

FIG. 9 illustrates an exampleof a storage medium.

FIG. 10 illustrates an example computing platform.

DETAILED DESCRIPTION

[Rectified under Rule 91, 15.01.2015]
In some examples, implementation of DPDK for high performance packet processing applications may include deployment of poll mode drivers (PMDs) toconfigure and/or operate NW I/O devices such as Intel1G/10G/40G NICs. For these examples, deployment of the PMD may enable DPDK-based network applications to access the NW I/O device resources (e.g. receive (Rx) andtransmit (Tx) queues) at a highest or maximum processor/core frequency without triggering interrupts, in order to receive, process and transmi tpackets in a high performance and low latency fashion. However, in datacenter networks, awell-known phenomenon called "tidal effect" may occur. Tidal effect may result from significant changes innetwork traffic patterns occurring in different geographic areas over periods of time. Soduring a period of processing low or no network traffic, a thread of a DPDK-based application ( “DPDK polling thread” ) running on x86 processing cores may still be busy waiting (e.g. continuously polling forbut not processing network packets) . The waiting for network packets may waste a considerable amount of power as well as computational resources.

[Rectified under Rule 91, 15.01.2015]
Operating system (OS) power management subsystems or module smay provide a number of technologies (primarilyP-states, C-states and control in the OS kernel space) to adjust processor power during periods of either peak or low network traffic. In standard OSes (e.g. Linuxor

) , the OS power management modules may determine the appropriate processor voltage and/or frequency, operating point (P-state) and processor idle state (C-state) , respectively fora processor or cores to enter, by sampling CPU usage periodically. But this approach is not suitable for PMD-based packet processing applications having DPDK polling threads due to the OS power management module not being able to determine if the DPDK polling threads are really processing packets or busy waiting. The OS power management module’s inability to determine the operating state of DPDK polling threads may be problematic to determine appropriate power states for processors or cores supporting these DPDK polling threads to enter in order to save power in datacenter networks impacted by the "tidaleffect" . It is with respect to these challenges that the examples described herein are needed.

According to some first examples, techniques for power management associated with processing received packets at a NW I/O device may include monitoring received and available packet descriptors maintained at a receive queue for the NW I/O device over multiple polling iterations for a DPDK polling thread. These first examples may also include determining a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration and incrementing a trend count based on the level of fullness for the receive queue. These first examples may also include sending a performance indication to an OS power management module based on whether the trend count exceeds a tread count threshold. The performance indication may be capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.

According to some second examples, techniques for power management associated with processing received packets at the NW device may also include monitoring received and available packet descriptors maintained at the receive queue for the NW I/O device over multiple polling iterations for the DPDK polling thread. These second examples may also include determining a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration and incrementing an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold. These second examples may also include causing the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold. The second time period may be longer than the first time period.

FIG. 1 illustrates an example system 100. As shown in FIG. 1, in some examples, system 100 includes a NW I/O device 110 arranged to receive or transmit packets included in NW traffic 105. A pre-flow load balancer 120 may be capable of distributing packets to receive (Rx) queues 130-1 to 130-n, where “n” is any positive whole integer > 1. For these examples, Rx queues 130-1 to 130-n may be arranged to at least temporarily maintain received packets for processing by respective DPDK polling threads 140-1 to 140-n. Each DPDK polling thread 140- 1 to 140-n may be capable of executing at least portions of a network packet processing application including, but not limited to firewall, VPN, NAT, DPI or load balancer applications. Each DPDK polling thread 140-1 to 140-n may include respective poll mode drivers 142-1 to 142-n to enable access of Rx queues 130-1 to 130-n in a polling mode of operation, withoutinterrupts, toreceiveprocess or transmitpackets received in NW traffic 105.

According to some examples, as shown in FIG. 1, system 100 may also include DPDK power management components 150 arranged to operate in user space 101 and an OS power management module 160 arranged to operate in kernel space 102. As described in more detail below, DPDK power management components 150 may include logic and/or features capable of monitoring received and available packet descriptors maintained at Rx queues 130-1 to 130-n for processing by DPDK polling threads 140-1 to 140-n. The logic and/or features at DPDK power management components 150 may also monitor sleeping or idle times for DPDK polling threads 140-1 to 140-n.

In some examples, state algorithms 154 of DPDK power management components 150 may utilize monitored information to cause DPDK polling threads 140-1 to 140-n to be placed in temporary sleep states, send an interrupt turn on hintor message to NW I/O device 110 (via one-shot Rx interrupt on hint180) and cause a change from a polling mode to an interrupt mode of operation, or to enable library 152 to send C-state (sleep) or P-state (performance) hints or indications. For these examples, as shown in FIG. 1, the C-state or P-state hints may be sent to processor element (PE) idle 162 or PE frequency 164 at OS power management module 160. The elements of OS power management module 160 may then causechanges to either C-state (s) or P-state (s) of one or more PEs 172-1 to 172-n included in one or more processor (s) 170 based on received C-state or P-state hints. C-states or P-states may be changed or controlled according to one or more processor power management standards or specification such as Advanced Configuration and Power Interface Specification (ACPI) , Revision 5.1, published in July, 2014 by the Unified Extensible Firmware Interface Forum ( “the ACPI specification” ) .

According to some examples, processor (s) 170 may include a multicore processor and PEs 172-1 to 172-n may each be a core of the multicore processor and/or may be a virtual machine (VM) supported by one or more cores of the multicore processor. Also, for these examples, DPDK polling threads 140-1 to 140-n may be capable of being executed by PEs 172-1 to 172-n. Processor (s) 170 may include various types of commercially available x86 processors including, but not limited to,

and

processors；Intel

Core (2)

Core i3, Core i5, Core i7,

Xeon orXeon

processors.

[Rectified under Rule 91, 15.01.2015]
According to some examples, a newAPI (NAPI) may be an interupt mitigation technique for use in kernel space 102 (e.g., for a Linuxkernel) to support packet processing by DPDK polling threads 140-1 to 140-n. NAPI is typically designed to improve performance of high-speed networking by introducing a pollingmode capability for an OS andNICor NW I/O drivers. WithNAPI, aNW I/O driver can work in interrupt-driven mode by default and only switch to polling mode when the flow of incoming packets exceeds a certain threshold. NAPI allows for frequent mode switches, which may be well accepted for network terminal endpoints (e.g., server or personal computer) as these terminal endpoints may not have strict low latency and jitter requirements. Butcertain types of network devices (e.g., switch, router and L4-L7 network appliances) may operate within strict latency, jitter and packet loss requirements. For these types of network devices, frequent mode switching, servicing interrupts and waking up a suspended, paused or sleeping thread may be costly interms of processor resource and latency hits. These processor resource and latency hits may be unacceptable for network devices in such deployments as in adatacenter network.

[Rectified under Rule 91, 15.01.2015]
According to some examples, poll mode driver 142-1 to 142-n of DPDK polling threads 140-1 to 140-n may be designed or arranged to work in a polling mode by default. As described more below, when DPDK power management components 150 detect network traffic that is trending lower and lower, DPDK power management components 150 may cause DPDK polling threads 140-1 to 140-n to sleep for one or more periods of time and also may send hints to OS power management module 160. Based on the hints, OS power management module 160 maycause PEs 172-1 to 172-n to scale down processor frequencies or transition to idle or sleep states to save power. Also, when DPDK power management components 150 detect no traffic for a certain duration threshold, pollmode drivers 142-1 to 142-n may switch to an interrupt mode from the default polling mode. In this way, DPDK polling threads 140-1 mainly work in a polling mode environment to better satisfy performance requirements when processing packets and thus may avoid frequent mode switches.

[Rectified under Rule 91, 15.01.2015]
FIG. 2 illustrates an example first logic flow. As shown in FIG. 2, the example first logic flow includes logic flow 200. According to some examples, logic flow 200 may for power management associated with processing received packets for a NW device (e.g., located at a datacenter) . For these examples, at least some components of system 100 shown in FIG. 1 may be capable of implementing portions of logic flow 200. However, the example logic flow 200 is not limited to using components of system 100 shown or described in FIG. 1.

In some examples, as shown in FIG. 2, DPDK power management components may be initialized 202. For these examples, a DPDK polling thread (e.g., DPDK polling thread 140-1) may start continuous loop of polling packets from Rx queues for a NW I/O device (e.g., Rx queue 130-1). The loop may be continuous unless placed in a sleep or an interrupt is issued as described more below. For each polling iteration (e.g., every 1-2 microseconds (μs)) 204, a number of used and free packet descriptors maintained at the Rx queue may be obtained by DPDK power management components. If 0 packets have been received for a given polling iteration 206, the number of iterations for which 0 packets were received may be compared to consecutive number threshold 208 (e.g., 5 iterations). In some examples, the logic flow moves back to 204 if the consecutive number threshold has not been exceeded.

According to some examples, based on the number of iterations for which 0 packets were received an ‘idle’ count may be incremented by 1 at 210. A determination of whether the ‘idle’ count is below or less than THRESHOLD_1 is made at 212. At 214, if the ‘idle’ count is less than THRESHOLD_1, the DPDK polling thread may be placed in sleep for a short period (e.g., several μs) by the DPDK power management components. At 216 if the ‘idle’ count is less than THRESHOLD_2, the DPDK polling thread may be placed in sleep for a relatively long period (e.g., dozens of μs).

In some examples, the short sleep period may be a short, several μs sleep period to reduce power consumption compared to a continuous spin loop. Thus causing the DPDK polling thread to avoid costly context switches during times of a not yet identifiable traffic trend. The relatively long sleep period may be such that a lower traffic trend has been identified. In this case the DPDK power management components may cause the DPDK polling thread to sleep for the longer period and may also send a long sleep indication or C-state hint to an OS power management module. The OS power management module may then cause a PE supporting the DPDK polling thread to enter an ACPI C1 power state. This C1 power state may still enable the PE to quickly power to a C0 power state if new NW traffic arrives.Also, if new NW traffic does arrive, the ‘idle’ count is reset to a count of 0.

According to some examples, THRESHOLD_1 may be several times lower compared to THRESHOLD_2 to cause the DPDK polling thread to sleep after relatively short periods of 0 packets at the Rx queue. However, if the ‘idle’ count exceeds THRESHOLD_2, a one-shot Rx interrupt may be enabled 220. Once there is incoming packet received by the NW I/O, the one-shot Rx interrupt istriggered 222 that may cause the paused DPDK polling thread to switch back to polling mode from interrupt mode. The idle count exceeding THRESHOLD_2 may indicate a slow or no network traffic period. Also, pausing of the DPDK polling thread may enable the OS power management module to cause the PE executing the DPDK polling thread to be placed in deeper C-states of lower power usage than a C1 state. In effect, the DPDK polling thread may now operate in an interrupt mode that switches back to a polling mode responsive to receiving network traffic again.

In some examples, fullness levels of the Rx queue may be determined if packets were received in the Rx queue. For example, if the Rx queue is near empty (e.g., 25％ to 50％ full) 224, a ‘trend’ count may be incremented by a small number 226. If the RX queue is half full (e.g., 51％ to 75％) 234, the trend’ count may be incremented by a large number 236. Also, if the ‘trend’ count exceeds a trend count threshold at 228, the DPDK power management components may send a performance indication or P-state hint to the OS power management module. The performance indication may cause the OS power management module to increase operating frequencies 230 or raise an ACPI P-state for the PE executing the DPDP polling thread. The ‘trend’ count may be set such that gradual increases in network traffic can be detected and P-states for PEs may be gradually increased to balance power saving with performance while processing received packets 232.

According to some examples, if the Rx queue is near full (e.g., > 76％full) 238, a number of consecutive polling iterations for which the Rx queue was near full may be compared to a consecutive threshold (e.g., 5 polling iterations) at 240. For these examples, the DPDK power management components may send a high performance indication or high P-state hint to the OS power management module if the consecutive threshold is exceeded. The high performance indication may cause the OS power management module to scale up operating frequencies to highest frequency 242 or raise an ACPI P-state for the PE executing the DPDK polling thread to a highest performance P-state. Scaling up to the highest performance P-state may allow the OS power management module to quickly react to high network traffic loads and thus switch the PE executing the DPDK polling thread from a balance of power saving and performance to a purely performance-based operating state while processing received packets 232.

In some examples, the DPDK power management components periodically monitor an amount of time the DPDK polling thread is sleeping. For these examples, the DPDK power management components may initialize a periodical timer at 244 that may start a timer intervalfor which monitoring sleep for the DPDK polling thread may occur. Following expiration of the timer at 246, the DPDK power management components may determine whether the DPDK polling thread was placed in sleep for greater than 25％of the polling iterations. As mentioned previously, the DPDK polling thread may have been placed in sleep for various times based on whether or not an ‘idle’ count was less than THRESHOLD_1 or THRESHOLD_2. If the DPDK polling was found to be in sleep for greater than 25％then the DPDK power management components may send a performance indication or P-state hint to the OS power management module at 252. The performance indication may result in OS power management module causing the PE executing the DPDK polling thread to have a lowered or decreased operating frequency. In other words, the ACPI P-state for the PE may be lowered to a lower performance P-state.

According to some examples, if the DPDK polling thread was not in sleep for greater than 25％of the polling iterations, the DPDK power management components may determine whether or not an average packet-per-iteration for packets received during the time interval is less than a threshold of expected average packet-per-interaction at 250. If below the threshold, the DPDK power management components may send a performance indication or P-state hint to the OS power management module at 252. Having the PE lower its P-state responsive to greater than 25％sleep or less packets received than expected may be a way to ramp down performance states to save power based on monitored information that indicates network traffic or at least processing of packets from network traffic is decreasing.

FIG. 3illustrates an example first process 300. As shown in FIG. 3, the first process includes process 300. According to some examples, process 300 may demonstrate how different elements of system 100 may implement portions of logic flow 200 described above for FIG. 2. In particular those portions related to sleep, idle or interrupt actions taken by DPDK power management components (PMCs) . For these examples, at least some components of system 100 shown in FIG. 1may be related to process 300. However, the example process 300 is not limited to implementations using components of system 100 shown or described in FIG. 1.

Starting at process 3.1 (Rx Packets) , packets may be received by NW I/O device 110 and placed at least temporarily at Rx queues 130.

Moving to process 3.2 (Poll and Process) , DPDK polling threads 140 may be capable of polling Rx queues 130 and process packets as they are received at Rx queues 130.

Moving to process 3.3 (Monitor Rx’ d and Avail. Packet Descriptors) , DPDK power management components 150 may include logic and/or features to monitor received and available packet descriptors maintained at Rx queues 130 over multiple polling iterations for DPDK polling threads 140.

Moving to process 3.4 (0 Packets for > Consecutive Threshold) , DPDK power management components 150 may include logic and/or features to determine if 0 packets have been received for a number of consecutive polling iterations that exceeds a consecutive threshold (e.g., 5 polling iterations) .

Moving to process 3.5 (Increment Idle Count) , DPDK power management components 150 may include logic and/or features to increment an idle count by a count of 1 if the consecutive threshold is exceeded.

Moving to process 3.6A (Short Period Sleep) , DPDK power management components 150 may include logic and/or features to place DPDK polling threads 140 in sleep for a short period (e.g., a couple μs) if the increment idle count is found to be less than a first idle count threshold (e.g., THRESHOLD_1) . The process may then come to an end.

Moving to a first alternative at process 3.6B (Long Period Sleep) , DPDK power management components 150 may include logic and/or features to place DPDK polling threads 140 in sleep for a relatively long sleep period (e.g., several dozenμs) if the increment idle count is found to be greater than the first idle count threshold but less than a second idle count threshold (e.g., THRESHOLD_2) .

Moving to process 3.7B (Long Sleep Indication) , DPDK power management components 150 may include logic and/or features to send a long sleep indication to OS power management module (PMM) 160 to indicate that DPDK polling threads 140 were placed in sleep for the long sleep period.

Moving to process 3.8B (Sleep Mode for Long Period), the OS power management module 160 may cause PE(s) 172 to be placed in a sleep mode for up to the long sleep period. In some examples, the sleep mode may include an ACPI C1 power state. The process may then come to an end for this first alternative.

Moving to a second alternative at process 3.6C (Turn On One-Shot Rx Interrupt), DPDK power management components 150 may include logic and/or features to send an interrupt turn on hintor message to NW I/O device 110 based on the idle count exceeding the second idle count threshold (e.g., THRESHOLD_2).

Moving to process 3.7C (Switch to Interrupt Mode), poll mode driver 142 may switch from working with NW I/O device 110 in a poll mode to an interrupt mode. This mode switch may also cause DPDK polling threads 140 to pause.

Moving to process 3.8C (Rx Packets), network traffic 105 may now include packets for processing by DPDK threads 140.

Moving to process 3.9C (Switch to Poll Mode), poll mode driver 142 may switch back to working with NW I/O device 110 in the poll mode and the process may then come to an end for this second alternative.

FIG. 4 illustrates an example second process 400. As shown in FIG. 4, the second process includes process 400. Similar to process 300, process 400 may demonstrate how different elements of system 100 may implement portions of logic flow 200 described above for FIG. 2. In particular those portions related to monitoring sleep percentages for DPDK polling threads or average-packet-per-iteration to determine whether to lower a performance state for PE(s) 172. For these examples, at least some components of system 100 shown in FIG. 1 may be related to process 400. However, the example process 400 is not limited to implementations using components of system 100 shown or described in FIG. 1.

Starting at process 4.1 (Initialize Timer) , DPDK power management components 150 may include logic and/or features to initialize or initiate a timer having a timer interval. In some examples, the timer interval may be approximately 100 milliseconds (ms) .

Moving to process 4.2 (Monitor Activity to Determine Sleep ％) , DPDK power management components 150 may include logic and/or features to monitor how often DPDK polling threads 140 have been placed in sleep.

Moving to process 4.3 (Timer Expires) , the time expires after the timer interval.

Moving to process 4.4A (Performance Indication (sleep ％) ) , DPDK power management components 150 may include logic and/or features to determine whether DPDK polling threads 140 were sleeping a percentage of a time above a percentage threshold during the timer interval. In some examples, DPDK power management components 150 may send a performance indication to OS power management module 160 if the sleeping percentage for DPDK polling threads 140 was above or exceeded the percentage threshold (e.g., > 25％) .

Moving to process 4.5A (Lower Performance State) , OS power management module 160 may cause PE (s) 172 to lower their performance state or P-state. The process may then come to an end.

Moving to a first alternative at process 4.4B (Performance Indication (packet ave. )) , DPDK power management components 150 may include logic and/or features to determine whether an average packet-per-iteration is greater or less than a packet average threshold. In some examples, DPDK power management components 150 may senda performance indication to OS power management module 160 if the average packet-per-iteration was below the packet average threshold.

Moving to process 4.5B (Lower Performance State) , OS power management module 160 may cause PE (s) 172 to lower their performance state or P-state. The process may then come to an end for this first alternative.

FIG. 5 illustrates an example third process 500. As shown in FIG. 5, the third process includes process 500. According to some examples, process 500 may demonstrate how different elements of system 100 may implement portions of logic flow 200 described above for FIG. 2. In particular, those portions related to monitoring Rx queue fullness to determine if or when to raise performance for PE (s) . For these examples, at least some components of system 100 shown in FIG. 1 may be related to process 500. However, the example process 500 is not limited to implementations using components of system 100 shown or described in FIG. 1.

Starting at process 5.1 (Rx Packets) , packets may be received by NW I/O device 110 and placed at least temporarily at Rx queues 130.

Moving to process 5.2 (Poll and Process) , DPDK polling threads 140 may be capable of polling Rx queues 130 and process packets as they are received at Rx queues 130.

Moving to process 5.3 (Monitor Rx’ d and Avail. Packet Descriptors) , DPDK power management components 150 may include logic and/or features to monitor received and available packet descriptors maintained at Rx queues 130 over multiple polling iterations for DPDK polling threads 140.

Moving to process 5.4 (Determine Rx Queue Fullness) , DPDK power management components 150 may include logic and/or features to determine a fullness of Rx queues 130 based on available packet descriptors maintained at Rx queues 130 following each polling iteration.

Moving to process 5.5 (Increment Trend Count), DPDK power management components 150 may include logic and/or features to either increment a trend count by a single count or a large count based on the determined level of fullness of Rx queues 130 as described above for logic flow 200 shown in FIG. 2.

Moving to process 5.6A (Performance Indication), DPDK power management components 150 may include logic and/or features to send a performance indication to OS power management module 160 based on the incremented tread count exceeding a tread count threshold.

Moving to process 5.7A (Incr. Op. Freq. a Step Up), OS power management module 160 may increase a performance state or P-State of PE(s) 172. In some examples, the performance state for PE(s) 172 may be raised a step up or a single P-State which may cause the operating frequency of PE(s) 172 to be increased when executing DPDK polling threads 140. The process may then come to an end.

Moving to a first alternative at process 5.6B (High Performance Indication), DPDK power management components 150 may include logic and/or features to send a high performance indication to OS power management module 160 responsive to a consecutive number of polling iterations for which Rx queues 130 were determined to be near full (e.g., > 75％) .

Moving to process 5.7B (Incr. Op. Freq. to Max.), OS power management module 160 may increase a performance state or P-State of PE(s) 172 to a highest or maximum P-State. In some examples, raising PE(s) 172 to the highest or maximum P-Statue results in PE(s) 172 being raised to their highest or maximum operating frequency when executing DPDK polling threads 140. The process may then come to an end for this first alternative.

FIG. 6illustrates an exampleblock diagram for apparatus600. Although apparatus 600 shown in FIG. 6 has a limited number of elements in a certain topology, it may be appreciated that the apparatus 600 may include more or less elements in alternate topologies as desired for a given implementation.

According to some examples, apparatus 600 may be supported bycircuitry 620 maintained at or a computing platform or network device that may be deployed in a datacenter. Circuitry 620 may be arranged to execute one or more software or firmware implemented modules or components622-a. It is worthy to note that “a” and “b” and “c” and similar designators as used herein are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value for a ＝6, then a complete set of softwareor firmware forcomponents622-a may include components622-1, 622-2, 622-3, 622-4, 622-5 or 622-6. The examples presented are not limited in this context and the different variables used throughout may represent the same or different integer values. Also, these “components” may be software/firmware stored in computer-readable media, and although the components are shown in FIG. 6as discrete boxes, this does notlimit these components to storage in distinct computer-readable media components (e.g., a separate memory, etc. ) .

According to some examples, circuitry 620 may include a processor, processor circuit or processor circuitry. Circuitry620may be any of various commercially available processors, including without limitation an

and

processors； Intel

Core (2)

Core i3, Core i5, Core i7,

Xeon orXeon

processors. According to some examples circuitry 620 may also include an application specific integrated circuit (ASIC) and at least some components622-amay be implemented as hardware elements of the ASIC.

In some examples, apparatus 600 may include aqueue component622-1. Queuecomponent622-1 may be executed by circuitry 620to monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The received and available packet descriptors may be included in rx’ d&avail pkt descriptors 610 and may be maintain by queue component 622-1 in Rx queue information 623-a (e.g., in a data structure such as a lookup table (LUT)) . Queue module 622-1 may be capable of determining a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration. The level of fullness may also be maintained in Rx queue information 623-a.

In some examples, queue component 622-1 may also determine a number of packets received at the receive queue for each polling iteration based on the information included in Rx queue information 623-a.

According to some examples, apparatus 600 may also include an increment component622-2. Increment component622-2 may be executed by circuitry 620 to increment a trend count based on the level of fullness for the receive queue following each polling iteration. For these examples, the trend count may be maintained by increment component 622-2 in trend count 624-b (e.g., in a LUT) . Increment component 622-2 may also increment an idle count by at least a count of 1 if queue module 622-1 has determined that 0 packets were received for a consecutive number of polling iterations that exceeds a consecutive threshold. The idle count may be maintained by increment component 622-2 in idle count 625-c (e.g., in a LUT) .

In some examples, apparatus 600 may also include a performance component 622-3. Performancecomponent622-3 may be executed by circuitry 620to send a performance indication 640 to an OS power management module based on whether the trend count exceeds a tread count threshold. The performance indication 640 may be capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread. For these examples, the tread count threshold may be maintained by performance component 622-3 in trend count threshold 626-d (e.g., in a LUT) .

According to some examples, performance component 622-3 may send a high performance indication 645 to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full by queue component 622-1 exceeding a consecutive threshold. The high performance indication 645 may be capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state by causing an operating frequency of the processing element to be increased to a highest operating frequency. For these examples, the consecutive threshold may be maintained by performance component 622-3 in consecutive threshold 627-e (e.g., in a LUT) .

In some examples, apparatus 600 may also include a sleep component 622-4. Sleep component 622-4 may be executed by circuitry 620 to cause the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count incremented by increment component and maintained in idle count 625-c exceeds or is less than a first idle count threshold maintained by sleep component 622-4 in idle count thresholds 630-h (e.g., in a LUT) . For these examples, the second time period may be longer than the first time period. Sleep 615 may include indications or commands to cause the DPDK polling thread to sleep.

According to some examples, sleep component 622-4 may cause DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold and send a long sleep indication 650 to the OS power management module. Long sleep indication 650 may be capable of causing the OS power management module to cause the processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.

According to some examples, apparatus 600 may also include an interrupt control component 622-5. Interrupt control component 622-4 may be executed by circuitry 620 to send an message to the NW I/O device to enable one-shot Rx interrupt based on whether the idle count incremented by increment component 622-2 exceeds a second idle count threshold maintained by sleep component 622-5 with idle count thresholds 630-h. For these examples, the message may be included in one-shot Rx interrupt 635.

According to some examples, apparatus 600 may also include a timer component 622-6. Timer component 622-6 may be executed by circuitry 620 to initiate a timer having a timer interval maintained by timer component 622-6 in timer interval 632-j (e.g., in a LUT) .

In some examples, sleep component 622-4 may determine a percentage of iterations for which the DPKK polling thread was sleeping during the timer interval responsive to the timer initiated by timer component 622-6 expiring. The percentage may be maintained by sleep component 622-4 with sleep information 631-i. For these examples, performance component 622-3 may send performance indication 640 to the OS power management module based on whether the percentage is greater than a percentage threshold. Performance indication 640 may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element. The percentage threshold used for this determination may be maintained with percentage threshold 628-f (e.g., in a LUT) by performance component 622-3.

According to some examples, queue component 622-1 may determine an average packet-per-iteration for packets received at the receive queue during the time interval responsive to the timer initiated by timer component 622-6 expiring. The average packet-per-iteration determined by queue component 622-1 may be maintained with Rx queue information 623-a. For these examples, performance component 622-3 may send a performance indication 640 to the OS power management module based on whether the average packet-per-iteration is greater than a packet average threshold. Performance indication 640 may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element. The packet average threshold may be maintained by performance component 622-3 with average threshold 629-g (e.g., in a LUT) . [0078]Various components of apparatus 600 and a device, node or logical server implementing apparatus 600 may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

Included herein is a set of logic flows representative of example methodologies for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may, in accordance therewith, occur in a different order and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.

A logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow may be implemented by computer executable instructions stored on at least one non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. The embodiments are not limited in this context.

FIG. 7 illustrates an example second logic flow. As shown in FIG. 7, the example second logic flow includes logic flow 700. Logic flow 700 may be representative of some or all of the operations executed by one or more logic, features, or devices described herein, such as apparatus 600. More particularly, logic flow 700 may be implemented by at least queuecomponent622-1, increment component622-2 or performance component 622-3.

According to some examples, logic flow 700at block 702 may monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. For these examples, queue component 622-1may monitor the receive queue.

In some examples, logic flow 700at block 704 maydetermine a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration. For these examples, queue component 622-1 may determine the level of fullness.

According to some examples, logic flow 700 at block 706 may increment a trend count based on the level of fullness for the receive queue. For these examples, increment component 622-2 may increment the trend count.

Insome examples, logic flow 700 at block 708 may send a performance indication to an OS power management module based on whether the trend count exceeds a tread count threshold, the performance indication capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread. For these examples, performance component 622-3 may send the performance indication.

FIG. 8 illustrates an example third logic flow. As shown in FIG. 8, the example third logic flow includes logic flow 800. Logic flow 800 may be representative of some or all of the operations executed by one or more logic, features, or devices described herein, such as apparatus 600. More particularly, logic flow 800 may be implemented by at least queue component 622-1, increment component 622-2 or sleep component 622-4.

According to some examples, logic flow 800 at block 802 may monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. For these examples, queue component 622-1may monitor the receive queue.

In some examples, logic flow 800 at block 804 may determine a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration. For these examples, queue component 622-1 may determine the number of packets received at the receive queue.

According to some examples, logic flow 800 at block 806 may increment an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold. For these examples, increment component 622-2 may increment the trend count.

In some examples, logic flow 800 at block 808 may cause the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold, the second time period longer than the first time period. For these examples, sleep component 622-4 may cause the DPDK polling thread to sleep.

FIG. 9illustrates an example storage medium900. As shown in FIG. 9, the first storage medium includes a storage medium 900. The storage medium 900 may comprise an article of manufacture. In some examples, storage medium 900 may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium 900 may store various types of computer executable instructions, such as instructions to implement logic flow 700 or logic flow 800. Examples of acomputer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 10illustrates an example computing platform 1000. In some examples, as shown in FIG. 10, computing platform1000 may include a processing component 1040, other platform components 1050 or a communications interface 1060. According to some examples, computing platform 1000 may host power and/or performance management elements (e.g., DPDK power management components and an OS power management module) providing power/performance management functionality for a system having DPDK polling threads such as system 100 of FIG. 1. Computing platform 1000 may either be a single physical network device or may be a composed logical network device that includes combinations of disaggregatephysical components or elements composed from a shared pool of configurable computing resources deployed in a datacenter.

According to some examples, processing component 1040 may execute processing operations or logic for apparatus 600 and/or storage medium 900. Processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth) , integrated circuits, application specific integrated circuits (ASIC) , programmable logic devices (PLD) , digital signal processors (DSP) , field programmable gate array (FPGA) , memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API) , instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other platform components 1050 may include common computing elements, such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays) , power supplies, and so forth. Examples of memory units may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM) , random-access memory (RAM) , dynamic RAM (DRAM) , Double-Data-Rate DRAM (DDRAM) , synchronous DRAM (SDRAM) , static RAM (SRAM) , programmable ROM (PROM) , erasable programmable ROM (EPROM) , electrically erasable programmable ROM (EEPROM) , flash memory, polymer memory such as ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, an array of devices such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory) , solid state drives (SSD) and any other type of storage media suitable for storing information.

In some examples, communications interface 1060 may include logic and/or features to support acommunication interface. For these examples, communications interface 1060 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification. Network communications may occur via use of communication protocols or standards such those described in one or moreEthernet standards promulgated by IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications such as the OpenFlow Hardware Abstraction API Specification. Network communications may also occur according to theInfiniband Architecture specification or the TCP/IP protocol.

As mentioned above, computing platform 1000 may be implemented in a single network device or a logical network devicemade up of composed disaggregate physical components or elements from a shared pool of configurable computing resources. Accordingly, functions and/or specific configurations of computing platform1000 described herein, may be included or omitted in various embodiments of computing platform1000, as suitably desired for a physical or logical network device.

The components and features of computing platform1000 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs) , logic gates and/or single chip architectures. Further, the features of computing platform1000 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic” or “circuit. ”

It should be appreciated that the exemplary computing platform1000 shown in the block diagram of FIG. 10 may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth) , integrated circuits, application specific integrated circuits (ASIC) , programmable logic devices (PLD) , digital signal processors (DSP) , field programmable gate array (FPGA) , memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API) , instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable mediummay include a non-transitory storage medium to store logic. In some examples, thenon-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable mediummay include a non-transitory storage medium to store or maintaininstructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.

Some examples may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled, ” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The follow examples pertain to additional examples of technologies disclosed herein.

Example 1. An example apparatus may include circuitry at a host computing platform and a queue component for execution by the circuitry to monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The queue module may determine a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration. The apparatus may also include an increment component for execution by the circuitry that may increment a trend count based on the level of fullness for the receive queue following each polling iteration. The apparatus may also include a performance component for execution by the circuitry to send a performance indication to an OS power management module based on whether the trend count exceeds a tread count threshold. The performance indication may be capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.

Example 2. The apparatus of example 1, the OS power management module may increase the performance state of the processing element comprises the OS power management module capable of causing an operating frequency of the processing element to be increased.

Example 3. The apparatus of example 1, the level of fullness determined by the queue component may include one of near empty, half full or near full.

Example 4. The apparatus of example 3, the increment component may increment the trend count by a small number if the level of fullness is determined by the queue component to be near empty or by a large number if the level of fullness is determined by the queue component to be half full, the large number approximately 100 times that of the small number.

Example 5. The apparatus of example 3 may also include the performance component to send a high performance indication to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full by the queue component exceeds a consecutive threshold. The high performance indication may be capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state by causing an operating frequency of the processing element to be increased to a highest operating frequency.

Example 5-1. The apparatus of example 3, near empty may be 25％to 50％full, half full may be 51％to 75％full and near full may be greater than 75％full.

Example 6. The apparatus of example 1, the OS power management module may be capable of increasing the performance state of the processing element according to one or more industry standards including ACPI Specification, Revision 5.0. For these examples, the OS power management module may be capable of increasing the performance state of the processing element to enter a Pn-1 performance state, where “n” represent a lowest performance state resulting in a lowest operating frequency of the processing element.

Example 7. The apparatus of example 1 may also include the queue component to determine a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration. The increment component may increment an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold. The apparatus may also include a sleep component for execution by the circuitry to cause the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold. For these examples, the second time period may be longer than the first time period.

Example 8. The apparatus of example 7 may also include an interrupt control component for execution by the circuitry to send an interrupt turn on message to the NW I/O device that may enable a one-shot Rx interrupt based on whether the idle count exceeds a second idle count threshold.

Example 9. The apparatus of example 7, the sleep component may cause DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold and send a long sleep indication to the OS power management module. The long sleep indication may be capable of causing the OS power management module to cause the processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.

Example 10. The apparatus of example 9 may also include a timer component for execution by the circuitry to initiate a timer having a timer interval. The sleep component may determine a percentage of iterations for which the DPDK polling thread was sleeping during the timer interval responsive to the timer expiring. The performance component may send a performance indication to the OS power management module based on whether the percentage is greater than a percentage threshold. The performance indication may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element.

Example 11. The apparatus of example 9 may also include a timer component for execution by the circuitry to initiate a timer having a timer interval. The queue component may determine an average packet-per-iteration for packets received at the receive queue during the timer interval responsive to the timer expiring. The performance component may send a performance indication to the OS power management module based on whether the average packet-per-iteration is less than a packet average threshold. The performance indication may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element.

Example 12. The apparatus of example 9, the OS power management module may be capable of placing the processing element in sleep mode according to one or more industry standards including ACPI Specification, Revision 5.0. For these examples, the OS power management module may cause the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode responsive to the sleep indication.

Example 13. The apparatus of example 7, the consecutive threshold may be 5 iterations and each polling iteration may occur approximately every 1 microsecond.

Example 14. The apparatus of example 13, the sleep indication indicating the idle count is less than the first idle count threshold that may cause the DPDK polling thread to sleep for the first time period. For these examples, the first time period may last approximately 5 polling iterations.

Example 15. The apparatus of example 13, the sleep indication indicating the idle count exceeds the first idle count threshold that may cause the DPDK polling thread to sleep for the second time period. For these examples, the second time period may last approximately 50 polling iterations.

Example 16. The apparatus of example 1, the processing element may include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 17. The apparatus of example 1, the DPDK polling thread may be capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, an NAT application, a DPI application or a load balancer application.

Example 18. The apparatus of example1 may also include a digital display coupled to the circuitry to present a user interface view.

Example 19. An example method may include monitoring received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The method may also include determining a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration. The method may also include incrementing a trend count based on the level of fullness for the receive queue. The method may also include sending a performance indication to an OS power management module based on whether the trend count exceeds a tread count threshold. The performance indication may be capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.

Example 20. The method of example 19, the OS power management module to increase the performance state of the processing element includes the OS power management module capable of causing an operating frequency of the processing element to be increased.

Example 21. The method of example 19, the level of fullness may include one of near empty, half full or near full.

Example 22. The method of example 21, incrementing the trend count by a small number if the level of fullness is near empty or by a large number if the level of fullness is half full. For these examples, the large number may be approximately 100 times that of the small number.

Example 23. The method of example 21 may also include sending a high performance indication to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full exceeds a consecutive threshold. The high performance indication may be capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state including increasing an operating frequency of the processing element to a highest operating frequency.

Example 24. The method of example 21, near empty may be 25％to 50％full, half full may be 51％to 75％full and near full may be greater than 75％full.

Example 25. The method of example 19, the OS power management module may be capable of increasing the performance state of the processing element according to one or more industry standards including ACPI Specification, Revision 5.0. For these examples, the OS power management module may be capable of increasing the performance state of the processing element to enter a Pn-1 performance state, where “n” represent a lowest performance state resulting in a lowest operating frequency of the processing element.

Example 26. The method of example 17, the processing element may include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 27. The method of example 19, the DPDK polling thread may be capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, an NAT application, a DPI application or a load balancer application.

Example 28. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by system may cause the system to carry out a method according to any one of examples 19 to 27.

Example 29. An apparatus may include means for performing the methods of any one of examples 19 to 27.

Example 30. An example at least one machine readable medium may include a plurality of instructions that in response to being executed on system at a host computing platform cause the system to monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The instructions may also cause the system to determine a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration. The instructions may also cause the system to increment a trend count based on the level of fullness for the receive queue and send a performance indication to an OS power management module based on whether the trend count exceeds a tread count threshold. The performance indication may be capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.

Example 31. The at least one machine readable medium of example 30, the OS power management module to increase the performance state of the processing element may include the OS power management module being capable of causing an operating frequency of the processing element to be increased.

Example 32. The at least one machine readable medium of example 30, the level of fullness may include one of near empty, half full or near full.

Example 33. The at least one machine readable medium of example 32, the instructions may cause the system to increment the trend count by a small number if the level of fullness is near empty or by a large number if the level of fullness is half full. For these examples, the large number may be approximately 100 times that of the small number.

Example 34. The at least one machine readable medium of example 32, the instructions may further cause the system to send a high performance indication to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full exceeds a consecutive threshold. For these examples, the high performance indication may be capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state including increasing an operating frequency of the processing element to a highest operating frequency.

Example 35. The at least one machine readable medium of example 32, near empty may be 25％to 50％full, half full may be 51％to 75％full and near full may be greater than 75％full.

Example 36. The at least one machine readable medium of example 30, the OS power management module may be capable of increasing the performance state of the processing element according to one or more industry standards including ACPI Specification, Revision 5.0. The OS power management module may be capable of increasing the performance state of the processing element to enter a Pn-1 performance state, where “n” represent a lowest performance state resulting in a lowest operating frequency of the processing element.

Example 37. The at least one machine readable medium of example 30, the processing element may include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 38. The at least one machine readable medium of example 30, the DPDK polling thread may be capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, an NAT application, a DPI application or a load balancer application.

Example 39. An example method may include monitoring received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The method may also include determining a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration. The method may also include incrementing an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold. The method may also include causing the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold. The second time period may be longer than the first time period.

Example 40. The method of example 39 may also include sending an interrupt turn on hint to the NW I/O device and cause the DPDK polling thread to pause based on the idle count exceeding a second idle count threshold.

Example 41. The method of example 39 may also include the DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold. The method may also include sending a long sleep indication to an OS power management module. The long sleep indication may be capable of causing the OS power management module to cause a processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.

Example 42. The method of example 41 may also include initiating a timer having a timer interval. The method may also include determining a percentage of iterations for which the DPDK polling thread was sleeping during the timer interval responsive to the timer expiring. The method may also include sending a performance indication to the OS power management module based on whether the percentage is greater than a percentage threshold. The performance indication may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element.

Example 43. The method of example 41 may also include initiating a timer having a timer interval. The method may also include determining an average packet-per-iteration for packets received at the receive queue during the timer interval responsive to the timer expiring. The method may also include sending a performance indication to the OS power management module based on whether the average packet-per-iteration is less than a packet average threshold. The performance indication may cause the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element.

Example 44. The method of example 41, the OS power management module may be capable of placing the processing element in sleep mode according to one or more industry standards including ACPI Specification, Revision 5.0. For these examples, the OS power management module may cause the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode responsive to the sleep indication.

Example 45. The method of example 41, the processing element may be one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 46. The method of example 39, the consecutive threshold may be 5 iterations and each polling iteration may occur approximately every 1 microsecond.

Example 47. The method of example 46, the sleep indication may indicate the idle count is less than the first idle count threshold, causing the DPDK polling thread to sleep for the first time period. The first time period may last approximately 5 polling iterations.

Example 48. The method of example 46, the sleep indication may indicate that the idle count exceeds the first idle count threshold, causing the DPDK polling thread to sleep for the second time period. The second time period may last approximately 50 polling iterations.

Example 49. The method of example 39, the DPDK polling thread may be capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, an NAT application, a DPI application or a load balancer application.

Example 50. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by system at a host computing platform may cause the system to carry out a method according to any one of examples 39 to 49.

Example 51. An example apparatus may include means for performing the methods of any one of examples 39 to 49.

Example 52. An example at least one machine readable medium may include a plurality of instructions that in response to being executed on system at a host computing platform may cause the system to monitor received and available packet descriptors maintained at a receive queue for a NW I/O device over multiple polling iterations for a DPDK polling thread. The instructions may also cause the system to determine a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration. The instructions may also cause the system to increment an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold. The instructions may also cause the system to cause the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold. The second time period may be longer than the first time period.

Example 53. The at least one machine readable medium of example 52, the instructions may further cause the system to send an interrupt turn on hint to the NW I/O device and cause the DPDK polling thread to pause based on the idle count exceeding a second idle count threshold.

Example 54. The at least one machine readable medium of example 52, the DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold. The instructions may further cause the system to send a long sleep indication to an OS power management module. The long sleep indication may be capable of causing the OS power management module to cause a processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.

Example 55. The at least one machine readable medium of example 54, the instructions may further cause the system to initiate a timer having a timer interval and determine a percentage of iterations for which the DPDK polling thread was sleeping during the timer interval responsive to the timer expiring. The instructions may also cause the system to send a performance indication to the OS power management module based on whether the percentage is greater than a percentage threshold. The performance indication may be capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element.

Example 56. The at least one machine readable medium of example 54, the instructions may further cause the system to initiate a timer having a timer interval and determine an average packet-per-iteration for packets received at the receive queue during the timer interval responsive to the timer expiring. The instructions may also cause the system to send a performance indication to the OS power management module based on whether the average packet-per-iteration is less than a packet average threshold. The performance indication may cause the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element.

Example 57. The at least one machine readable medium of example 54, the OS power management module may be capable of placing the processing element in sleep mode according to one or more industry standards including ACPI Specification, Revision 5.0. The OS power management module may cause the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode responsive to the sleep indication.

Example 58. The at least one machine readable medium of example 54, the processing element may include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 59. The at least one machine readable medium of example 51, the consecutive threshold may include 5 iterations and each polling iteration may occur approximately every 1 microsecond.

Example 60. The at least one machine readable medium of example 59, the sleep indication may indicate the idle count is less than the first idle count threshold, causing the DPDK polling thread to sleep for the first time period. The first time period may last approximately 5 polling iterations.

Example 61. The at least one machine readable medium of example 59, the sleep indication may indicate the idle count exceeds the first idle count threshold, causing the DPDK polling thread to sleep for the second time period. The second time period may last approximately 50 polling iterations.

Example 62. The at least one machine readable medium of example 52, the DPDK polling thread may be capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, an NAT application, a DPI application or a load balancer application.

It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72 (b) , requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein, " respectively. Moreover, the terms "first, " "second, " "third, " and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.

]Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

An apparatus comprising:

circuitry at a host computing platform；

a queue component for execution by the circuitry to monitor received and available packet descriptors maintained at a receive queue for a network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread, the queue module to determine a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration；

an increment component for execution by the circuitry to increment a trend count based on the level of fullness for the receive queue following each polling iteration； and

a performance component for execution by the circuitry to send a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a tread count threshold, the performance indication capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.
The apparatus of claim 1, the OS power management module to increase the performance state of the processing element comprises the OS power management module capable of causing an operating frequency of the processing element to be increased.
The apparatus of claim 1, the level of fullness determined by the queue component comprises one of near empty, half full or near full.
The apparatus of claim 3, the increment component to increment the trend count by a small number if the level of fullness is determined by the queue component to be near empty or by a large number if the level of fullness is determined by the queue component to be half full, the large number approximately 100 times that of the small number.
The apparatus of claim 3, comprising:

the performance component to send a high performance indication to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full by the queue component exceeds a consecutive threshold, the high performance indication capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state by causing an operating frequency of the processing element to be increased to a highest operating frequency.
The apparatus of claim 3, comprising near empty is 25％ to 50％ full, half full is 51％ to 75％ full and near full is greater than 75％ full.
The apparatus of claim 1, comprising the OS power management module capable of increasing the performance state of the processing element according to one or more industry standards including Advanced Configuration and Power Interface (ACPI) Specification, Revision 5.0, the OS power management module capable of increasing the performance state of the processing element to enter a Pn-1 performance state, where “n” represent a lowest performance state resulting in a lowest operating frequency of the processing element.
The apparatus of claim 1, comprising:

the queue component to determine a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration；

the increment component to increment an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold； and

a sleep component for execution by the circuitry to cause the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold, the second time period longer than the first time period.
The apparatus of claim 9, comprising:

an interrupt control component for execution by the circuitry to send an interrupt turn on message to the NW I/O device to enable a one-shot receive (Rx) interrupt based on whether the idle count exceeds a second idle count threshold.
The apparatus of claim 8, comprising the sleep component to cause DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold and send a long sleep indication to the OS power management module, the long sleep indication capable of causing the OS power management module to cause the processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.
The apparatus of claim 10, comprising:

a timer component for execution by the circuitry to initiate a timer having a timer interval；

the sleep component to determine a percentage of iterations for which the DPDK polling thread was sleeping during the timer interval responsive to the timer expiring； and

the performance component to send a performance indication to the OS power management module based on whether the percentage is greater than a percentage threshold, the performance indication capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element.
The apparatus of claim 10, comprising:

a timer component for execution by the circuitry to initiate a timer having a timer interval；

the queue component to determine an average packet-per-iteration for packets received at the receive queue during the timer interval responsive to the timer expiring； and

the performance component to send a performance indication to the OS power management module based on whether the average packet-per-iteration is less than a packet average threshold, the performance indication capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element.
The apparatus of claim 10, comprising the OS power management module capable of placing the processing element in sleep mode according to one or more industry standards including Advanced Configuration and Power Interface (ACPI) Specification, Revision 5.0, the OS power management module to cause the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode responsive to the sleep indication.
The apparatus of claim 8, the consecutive threshold comprises 5 iterations and each polling iteration occurs approximately every 1 microsecond.
The apparatus of claim 14, comprising the sleep indication indicating the idle count is less than the first idle count threshold, causing the DPDK polling thread to sleep for the first time period, the first time period lasting approximately 5 polling iterations.
The apparatus of claim 14, comprising the sleep indication indicating the idle count exceeds the first idle count threshold, causing the DPDK polling thread to sleep for the second time period, the second time period lasting approximately 50 polling iterations.
The apparatus of claim 1, the processing element comprising one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.
The apparatus of claim 1, comprising the DPDK polling thread capable of executing a network packet processing application to process packets received by the NW I/O device, the network packet processing application including one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application or a load balancer application.
At least one machine readable medium comprising a plurality of instructions that in response to being executed on system at a host computing platform cause the system to:

monitor received and available packet descriptors maintained at a receive queue for a network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread；

determine a level of fullness for the receive queue based on available packet descriptors maintained at the receive queue following each polling iteration；

increment a trend count based on the level of fullness for the receive queue；

send a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a tread count threshold, the performance indication capable of causing the OS power management module to increase a performance state of a processing element executing the DPDK polling thread.
The at least one machine readable medium of claim 19, the level of fullness comprises one of near empty, half full or near full.
The at least one machine readable medium of claim 20, the instructions to further cause the system to:

send a high performance indication to the OS power management module responsive to a consecutive number of polling iterations for which the receive queue is determined to be near full exceeds a consecutive threshold, the high performance indication capable of causing the OS power management module to increase the performance state of the processing element to a highest performance state including increasing an operating frequency of the processing element to a highest operating frequency.
The at least one machine readable medium of claim 20, comprising near empty is 25％ to 50％ full, half full is 51％ to 75％ full and near full is greater than 75％ full.
The at least one machine readable medium of claim 19, the OS power management module capable of increasing the performance state of the processing element according to one or more industry standards including Advanced Configuration and Power Interface (ACPI) Specification, Revision 5.0, the OS power management module capable of increasing the performance state of the processing element to enter a Pn-1 performance state, where “n” represent a lowest performance state resulting in a lowest operating frequency of the processing element.
The at least one machine readable medium of claim 19, comprising the DPDK polling thread capable of executing a network packet processing application to process packets received by the NW I/O device, the network packet processing application including one of a firewall application, a virtual private network (VPN) application, a network address translation (NAT) application, a deep packet inspection (DPI) application or a load balancer application.
A method comprising:

monitoring received and available packet descriptors maintained at a receive queue for a network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread；

determining a number of packets received at the receive queue for each polling iteration based on available packet descriptors maintained at the receive queue following each polling iteration；

incrementing an idle count by a count of 1 if a number of packets received is 0 for a consecutive number of polling iterations that exceeds a consecutive threshold； and

causing the DPDK polling thread to sleep for one of a first or a second time period based on whether the idle count exceeds or is less than a first idle count threshold, the second time period longer than the first time period.
The method of claim 25, comprising:

sending an interrupt turn on hint to the NW I/O device and cause the DPDK polling thread to pause based on the idle count exceeding a second idle count threshold.
The method of claim 25, comprising:

the DPDK polling thread to sleep for the second time period based on the idle count exceeding the first idle count threshold； and

sending a long sleep indication to an operating system (OS) power management module, the long sleep indication capable of causing the OS power management module to cause a processing element executing the DPDK polling thread to be placed in a sleep mode for up to the second time period.
The method of claim 27, comprising:

initiating a timer having a timer interval；

determining a percentage of iterations for which the DPDK polling thread was sleeping during the timer interval responsive to the timer expiring； and

sending a performance indication to the OS power management module based on whether the percentage is greater than a percentage threshold, the performance indication capable of causing the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency or decreasing an operating voltage of the processing element.
The method of claim 27, comprising:

initiating a timer having a timer interval；

determining an average packet-per-iteration for packets received at the receive queue during the timer interval responsive to the timer expiring； and

sending a performance indication to the OS power management module based on whether the average packet-per-iteration is less than a packet average threshold, the performance indication to cause the OS power management module to lower a performance state of the processing element that includes decreasing an operating frequency of the processing element.
The method of claim 27, comprising the OS power management module capable of placing the processing element in sleep mode according to one or more industry standards including Advanced Configuration and Power Interface (ACPI) Specification, Revision 5.0, the OS power management module to cause the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode responsive to the sleep indication.