CN114545801A

CN114545801A - Processor capable of directly starting output by external signal

Info

Publication number: CN114545801A
Application number: CN202011292707.6A
Authority: CN
Inventors: 梁伟成; 张平
Original assignee: Xinqiao Technology Co ltd
Current assignee: Xinqiao Technology Co ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2022-05-27
Anticipated expiration: 2040-11-18
Also published as: CN114545801B

Abstract

The invention relates to a processor capable of directly starting output by an external signal, which mainly comprises an input unit, an output unit and a timing numerical control module, wherein the timing numerical control module is electrically connected with the input unit and the output unit.

Description

Processor capable of directly starting output by external signal

Technical Field

The present invention relates to a processor, and more particularly, to a processor capable of directly starting an output from an external signal.

Background

Generally, a processor of a Microprocessor (MPU), a Microcontroller (MCU), etc. generally includes an internal core logic block, a peripheral function block, and an input/output interface, as shown in fig. 5, which is a conventional processor 600 including an internal core logic block 610 (an arithmetic logic Unit 611), a peripheral function block 620 (a timer counter 621, a program memory 622, a register 623), and an input/output interface 630 (an input interface 631 and an output interface 632), wherein the processor 600 controls operations of the peripheral function block 620 and signals transmitted or received by the input/output interface 630 through the internal core logic block 610. To optimize the performance of the processor 600, the processor 600 further comprises an interrupt generator 640, wherein the interrupt generator 640 is configured to interrupt the processor 600 to execute the existing program, and then execute another program, and continue to execute the existing program after completing the execution of the other program, without waiting for the completion of the execution of the existing program.

However, although the conventional processor has introduced the operation of the interrupt operation, the conventional processor still needs to wait for tens of clock cycles before outputting the required signal, i.e. the conventional interrupt operation still causes the delay of the signal output, and thus, there is a need for a better solution.

Disclosure of Invention

In view of the above-mentioned deficiencies of the prior art, a primary objective of the present invention is to provide a processor capable of directly starting output by an external signal, which generates a programmable pulse signal according to an external trigger signal without passing through an internal core logic block of the processor, thereby achieving the purpose of improving control accuracy.

The main technical means adopted to achieve the above object is to make the processor capable of directly starting output by external signal include:

an input unit;

an output unit;

a timing and counting control module electrically connected with the input unit and the output unit,

the buffer is electrically connected with the timing and counting control module; and

the internal core logic block is electrically connected with the register;

wherein, the input unit obtains a trigger signal, the timing and counting control module controls the output unit to output a programmable pulse signal according to the trigger signal,

the processor does not control the output unit to output the programmable pulse signal with the internal core logic block.

With the above structure, the timing and counting control module can generate the programmable pulse signal according to the trigger signal, so that the processor can generate the programmable pulse signal according to the external trigger signal without waiting for the operation of the internal core logic block, thereby achieving the purpose of improving the control accuracy.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is a block diagram of a system architecture according to an embodiment of the present invention;

FIG. 2 is a block diagram of another system architecture of an embodiment of the present invention;

FIG. 3 is a block diagram of an embodiment of a timing and counting control module according to the present invention;

FIG. 4 is a timing diagram of one embodiment of the present invention; and

FIG. 5 is a block diagram of a conventional processor architecture.

Reference numerals

10

input unit

20, 20a, 20b timing counting control module

21 flip-flop 22 first logic gate

221 a first input 222 and a second input

223 output 23 second logic gate

231 a first input 232 and a second input

233 output end 24 timing counting unit

30

output unit

40, 40a, 40b buffer

50 internal core logic Block 100, 100' processor

600 processor 610 internal core logic block

611 arithmetic logic unit 620 peripheral function blocks

621 timer counter 622 program memory

623 buffer 630 input/output interface

631 input interface 632 output interface

640 interrupt generator CLK clock input

Clock internal Clock signal D input terminal

Clock signal gated by event overflow signal

ONtrigger signal ONlatch latch signal

Pprogram programmable pulse signal Q output end

R Reset terminal D-FF Reset signal

Ta, Ta1, Tb, Tc and Tc1 time points at the S setting end

Vh logic high potential

Detailed Description

Referring to fig. 1, the processor 100 at least includes an input unit 10, a timing count control module 20, an output unit 30, a register 40, and an internal core logic block 50. The input unit 10 is configured to receive a trigger signal ONtrigger. The timing and counting control module 20 is electrically connected to the input unit 10 for receiving the trigger signal ONtrigger through the input unit 10, the output unit 30 is electrically connected to the timing and counting control module 20, the output unit 30 is configured to output a programmable pulse signal Pprogram generated by the timing and counting control module 20, the buffer 40 is electrically connected to the timing and counting control module 20, and the internal core logic block 50 is electrically connected to the buffer 40. In other words, the timing and counting control module 20 is configured to control the output unit 30 to output the programmable pulse signal Pprogram according to the trigger signal ONtrigger. Therefore, the processor 100 can generate the programmable pulse signal Pprogram in real time according to the external trigger signal ONtrigger and the timing and counting control module 20 without waiting for the operation of the internal core logic block 50, thereby avoiding the delay caused by the internal core logic block 50 and achieving the purpose of improving the precise control.

In one embodiment, the trigger signal is an internal trigger signal of the processor 100 or an external trigger signal received by an external circuit of the processor 100.

In one embodiment, the processor 100 may be implemented as a controller applied to a switching power converter, a motor driving controller, or an automatic response controller, and the invention is not limited thereto.

In one embodiment, the input unit 10 and the output unit 30 are input/output interfaces of the processor 100.

In an embodiment, the programmable pulse signal Pprogram is a pulse width modulation signal, a clock signal or a single shot (single shot) signal, and the invention is not limited thereto.

In one embodiment, the processor 100 may further configure a plurality of timing and counting control modules for circuit design. As shown in fig. 2, in the embodiment, the processor 100' may be configured with two timing and counting control modules (i.e., the timing and counting control module 20a and the timing and counting control module 20b), the timing and counting control module 20a is electrically connected to the register 40a, the timing and counting control module 20b is electrically connected to the register 40b, the register 40a and the register 40b are electrically connected to the internal core logic block 50, and in this embodiment, the timing and counting control module 20b may be configured to implement a signal delay or counting function, and the invention is not limited thereto.

In another embodiment, the timing and counting control module 20a may first implement a signal delay function to delay the trigger signal ONtrigger, and then the timing and counting control module 20b generates the programmable pulse signal Pprogram, which is not limited in the present invention.

To further illustrate the timing and counting control module 20 of the present invention, please refer to fig. 3, which at least includes a flip-flop 21, a first logic gate 22, a second logic gate 23 and a timing and counting unit 24, wherein the flip-flop 21 is electrically connected to the first logic gate 22, the first logic gate 22 is electrically connected to the second logic gate 23, and the timing and counting unit 24 is electrically connected to the first logic gate 22 and the second logic gate 23, wherein the embodiment disclosed in fig. 3 is only for illustration and is not used to limit the present invention.

Further, the flip-flop 21 has an input terminal D, an output terminal Q, a clock input terminal CLK, a set terminal S, and a reset terminal R. The input terminal D and the setting terminal S are configured to receive a logic high voltage Vh, the clock input terminal CLK is configured to receive the trigger signal ONtrigger, the output terminal Q is configured to output a latch signal ONlatch, and the Reset terminal R is configured to receive a Reset signal D-FF Reset, so that the flip-flop 21 is configured to be triggered by the trigger signal ONtrigger and cause the latch signal ONlatch to change state (e.g., from a low voltage level to a high voltage level), and is configured to cause the latch signal ONlatch to change state (e.g., from a high voltage level to a low voltage level) according to the Reset signal D-FF Reset.

In one embodiment, the flip-flop is a D-type flip-flop, and the invention is not limited thereto.

The first logic gate 22 has a first input terminal 221, a second input terminal 222 and an output terminal 223, the first input terminal 221 is electrically connected to the timing and counting unit 24 for receiving an overflow signal event, the second input terminal 222 is electrically connected to the output terminal Q of the flip-flop 21 for receiving the latch signal ONlatch, the output terminal 223 is used for outputting the programmable pulse signal Pprogram, and the first logic gate 22 is used for generating the programmable pulse signal Pprogram according to the overflow signal event and the latch signal ONlatch.

The second logic gate 23 has a first input 231, a second input 232 and an output 233, the first input 231 is configured to receive an internal Clock signal Clock, the second input 232 is electrically connected to the output 223 of the first logic gate 22 and receives the programmable pulse signal Pprogram, the output 233 is electrically connected to the counting unit 24 and is configured to output a gated Clock signal gated Clock to the Clock input of the counting unit 24, and the second logic gate 23 is configured to generate the gated Clock signal gated Clock according to the internal Clock signal Clock and the programmable pulse signal Pprogram.

In an embodiment, the first logic gate 22 and the second logic gate 23 may be implemented by and gates, and the invention is not limited thereto.

Further, the overflow signal event is a control signal generated when the timer counting unit 24 counts up or down an overflow occurs. For example, at carry 16, when the tick count unit 24 is up-counting and overflowed by FFFF up-counting, the overflow signal event is generated.

In one embodiment, the overflow signal event is a low-level triggered signal, that is, when the overflow signal event is converted from a high voltage level to a low voltage level, the corresponding circuit is enabled to perform the corresponding operation.

In the following, referring to fig. 4, the operation method of the timing and counting control module 20 is described by taking the aforementioned timing and counting control module 20 as an example, it should be noted that the following high voltage level and low voltage level are only used for illustrating the present invention, and are not meant to limit the present invention, and those skilled in the art can use high voltage level or low voltage level instead to complete the present invention according to their requirements. Referring to fig. 3 and 4, firstly, at the time Ta, the trigger signal ONtrigger is switched from the low voltage level to the high voltage level, so that the flip-flop 21 is driven to switch the latch signal ONlatch from the low voltage level to the high voltage level, and at the same time, the overflow signal event is the high voltage level, so that the programmable pulse signal Pprogram is switched from the low voltage level to the high voltage level due to the latch signal ONlatch and the overflow signal event, and the corresponding gated Clock signal gated Clock is generated by the internal Clock signal Clock and the programmable pulse signal Pprogram. At time Ta1, the trigger signal ONtrigger is switched from the high voltage level to the low voltage level, and the latch signal ONlatch, the overflow signal event, the programmable pulse signal Pprogram and the Reset signal D-FF Reset remain unchanged. At time Tb, the latch signal ONlatch still maintains the high voltage level, and the overflow signal event is converted from the high voltage level to the low voltage level, so that the programmable pulse signal Pprogram is converted from the high voltage level to the low voltage level. At time Tc, the Reset signal D-FF Reset is switched from the high voltage level to the low voltage level, and the flip-flop 21 is Reset, so that the latch signal ONlatch is switched from the high voltage level to the low voltage level. At time Tc1, the Reset signal Reset changes from a low voltage level to a high voltage level. Here, an operation cycle is completed, and the timing count control module 20 returns to the initial state to wait for the next trigger signal ONtrigger.

In this embodiment, the timing and counting control module 20 generates the gated clock signal as the clock signal of the timing and counting unit 24 in addition to the programmable pulse signal Pprogram according to the trigger signal ONtrigger, in other words, the timing and counting control module 20 generates one or more pulse signals according to the trigger signal ONtrigger.

In another embodiment, the actions of the chronograph counting unit 24 may be synchronized by throttling (enable/halt) the counting or not of the chronograph counting unit 24.

In another embodiment, the timing count control module 20 may include two timing count units (24A, 24B), the timing count units (24A, 24B) have a count start difference value (for example, the count value of the timing count unit 24B is greater than that of the timing count unit 24A), so that the timing count units (24A, 24B) count simultaneously with the same clock, the trigger signal ONtrigger directly latches the current value of the timing count unit 24B and compares the current value with the value of the timing count unit 24A, and when the timing count unit 24A catches up with the timing count unit 24B, the overflow signal event is generated.

In summary, the timing and counting control module 20 of the present invention can generate the programmable pulse signal Pprogram in real time according to the trigger signal ONtrigger, so that the processor 100 can quickly and accurately generate the programmable pulse signal Pprogram required by the peripheral circuit without performing operations via the internal core logic block 50 and without being affected by the capability or delay of the internal core logic block 50, thereby realizing the function of controlling a high-level system by a low-level processor, reducing the system control cost, and achieving the purpose of improving the control accuracy.

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A processor capable of directly activating an output by an external signal, comprising:

an input unit;

an output unit;

a first timing and counting control module electrically connected with the input unit and the output unit,

the buffer is electrically connected with the first timing counting control module; and

the internal core logic block is electrically connected with the register;

wherein, the input unit obtains a trigger signal, the first timing and counting control module controls the output unit to output a programmable pulse signal according to the trigger signal,

wherein the processor does not control the output unit to output the programmable pulse signal with an internal core logic block.

2. The processor of claim 1, further comprising:

a second timing and counting control module electrically connected with the first timing and counting control module and the output unit and configured between the first timing and counting control module and the output unit; and

and a second register electrically connected to the second timing and counting control module and the internal core logic block and configured between the second timing and counting control module and the internal core logic block.

3. The processor of claim 1, wherein the timing and counting control module further comprises:

a flip-flop having a clock input terminal, an output terminal, and a reset terminal, the clock input terminal receiving the trigger signal, the output terminal outputting a latch signal, the reset terminal receiving a reset signal;

a first logic gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives an overflow signal, the second input terminal is electrically connected to the output terminal of the flip-flop and receives the latch signal, and the output terminal of the first logic gate outputs the programmable pulse signal;

a second logic gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second logic gate receives an internal clock signal, the second input terminal of the second logic gate is electrically connected to the input terminal of the first logic gate and receives the programmable pulse signal, and the output terminal of the second logic gate outputs a gated clock signal; and

and the timing counting unit is electrically connected with the first input end of the first logic gate and is electrically connected with the output end of the second logic gate.

4. The processor of claim 3, wherein at a first time point, the trigger signal, the latch signal, the overflow signal, the reset signal, and the programmable pulse signal are at a first voltage level; at a second time point, the overflow signal is converted from the first voltage level to a second voltage level, the latch signal and the reset signal are the first voltage level, the programmable pulse signal is converted from the first voltage level to the second voltage level, and the trigger signal is the second voltage level; at a third time point, the reset signal and the latch signal are converted from the first voltage level to the second voltage level, and the trigger signal, the programmable pulse signal and the overflow signal are the second voltage level, wherein the first time point is earlier than the second time point, and the second time point is earlier than the third time point.

5. The processor as recited in claim 4, wherein said trigger signal transitions from said first voltage level to said second voltage level at a fourth time, said fourth time being later than said first time and earlier than said second time.

6. The processor of claim 5, wherein the reset signal transitions from the second voltage level to the first voltage level at a fifth time, the fifth time being later than the third time.

7. The processor of any one of claims 4, 5 or 6, wherein the first voltage level is a high voltage level and the second voltage level is a low voltage level.

8. The processor of claim 3, wherein the flip-flop is a D-type flip-flop.

9. The processor of claim 3, wherein the first logic gate and the second logic gate are AND gates.

10. The processor of claim 3, wherein the operation of the timing and counting unit is synchronized by throttling the counting or non-counting of the timing and counting unit.

11. The processor as claimed in claim 3, wherein the timing count control module comprises two timing count units having count start difference values with each other, and latching a value of one of the timing count units with the trigger signal, and generating the overflow signal when another one of the timing count units overtakes the value of one of the timing count units.

12. The processor of claim 1, wherein the trigger signal is an external trigger signal from outside the processor.

13. The processor of claim 1, wherein the programmable pulse signal is a pulse width modulated signal, a clock signal, or a one-shot signal.

14. The processor of claim 1, wherein the timing count control module generates a plurality of pulse signals including the programmable pulse signal according to the trigger signal.