CN114490460A

CN114490460A - FLASH controller for ASIC and control method thereof

Info

Publication number: CN114490460A
Application number: CN202210328975.1A
Authority: CN
Inventors: 邓健; 田伟
Original assignee: Chipintelli Technology Co Ltd
Current assignee: Chipintelli Technology Co Ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-05-13
Anticipated expiration: 2042-03-31
Also published as: US20230315298A1; CN114490460B; US11768607B1

Abstract

A FLASH controller for ASIC and its control method, the said controller includes the master control module, and arbitration module, read data fifo and write data fifo that are connected with the master control module; the read data fifo and the write data fifo are both connected with the arbitration module and the data interface module, wherein the data interface module is connected with an AHB data bus; the controller further comprises a register module, the register module is connected with a read data fifo, a write data fifo, an arbitration module and a configuration interface module, the configuration interface module is connected with an AHB configuration bus, and the master control module is connected with the register module through a synchronization module. The invention uses the AHB data bus and the AHB configuration bus to correspond to different operations by two sets of bus interfaces, finishes the FLASH general read-write operation by DMA data transmission and a high-capacity internal cache unit, simplifies the operation flow of the controller and improves the data transmission efficiency.

Description

FLASH controller for ASIC and control method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a FLASH controller for an ASIC (application specific integrated circuit) and a control method thereof.

Background

With the rapid development of FLASH technology, more and more devices support Double-edge triggered data transmission of clock signals, namely Double Transfer Rate (DTR). The FLASH transmission rate adopting the DTR technology is twice as high as that of the single-edge data transmission technology. Currently, the highest rate of SPI NOR FLASH devices in DTR mode has been pushed out to reach 200 MHz. In relatively low frequency logic on-chip memory applications, NOR FLASH devices are capable of providing higher data transfer rates with a small number of interfaces and support on-chip execution, namely, xecute In Place, abbreviated XIP.

Chinese patent application No. 201811314760.4, entitled embedded Nor-FLASH controller level control method that is configurable and efficient, proposes a control method to improve FLASH data write rate by mass caching and automatically erasing Nor-FLASH data. However, the method has limited improvement on the bandwidth of data reading and writing, and cannot bring the performance of a high-performance FLASH device into full play.

The chinese patent application No. 201610934188.6, entitled serial FLASH controller-based method and apparatus for receiving data, proposes a method: two independent clocks, one working clock is introduced as a FLASH device clock, and a higher-frequency clock is used as a sampling clock for returning data of the FLASH device; and the serial data signal returned by the FLASH is delayed to improve the transmission speed of the serial FLASH data. However, the two clocks also increase the metastable risk of signals after crossing the clock domain, and in the case that one FLASH controller controls 2 pieces of FLASH with large bandwidth to transmit data, eight lines of Octal SPI are usually required to transmit data, and 8 data lines need to be delayed, which increases the area and power consumption of the logic unit.

Disclosure of Invention

In order to overcome the technical defects in the prior art, the invention discloses a DTR-FLASH controller for an ASIC (application specific integrated circuit) and a control method thereof.

The FLASH controller for the ASIC comprises a main control module, an arbitration module, a read data fifo and a write data fifo, wherein the arbitration module, the read data fifo and the write data fifo are connected with the main control module; the read data fifo and the write data fifo are both connected with the arbitration module and the data interface module, wherein the data interface module is connected with an AHB data bus;

the FLASH controller also comprises a register module, the register module is connected with a read data fifo, a write data fifo, an arbitration module and a configuration interface module, the configuration interface module is connected with an AHB configuration bus, and the main control module is connected with the register module through a synchronization module;

the main control module internally comprises a data transmitter submodule for transmitting FLASH data information; the data receiver submodule is used for configuring and acquiring data of the FLASH interface; and the clock generator submodule is used for generating a clock.

Preferably, the clock generator submodule comprises a TX clock generating branch, and the generated TX clock is used as a FLASH device working clock;

the TX clock generation branch comprises a first frequency division module and a first clock bypass selector connected with the output end of the frequency division module, and the first clock bypass selector is also connected with the TX clock gating module.

Preferably, the clock generator sub-module further comprises an RX clock generation branch, and the generated RX clock is used as an internal data acquisition clock;

the RX clock generation branch comprises a second frequency division module and a first phase shift selector connected with the output end of the second frequency division module;

the RX clock generating branch circuit also comprises an inverter and a third frequency division module connected with the output end of the inverter, and the output end of the third frequency division module is connected with the first phase shifting selector;

the RX clock generation branch further comprises a first RX clock gating module and a second RX clock gating module, and the output ends of the first RX clock gating module and the second RX clock gating module are connected with the second phase shift selector; the output ends of the first phase shift selector and the second phase shift selector are connected with the second clock bypass selector; wherein the first and second RX clock gating modules output signals that are out of phase by one master clock cycle.

The invention also discloses a FLASH controller control method for ASIC, which comprises arbitration module working modes, wherein the arbitration module working modes comprise the following 3 types:

mode M4:

when the register is configured in FLASH XIP mode, the arbitration module enters XIP mode idle state,

if the arbitration module judges that the FLASH is configured for XIP read operation, an active handshake signal of the XIP read operation is sent out, and an XIP read state is entered; during the period, the system reads back the data corresponding to the address from the read data fifo, and enters an XIP handshake slave state after waiting for a handshake return signal sent by the main control module;

if the arbitration module judges that the configuration is not XIP read operation on the FLASH, the configuration is kept in an XIP mode idle state;

mode M5: when the register is configured in FLASH XIP read prefetch mode, the arbitration module enters XIP mode idle state,

if the arbitration module judges that XIP prefetching read operation to FLASH is configured, an active handshake signal of the XIP prefetching read operation is sent out, then an XIP prefetching read state is entered, the system reads back data from the read data fifo in the period, the controller reads back data corresponding to a subsequent address to the read data fifo from the FLASH device, and after the arbitration module finishes one XIP prefetching read, the controller enters an XIP prefetching idle state to wait for the next XIP read;

judging whether the address transmitted by the next XIP reading operation is the address matched with the current data or not by the arbitration module, and if the current data is matched with the address, returning the corresponding data in the read data fifo;

if the data and the address are not matched, an XIP address jumping state is entered, the current data is discarded, whether the next pre-fetched data in the read data fifo is matched with the current address or not is judged, if the next pre-fetched data in the read data fifo is not matched with the current address, the non-matched data is discarded until the data matched with the current address is read; if the transmission address exceeds the pre-fetching address judgment range, the transmitted address is used for reading the FLASH again;

if the arbitration module judges that the configuration is not XIP writing operation on the FLASH, the configuration is kept in an XIP mode idle state;

mode M6: when the register is configured to be a FLASH XIP mode, the arbitration module enters an XIP mode idle state, if the arbitration module judges that the configuration is to be an XIP write operation to FLASH, an active handshake signal of the XIP write operation is sent out, then the XIP write state is entered, the period system stores data into write data fifo, and the XIP handshake slave state is entered after the main control module writes the data corresponding to the address and receives a handshake return signal;

the control method further comprises a control mode of the main control module, wherein the control mode of the main control module comprises the following two modes: after the main control module receives the active handshake signal of the arbitration module, the main control module enters a handshake slave state 1 from an idle state, and returns a handshake response signal to the arbitration module to finish the handshake process;

the main control module initiates an active handshake request to the arbitration module, the slave chip selection high state enters a handshake master state, the arbitration module sends a handshake response signal after receiving the handshake request, and the main control module receives the handshake response and ends the handshake process.

Preferably: after the master control module finishes the handshake process, the subsequent control mode further comprises the following modes:

master control mode 1: after the data synchronization is completed in the handshaking process, the FLASH device starts to work;

master control mode 2: converting the command data information into an SPI (serial peripheral interface) time sequence signal sent in a command period according to the transmission configuration;

master control mode 3: converting address data information into an SPI (serial peripheral interface) time sequence signal sent by an address cycle according to transmission configuration;

master control mode 4: converting the extended byte data information into an SPI (serial peripheral interface) time sequence signal sent by an extended byte period according to transmission configuration;

master control mode 5: converting the virtual bit data information into an SPI time sequence interface signal sent by a virtual bit period according to transmission configuration;

master control mode 6: converting the read data information into an SPI (serial peripheral interface) time sequence signal sent in a read data state according to transmission configuration;

master control mode 7: converting the written data information into an SPI (serial peripheral interface) time sequence signal sent in a data writing state according to transmission configuration;

master control mode 8: in a data reading state, if cache data received by the main control module from the FLASH device triggers a pre-configured fifo full-write threshold, the cache data is continuously cached to cause the loss of a data part; the master control module enters a FIFO ready waiting state, and continues to send a new SPI instruction after FIFO cache data are ready;

master control mode 9: after the master control module enters a ready state waiting for FIFO, if a new configuration transmission request exists, entering a handshake slave state 2 to synchronize new data, and clearing invalid data in FIFO;

master control mode 10: after the transmission of the data is finished, the FLASH device stops working, and the operation on the FLASH is finished;

master control mode 11: and the master control module enters an idle state after finishing the handshake and waits for new instruction operation.

Preferably: the operating modes of the arbitration module further comprise the following 3 types:

mode M1: when the register is configured to be a FLASH common configuration mode, the arbitration module enters a general configuration mode idle state, then sends an active handshake signal, waits for the main control module to send configured data, and enters a general handshake slave state after receiving a handshake return signal;

mode M2: when the register is configured to be a FLASH common data mode, firstly entering a general data mode idle state, if the arbitration module judges that the register is configured to be a FLASH reading operation, sending an active handshake signal of the reading operation, then entering a general reading state, and waiting for the system to read data from read data fifo to a data interface bus;

waiting for the main control module to finish reading the data in the FLASH, and entering a general handshake slave state after receiving a handshake return signal; if the arbitration module judges that the configuration is not the general read operation of the FLASH, the configuration is kept in a general data mode idle state;

mode M3: when the register is configured to be a FLASH common data mode, firstly entering a general data mode idle state, if the arbitration module judges that the register is configured to be a FLASH write operation, sending an active handshake signal of the write operation, then entering a general write state, and waiting for data to be stored in write data fifo;

waiting for the main control module to write data, and entering a general handshake slave state after receiving a handshake return signal; and if the arbitration module judges that the configuration is not the general write operation on the FLASH, keeping the configuration in a general data mode idle state.

The invention uses AHB data bus and AHB configuration bus two sets of bus interfaces to correspond to different operations, thus supporting to use 2 chip selection signals to complete FLASH large bandwidth data flow control, and through DMA data transmission and large capacity internal cache unit to complete FLASH general read-write operation, simplifying the operation flow of the controller and improving the data transmission efficiency.

The invention reduces the area and power consumption of the controller through flexible time sequence adjustment design, reserves enough time sequence allowance, reduces the workload when the digital back end is realized, and shortens the period of the project. The adjustable time sequence improves the stability of the chip in the complex environment.

The data bandwidth supported by the invention in the SPI single line mode is as follows: the data bandwidth in the SPI octcal (8-line) mode is less than or equal to 166Mbit/s; the data bandwidth in DTR mode is: less than or equal to 400 Mbyte/s.

Drawings

FIG. 1 is a schematic diagram of a typical application scenario of the FLASH controller according to the present invention;

FIG. 2 is a diagram of an embodiment of an internal design architecture of the FLASH controller according to the present invention;

FIG. 3 is a diagram illustrating an embodiment of an arbitration state diagram of the arbitration module according to the present invention;

M1-M6 in FIG. 3 represent different modes of operation;

FIG. 4 is a diagram illustrating an embodiment of a state diagram of a host module according to the present invention;

fig. 5 is a schematic diagram of a specific implementation manner of the clock generation module according to the present invention.

Detailed Description

The following provides a more detailed description of the present invention.

A typical application scenario of the FLASH controller according to the present invention is shown in fig. 1.

In fig. 1, a FLASH controller adopts a DTR (Double edge triggered data transfer) FLASH controller, the FLASH controller is connected to a Bus matrix through an AHB (Advanced High-performance Bus) data Bus and an AHB configuration Bus, and the Bus matrix is connected to a Direct Memory Access (DMA) controller through an AHB Bus of the DMA and is connected to a CPU central processing unit through a data Bus DBUS, an instruction Bus IBUS, and a system Bus SBUS. The CPU kernel finishes instruction acquisition through IBUS, data loading and access are finished through a data bus DBUS, and peripheral access is finished through an SBUS.

The DMA controller of FIG. 1 is used for direct transfer of memory data; the SCU controller provides a clock and a reset signal required by the DTR FLASH controller; the bus matrix provides access arbitration management for a DMA controller bus, three buses of a CPU central processing unit and a DTR FLASH controller bus. The port IOPAD is used for interface management of input and output pins of the FLASH device.

The FLASH controller corresponds to different operations by using two sets of bus interfaces of an AHB data bus and an AHB configuration bus.

When a large amount of data is needed to be transmitted, the AHB data bus interface is used, and when the controller configuration and the FLASH instruction are sent, the AHB configuration bus interface is used. Thereby supporting the use of 2 chip select signals to complete FLASH large bandwidth data flow control, and being capable of configuring various SPI interfaces: the configuration of single-line SPI, double-line SPI, four-line SPI and eight-line SPI, the receiving and sending of clock single-edge data and the receiving and sending of DTR clock double-edge data are supported, and various command operations of FLASH are compatible. SPI is a Serial Peripheral Interface (Serial Peripheral Interface).

The FLASH general read-write operation is completed through DMA data transmission and a high-capacity internal cache unit, the operation flow of the controller is simplified, and the data transmission efficiency is improved.

Resolving a read-write signal, a read-write address and data length information of an AHB bus protocol through an AHB data bus interface to complete XIP operation, and setting a data prefetching mode; when the pre-fetching mode is started, the controller reads data in the FLASH device in advance according to the data address and judges whether the next sent address is in the pre-fetching range. If the address is in the range, the data stored in the corresponding address is directly returned, so that the data reading performance can be improved. The system can be booted in the FLASH device by powering on the default configuration to perform the operation in the chip.

When the FLASH adopts a Pseudo Static Random Access Memory (PSRAM), the FLASH controller can simultaneously support the PSRAM of a plurality of interfaces such as serial SPI, Quad SPI (four-wire SPI interface), Octal SPI (eight-wire SPI interface) and the like to realize XIP writing operation. The reading and writing signals, the reading and writing addresses and the data length information are analyzed by the AHB bus protocol signals to complete XIP writing, and the method is compatible with various command operations of the PSRAM.

The FLASH controller is internally provided with a clock generation module which generates a clock internally, so that the time sequence is flexibly adjusted: the clock generation module supports a plurality of clock frequency point configurations and can be configured to 1/2/4/6/8 frequency division of the input master clock; the data reception clock RX clock phase adjusts.

An internal design architecture of the FLASH controller of the present invention is shown in fig. 2.

The system comprises a main control module, and an arbitration module, a read data fifo and a write data fifo which are connected with the main control module; the read data fifo and the write data fifo are both connected with the arbitration module and the data interface module, wherein the data interface module is connected with an AHB data bus;

the main control module internally comprises a data transmitter submodule for transmitting FLASH data information and supporting phase adjustment of transmitted data; the data receiver submodule is used for configuring and acquiring data of the FLASH interface; and the clock generator submodule is used for generating a clock.

The register module is mainly used for storing relevant parameters of the FLASH controller and the current state of the controller. The module can send the configuration information of the bus to the controller to the corresponding module, collect the information of each submodule and generate state and interrupt information.

The configuration interface module is a bus interface of the register module and is mainly used for reading and writing parameters of the controller. The module is an AHB slave interface, is butted with an AHB master interface of an external bus matrix, can convert signals of the AHB into read-write enable and performs data interaction with the register module.

The data interface module is an AHB data transmission interface and is used for transmitting data streams. The module reads the FLASH data cached in the read data fifo (first-in first-out register) to the bus matrix, and can also cache the data transmitted from the bus matrix to the write data fifo. It can send the read-write address and data length information to the arbitration module.

The arbitration module judges the current transmission mode and determines the current operation according to the data transmitted by the data interface and the configuration interface module: sending the corresponding transmission mode and the corresponding address and data length information to a main control module; when DMA is used for reading and writing, the arbitration module generates a DMA transmission request signal; data may be transmitted in a single transmission or burst transmission manner by the AHB.

The main control module is mainly adapted to a FLASH interface protocol, and controls read-write data caching, flexible configuration of data receiving and sending formats and a FLASH device interface time sequence through a state machine, as shown in fig. 4. The main control module comprises three sub-modules: the data transmitter submodule is used for transmitting FLASH data information, and the clock generator submodule is used for generating a FLASH device clock TX clock and a sampling clock RX clock of the data receiver module. A highly flexible design employed inside the clock generator sub-module is used for timing adjustment of the RX clock. The data receiver sub-module can configure and collect the data of the FLASH interface according to different interface modes. The master control module also uses state handshake to complete various mode switching, address jump, data preparation, etc.

The write data fifo, the read data fifo, and the buffer register built in the register module are used to buffer the internal data. The data cache can be configured with 2 data cache modes: 1. configuring a register mode; 2. the FIFO storage mode and the high-capacity data writing FIFO buffer unit can buffer the data of the FLASH page at one time, improve the data sending rate, have configurable trigger threshold and are asynchronous FIFO.

The synchronous module is used for clock domain crossing processing of internal asynchronous clock domain signals.

One specific implementation of the arbitration state diagram of the arbitration module of the present invention is shown in fig. 3, which can generate at least 6 control modes, respectively:

mode M1: when the register is configured to be in a FLASH common configuration mode, the arbitration module enters a general configuration mode idle state, then sends out an active handshake signal, and enters a general handshake slave state after receiving a handshake return signal after the main control module finishes sending the configured data. Indicating that the configuration of the transmission has been completed. The mode M1 is mainly applied to the transmission of FLASH instructions, does not relate to the transmission of data, and can complete the reading and writing of a single instruction by configuring a cache register arranged in a register module. The configuration of the instruction is simple and the response speed is high.

Mode M2: when the register is configured to be a FLASH common data mode, the general data mode is firstly switched into an idle state, if the arbitration module judges that the register is configured to be a FLASH read operation, an active handshake signal of the read operation is sent out, then the register is switched into a general read state, and the system waits for the data to be read from the read data fifo to the data interface bus.

After the main control module finishes reading the data with the configuration data amount and receives the handshake return signal, the arbitration module enters a general handshake slave state to indicate that the read data is finished reading. The mode M2 is mainly used in a scenario where a large amount of data is read from a FLASH device, and fifo is used as a data buffer and DMA is required to carry the data.

And if the arbitration module judges that the configuration is not the general read operation of the FLASH, keeping the configuration in a general data mode idle state.

Mode M3: when the register is configured to be a FLASH common data mode, the general data mode is firstly switched into an idle state, if the arbitration module judges that the register is configured to be a FLASH write operation, an active handshake signal of the write operation is sent out, then the register is switched into a general write state, and data is waited to be stored in write data fifo.

After the main control module sends the data written in the FLASH and receives the handshake return signal, the arbitration module enters a general handshake slave state. Indicating that the transmitted data has completed writing. The mode M3 is mainly applied to the FLASH device data programming scene. Fifo is required to be used as a data buffer and DMA to carry data. Usually, the data programming of one page unit of FLASH requires time of millisecond, so the writing operation of FLASH is usually operated at lower working frequency.

And if the arbitration module judges that the configuration is not the general write operation on the FLASH, keeping the configuration in a general data mode idle state.

The invention also proposes three modes of operation of on-chip execution (XIP);

mode M4: when the register is configured to a FLASH XIP mode, the idle state of the XIP mode is entered first, if the arbitration module judges that the register is configured to read FLASH XIP, an active handshake signal of XIP read operation is sent out, then the register enters an XIP read state, during which the system can read back data from read data fifo by using a bus, and after waiting for the main control module to read FLASH data corresponding to an address and receiving a handshake return signal, the register enters an XIP handshake slave state to indicate that data corresponding to an address has been read back.

If the arbitration module determines that the configuration is not an XIP read operation to FLASH, it remains in an XIP mode idle state.

The mode M4 is mainly applied to a scene in which on-chip execution is performed on FLASH stored data, and fifo buffer data is required, and DMA is not required to transfer data. The system bus can execute programs in the FLASH chip, but has certain time sequence overhead.

Mode M5: when the register is configured to be a FLASH XIP read pre-fetch mode, the idle state of the XIP mode is entered first, if the arbitration module judges that the read operation is configured to be FLASH XIP pre-fetch, an active handshake signal of the XIP pre-fetch operation is sent out, then the XIP pre-fetch state is entered, during the period, the system reads back data from the read data fifo by using a bus, the controller can continuously read back the data corresponding to the subsequent address from the FLASH device to the read data fifo, and after the arbitration module finishes one-time XIP pre-fetch, the memory enters the XIP pre-fetch idle state to wait for the next-time XIP read. The arbitration module judges whether the address transmitted by the next XIP reading operation is the address matched with the current data, if the current data is matched with the address, the corresponding data in the read data fifo is immediately returned, if the data is not matched with the address, the XIP address jumping state is entered, the current data is discarded, whether the next prefetched data in the fifo is matched with the current address is judged, and if the data is not matched with the address, the unmatched data is discarded until the data matched with the current address is read. And if the transmitted address exceeds the address judgment range, reading the data of the FLASH by using the transmitted address. When the state is in XIP prefetch idle state, the prefetch mode may be exited, the XIP exit prefetch handshake master state entered, and the XIP mode idle state returned. The arbitration module enters an XIP handshake slave state when it receives a handshake return signal while in the XIP wait handshake state. Indicating that the data has been read back.

If the arbitration module determines that the configuration is not an XIP prefetch read operation to FLASH, then the state is maintained as an XIP mode idle state.

The mode M5 is mainly applied to a high-performance scenario in which FLASH stored data is read quickly, fifo buffer data is required, and DMA is not required to carry the data. After prefetching is started, the time sequence overhead can be greatly reduced when the system bus reads data, and the data reading speed is improved.

Mode M6: when the controller-connected FLASH is a PSRAM device, it can be configured in an XIP write mode. When the register is configured as a FLASH XIP mode, the idle state of the XIP mode is firstly entered, if the arbitration module judges that the configuration is the XIP write operation to FLASH, an active handshake signal of the XIP write operation is sent out, then the system enters the XIP write state, the system can store data into write data fifo by using a bus in the period, and the system enters the XIP handshake slave state after waiting for the main control module to write the PSRAM data corresponding to an address and receiving a handshake return signal. Indicating that data corresponding to an address has been written.

If the arbitration module determines that the configuration is not an XIP write operation to FLASH, it remains in an XIP mode idle state.

The mode M6 is mainly applied to a scene of writing data at high speed by using a PSRAM device, and the operation flow is simplified because the FLASH device has long programming time and can directly and quickly write data by using the PSRAM device.

The XIP mode idle state in each mode indicates that the arbitration module enters an XIP working state according to the configuration of the CPU, but does not start a data transmission operation. The XIP handshake slave state indicates that the arbitration module is performing handshake with the main control module, and the main control module initiates an active handshake signal to the arbitration module after completing data transmission operation in the XIP working mode, and notifies the arbitration module of data transmission completion. The general handshake slave state works the same.

In each mode, the configuration of the register is determined by a command sent by the CPU, and the configuration is completed by the register module.

Fig. 4 shows a control state diagram of the master control module of the present invention, and the handshake process established between the master control module and the arbitration module includes the following two typical control modes:

after the arbitration module completes the arbitration of the working mode according to the configuration information sent by the CPU, the arbitration module enters an active handshake state, and sends specific working information to the main control module to complete specific operation on the FLASH device. Meanwhile, after the main control module receives the active handshake signal of the arbitration module, the main control module enters a handshake slave state 1 from an idle state and returns a handshake response signal to the arbitration module to finish the handshake process.

Or the main control module initiates an active handshake request to the arbitration module, the arbitration module sends out a handshake response signal after receiving the handshake request, and the main control module receives the handshake response and exits the handshake process.

The arbitration module and the main control module perform each mode switching control through handshake coordination, and can efficiently synchronize data among different modules without causing data conflict. The method for acquiring the new instruction through the handshake process ensures the correctness of the data transmission in progress and avoids data collision and system crash caused by illegal operation.

The handshake matching process is that the arbitration module and the main control module are in the preparation and end stages of data transmission. After the active handshake signal is sent out, the receiving module enters a slave handshake state in an idle state, enters a slave handshake state and ends a handshake process; and transmitting data after finishing the handshake process.

For example, after the arbitration module in the mode M4 sends the active handshake signal of XIP read operation, the master module receives the active handshake signal of the arbitration module, if the master module is in the idle state at this time, returns a handshake response signal to end the handshake process, and if the master module is in another state, enters another master state. For another example, the master module initiates an active handshake signal, and the arbitration module enters an XIP handshake slave state if the arbitration module waits for a handshake state in XIP after the active handshake signal is received.

For another example, when the arbitration module operates during an XIP read operation, the CPU suddenly changes the operating mode of the controller from an XIP read operation to an XIP prefetch read operation, but the arbitration module does not receive an active handshake request initiated after the master control module completes the data transfer operation and returns to an idle state, and then ignores the instruction for changing the current operating mode. After the main control module finishes data transmission work, a handshake request is initiatively initiated to the arbitration module and returns to an idle state to wait for new handshake to receive a new instruction, or during the period of waiting for FIFO ready state, the controller and the flash device receive a new instruction through new handshake under the condition that no data is transmitted, and during the period of transmitting data of other states and the flash device, the main control module cannot enter into a handshake state to obtain a new instruction.

After the handshake process is established between the main control module and the arbitration module, the subsequent operation is determined according to specific working information, and the method mainly comprises the following steps:

master control mode 1: after the data synchronization between the modules is completed in the handshake process, the main control module enters a FLASH chip select low state, and usually, the FLASH device starts to work when a chip select signal is at a low level.

Master control mode 2: and converting the command data information into an SPI (serial peripheral interface) signal sent in a command period state according to the transmission configuration. The length of the sent command data is configurable, and the step can be skipped according to application requirements.

Master control mode 3: and converting the address data information into an SPI (serial peripheral interface) time sequence interface signal sent in an address cycle state according to the transmission configuration. The length of the sent address data is configurable, and the step can be skipped according to application requirements.

Master control mode 4: and converting the extended byte data information into an SPI time sequence interface signal transmitted in an extended byte period state according to the transmission configuration. This step can be skipped according to application requirements.

Master control mode 5: and converting the virtual bit data information into an SPI time sequence interface signal sent in a virtual bit period state according to the transmission configuration. The length of the dummy bit period to be sent is configurable, and the step can be skipped according to the application requirements.

Master control mode 6: and converting the read data information into an SPI (serial peripheral interface) time sequence signal sent in a read data state according to the transmission configuration. The length of the read data is configurable, and the step can be skipped according to the application requirements.

Master control mode 7: and converting the written data information into an SPI (serial peripheral interface) time sequence signal sent in a data writing state according to the transmission configuration. This step can be skipped according to application requirements.

The command cycle, the address cycle, the extended byte, the dummy bit cycle, the read data, the write data and other master control modes described in the master control modes 1 to 7 can be skipped to meet different application scene requirements. Such as operating only in instruction cycles, or only in instruction cycles plus address cycles, etc.

Master control mode 8: in a data reading state, if cache data received by the main control module from the FLASH device triggers a pre-configured fifo full-write threshold, the cache data is continuously cached to cause the loss of a data part; the main control module enters a FIFO ready waiting state, and continues to send a new SPI instruction after FIFO cache data are ready.

Master control mode 9: when the master control module enters a ready state of waiting FIFO, if a new configuration request is transmitted, entering a handshake slave state 2 to synchronize new data, and clearing invalid data in FIFO.

Master control mode 10: when the data is received and transmitted, the main control module enters a chip selection high state, the FLASH device stops working when the chip selection signal is at a high level, the operation on the FLASH is finished,

master control mode 11: and initiating an active handshake request to the arbitration module, sending a handshake response signal after the arbitration module receives the handshake request, and receiving the handshake response and exiting the handshake process by the main control module.

Master control mode 12: and the master control module enters an idle state after finishing the handshake and waits for new instruction operation.

One specific circuit configuration of the clock generator sub-module of the present invention is shown in fig. 5, which uses a master clock and a plurality of positive and negative edge enable signals to generate a TX clock and an RX clock, respectively.

The clock generator submodule comprises a TX clock generating branch, the TX clock generating branch comprises a first frequency division module and a first clock bypass selector connected with the output end of the frequency division module, and the first clock bypass selector is also connected with a TX clock gating module;

when the frequency divider is used, the main clock is connected with the input ends of the TX clock gating module and the first frequency dividing module; the first frequency-dividing module input is controlled by a TX clock positive edge enable signal and a TX clock negative edge enable signal which are input externally.

The clock generator submodule generates a TX clock which is used as an operating clock of the FLASH device, and the TX clock can be configured to be the same frequency, 2 frequency division, 4 frequency division, 6 frequency division and 8 frequency division of a main clock. The specific generation process of the TX clock is as follows:

step 1: the main clock input to the DTR FLASH controller is a system working clock, the main control module generates two control signals of TX clock positive edge enable and TX clock negative edge enable of a frequency division clock according to a frequency division coefficient configured by the CPU, and the TX clock positive edge enable signal and the TX clock negative edge enable signal respectively control the rising edge and the falling edge of the TX clock after frequency division of the main clock by 2, 4, 6 and 8. When the positive edge of the TX clock is enabled and the negative edge of the TX clock is disabled, the TX clock is converted from low level to high level; the TX clock transitions from a high level to a low level when the TX clock positive edge enable is inactive and the TX clock negative edge enable signal is active.

Step 2: the main clock is gated by a TX clock gating module to obtain a gated TX clock. The TX clock gating module has the function of generating a clock with the same frequency as the main clock, the main control module generates a clock gating signal according to the control state of the current transmitted or received FLASH data, and when the FLASH needs to work a clock, gating is opened and the clock starts to be output; and when the FLASH does not work, closing the gate control. The output clock is stopped. The specific circuits of the gate control module are prior art in the field and are not described herein again.

And 3, step 3: and the gated TX clock and the divided TX clock are selected by the first clock bypass selector to obtain the TX clock, and the selection signal is a clock bypass selection signal.

The clock generator sub-module also generates an RX clock as an internal data acquisition clock. The RX clock may be configured to be co-frequency, divide-by-2, divide-by-4, divide-by-6, divide-by-8, etc., supporting configurable phase shifting, such as shifting the RX clock by 1 to 8 master clock cycles based on a divided-by-8 RX clock generated by the master clock. I.e. the phase shift of the divided clock can reach the size of the division factor. In the same-frequency mode, only one main clock period is supported for phase adjustment.

The clock generator submodule also comprises an RX clock generation branch circuit, and the RX clock generation branch circuit comprises a second frequency division module and a first phase shift selector connected with the output end of the second frequency division module;

the RX clock generation branch further comprises a first RX clock gating module and a second RX clock gating module, and the output ends of the first RX clock gating module and the second RX clock gating module are connected with the second phase shift selector; the output ends of the first phase shift selector and the second phase shift selector are connected with the second clock bypass selector; the first RX clock gating module and the second RX clock gating module output signals have different phases by one main clock cycle due to different effective time of gating signals of the two gating units;

the output end of the second clock bypass selector is connected with the DQS selector through a delay module;

when the frequency divider is used, the main clock is connected with the first RX clock gating module, the second RX clock gating module inverter and the second frequency dividing module; the second frequency division module is controlled by the main control module input RX clock positive edge enable signal and RX clock negative edge enable signal. The DQS signal is input to the DQS selector. The FLASH device data strobe output signal (DQS) can accurately indicate the period of each data transmission for the receiving party to accurately receive the data.

One specific generation process of the RX clock is as follows:

step 1: the RX clock positive edge enable signal and the RX clock negative edge enable signal control the rising edge and the falling edge of the frequency division clock to obtain the divided RX clock; the RX clock positive edge enable and RX clock negative edge enable signals are generated by a division coefficient configuration.

Step 2: and the inverted main clock obtained after the main clock passes through the inverter is used for sampling the divided RX clock, so that the divided RX clock with the phase offset of 90 degrees and negative edge sampling is obtained.

And step 3: the divided RX clock and the divided RX clock sampled at the negative edge pass through a first phase shift selector controlled by an RX clock phase shift enable signal, and then the selected signals are sent to a second clock bypass selector.

And 4, step 4: after the main clock passes through two RX clock gating units, two data sampling clocks with a phase difference of one cycle are obtained: gated RX clock 1 and gated RX clock 2.

And 5: and passing the gated RX clock 1 and the gated RX clock 2 through a second phase shift selector, and sending the selected clocks into a second clock bypass selector. The selection signal of the second clock bypass selector is a clock bypass selection signal.

Step 6: the signal selected by the second clock bypass selector is connected with the delay module to perform clock delay fine adjustment, the fine adjustment grade can be set to be 1-32 grade, and the delay time is different according to the performance of the standard unit (the delay time of the complementary metal oxide semiconductor is greatly influenced by the process, the temperature and the voltage). In general, the delay of the 1-stage delay unit is in picoseconds, the total delay of the 32-stage delay units is in nanoseconds, and the delayed RX clock is output.

And 7, sending the delayed RX clock and the DQS signal of the FLASH device to a DQS selector, selecting the obtained RX clock as a sampling clock of data, and selecting the selection signal of the DQS selector as the selection signal of the DQS clock.

Where the DQS signal is the signal output by the FLASH device to the controller, the FLASH device data strobe output signal (DQS) can accurately indicate the period of each data transfer.

Each frequency division module can adopt a single D trigger, and a phase shift selector and a clock bypass selector are in the prior art; according to the invention, the clock generator submodule generates a TX clock and an RX clock, wherein the rising edge and the falling edge of the TX clock can be used as the clock edge of data transmission, and the rising edge and the falling edge of the RX clock can be used as the clock edge of data sampling. And each clock has high adjustability, which is specifically classified into 3 grades:

the first stage of adjustment is frequency division phase shift, the timing adjustable range of the stage is large, the RX clock is divided by the main clock, and the rising edge of the RX clock can be adjusted within the frequency division range, for example, when the RX clock is configured to be divided by 8, the time point of the start of the rising edge of the RX clock can be selected from the range from 1 st main clock cycle to 8 th main clock cycle;

the second stage of adjustment is sampling clock edge adjustment, and the adjustment is selected through a rising edge and a falling edge, for example, the rising edge of the RX clock after frequency division is selected, and the phase adjustment is 0 degree; the rising edge of the divided-frequency RX clock with negative edge sampling is 90-degree phase adjustment; the falling edge of the divided RX clock is 180-degree phase adjustment; the negative edge of the divided RX clock sampled is 270 degrees phase adjustment; the adjusting range of the second-stage adjustment is 90 degrees of phase of one master clock cycle;

the third stage is the delay adjustment of the delay module, and the adjustable range of the time sequence of the stage is smaller and is used for fine adjustment of the clock signal.

The three-level adjustment can enable the design to accurately sample data at normal temperature and in high and low temperature environments, and the stability of the chip is improved. By having an adjustable clock, a large timing margin is left for the back-end implementation steps, and digital back-end personnel can be free from spending too much time and effort on the timing satisfaction of the controller logic, thereby speeding up project progress.

The foregoing is directed to preferred embodiments of the present invention, wherein the preferred embodiments are not obviously contradictory or subject to any particular embodiment, and any combination of the preferred embodiments may be combined in any overlapping manner, and the specific parameters in the embodiments and examples are only for the purpose of clearly illustrating the inventor's invention verification process and are not intended to limit the scope of the invention, which is defined by the claims and the equivalent structural changes made by the description and drawings of the present invention are also intended to be included in the scope of the present invention.

Claims

1. A FLASH controller for an ASIC is characterized by comprising a main control module, an arbitration module, a read data fifo and a write data fifo, wherein the arbitration module, the read data fifo and the write data fifo are connected with the main control module; the read data fifo and the write data fifo are both connected with the arbitration module and the data interface module, wherein the data interface module is connected with an AHB data bus;

2. The FLASH controller for an ASIC of claim 1 wherein said clock generator submodule includes a TX clock generation branch, the generated TX clock being a FLASH device operating clock;

3. A FLASH controller for an ASIC according to claim 1 or 2, wherein the clock generator submodule further comprises an RX clock generation branch, the generated RX clock being an internal data acquisition clock;

4. A FLASH controller control method for ASIC is characterized by comprising an arbitration module working mode, wherein the arbitration module working mode comprises the following 3 types:

mode M4:

the control method also comprises a main control module control mode, wherein the main control module control mode comprises the following two modes: after the main control module receives the active handshake signal of the arbitration module, the main control module enters a handshake slave state 1 from an idle state and returns a handshake response signal to the arbitration module to finish the handshake process;

5. The control method according to claim 4, characterized in that: after the master control module finishes the handshake process, the subsequent control mode further comprises the following modes:

6. The control method according to claim 4, characterized in that: the operating modes of the arbitration module further comprise the following 3 types: