CN110008162B - Buffer interface circuit, and method and application for transmitting data based on buffer interface circuit - Google Patents
Buffer interface circuit, and method and application for transmitting data based on buffer interface circuit Download PDFInfo
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Abstract
The buffer interface circuit comprises a channel one access control module, a channel two access control module, a channel selection register, a MUX unit, a synchronous one module, a synchronous two module, a dual-port buffer area and an external access buffer area control module; one end of the first channel access control module and one end of the second channel access control module are respectively and correspondingly connected with the first-level bus in the chip and the second-level bus in the chip, and the other end of the first channel access control module and the second channel access control module are connected with the dual-port buffer area after being selected by the MUX unit; the first channel access control module and the second channel access control module respectively perform control information interaction with the peripheral access buffer control module through the first synchronous module and the second synchronous module; one end of the peripheral access buffer control module is connected with the dual-port buffer, and the other end of the peripheral access buffer control module is connected with the peripheral module; the high-efficiency data interaction between the on-chip multi-level bus and the peripheral equipment is realized, the performance and the efficiency are improved on the premise of ensuring the correct and reliable transmission, and the problem of high-efficiency data transmission between the internal multi-level bus host and the peripheral interface is effectively solved.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and relates to a buffer interface circuit, a data transmission method based on the buffer interface circuit and application of the buffer interface circuit.
Background
In a large-scale multi-clock domain complex chip, the performance of the interface circuit usually determines the data access bandwidth and the system operation efficiency. Designing a high-speed interface circuit which has the advantages of speed, flexibility, reliability, simplicity and easiness in use is often a key point of chip design.
The conventional buffer interface circuit is usually implemented based on a fifo structure or a dual-port ram structure in combination with a hardware control circuit. The control strategy and implementation of the hardware control circuit determine the transmission efficiency and performance of the interface buffer circuit. In a traditional design, a time-sharing access strategy is generally adopted, control circuits of two clock domains access fifo or ram in a time-sharing mode, and interaction of data in the two clock domains is achieved on the premise that data are correct. However, this structure has a problem that data transmission efficiency is not high, and when the control structure at one end of the interface is accessing the data area, the control structure at the other end is in a waiting state, and only after the access at one end is completed, the access at the other end can be started. This is often a performance affecting bottleneck for peripherals with higher data transfer rate requirements. If a strategy that both ends of an interface access a buffer area simultaneously is adopted, how to improve transmission efficiency on the premise of ensuring consistency and correctness of data is often a key of design.
In addition, in the current large-scale SoC/MCU system, the multi-level system bus structure has become a normal state, and in some application scenarios, the peripheral module needs to support the access of the multi-level bus system, so as to design a reliable, high-efficiency, simple and easy-to-use high-speed buffer interface structure, which meets the high-efficiency transmission requirement of the multi-level bus in the system, and becomes a key problem in the design of the chip system.
Disclosure of Invention
The invention provides a buffer interface circuit, a method and application for transmitting data based on the buffer interface circuit aiming at the multi-level bus structure in a high-performance SoC/MCU system to meet the multi-level access requirement of a high-speed peripheral and aiming at the condition of low buffer access efficiency under the traditional time-sharing access strategy, so that high-efficiency data interaction between an on-chip multi-level bus and the peripheral is realized, the performance and efficiency are improved on the premise of ensuring correct and reliable transmission, and the problem of high-efficiency data transmission between an internal multi-level bus host and a peripheral interface of the existing super-large-scale complex chip such as SoC, MCU and the like is effectively solved.
The invention is realized by the following technical scheme:
a buffer interface circuit comprises a channel I access control module, a channel II access control module, a channel selection register, a MUX unit, a synchronous I module, a synchronous II module, a dual-port buffer area and an external access buffer area control module;
one end of the first channel access control module is connected with the first-level bus in the chip, the other end of the first channel access control module is connected with the dual-port buffer area after being selected by the MUX unit, and the first channel access control module is in control information interaction with the peripheral access buffer area control module through the synchronous module;
one end of the channel two access control module is connected with the in-chip secondary bus, the other end of the channel two access control module is connected with the dual-port buffer area after being selected by the MUX unit, and the channel two access control module is in control information interaction with the peripheral access buffer area control module through the synchronous two module;
one end of the peripheral access buffer control module is connected with the dual-port buffer, and the other end of the peripheral access buffer control module is connected with the peripheral module;
the dual-port buffer comprises two half-areas of BUF1 and BUF 2;
the MUX unit is controlled by a channel selection register, and SEL signals driven by the channel selection register select a first channel access control module or a second channel access control module to control signals to be gated to a dual-port buffer area;
the first channel access control module and the second channel access control module respectively comprise corresponding configuration registers and state registers;
the dual-port buffer area has 2n addresses, and the addressing range of the on-chip bus access control module and the peripheral access buffer area control module is n addresses;
in the access process, at the same time, one half area of the dual-PORT buffer area corresponds to the signal control access at the PORT1 end, the other half area corresponds to the signal control access at the PORT2 end, and in the data transmission process, the half areas of the dual-PORT buffer area controlled by the PORT1 and the PORT2 are continuously circularly switched.
Furthermore, the dual-port buffer area adopts a RAM structure with byte enabling or bit enabling, or adopts a structure that a plurality of low-bit wide RAMs are spliced into a whole RAM.
Further, the channel one access control module and the channel two access control module adopt a control mode of synchronous pulse handshake signals interaction with the peripheral access buffer control module, and the pulse handshake signals include r1, f1, gnt1, req1, r2, f2, gnt2 and req2 signals.
Furthermore, the channel one access control module is used as an on-chip primary bus host to control interaction of primary bus data and peripheral data; and the channel two access control module is used as an on-chip secondary bus slave, receives control and data of the on-chip secondary bus host and completes data interaction between the peripheral and the bus.
Furthermore, the synchronous one module and the synchronous two modules both adopt pls2pls structures.
Furthermore, the configuration register, the state register and the channel selection register are all accessed and configured by an on-chip secondary bus;
and the synchronous processing of the control signal under the primary bus clock domain and the configuration register and the state register signal under the secondary bus clock domain is completed in the channel-I access control module.
The invention also discloses a method for transmitting data from the on-chip bus to the peripheral based on the buffer interface circuit, firstly, the initialization of the channel selection register is completed, and the MUX unit determines that the first channel access control module or the second channel access control module controls the double-port buffer area;
if the channel selects the access channel and the access control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a channel-access control module;
(2) after the transmission starts, the channel-I access control module is used as an on-chip primary bus host, primary bus data are written into a BUF1 half area of the dual-port buffer area, a mark pulse signal is output after the operation is finished, configuration information is simultaneously sent to the peripheral access buffer area control module, and meanwhile, the addressing area of the channel-I access control module jumps to a BUF2 half area to continue writing second frame data; after the peripheral access buffer control module receives the mark signal and transmits the configuration information, the addressing interval of the peripheral access buffer control module jumps to a BUF1 half area, first frame data is read and transmitted to the peripheral module, after the operation is finished, the addressing interval jumps to a BUF2 half area, and a mark pulse signal is transmitted to a channel-one access control module; after the first channel access control module finishes writing in the second frame data and receives a mark signal of the first frame data transmission finished by the peripheral access buffer control module, jumping back to a BUF1 half area to continue transmitting the third frame data, and after the peripheral access buffer control module receives the second frame data finish mark of the first channel access control module, accessing a BUF2 half area to transmit the second frame data from the dual-port buffer area to the peripheral module; by parity of reasoning, the subsequent multi-frame data transmission is completed;
if the channel selects the access channel II to access the control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a second access control module of the channel;
(2) after transmission starts, the channel two access control module is used as an on-chip secondary bus slave, receives write operation of a secondary bus host to write data into a BUF1 half area of a dual-port buffer area, outputs a mark pulse signal after operation is finished, simultaneously transmits configuration information to a peripheral access buffer area control module, simultaneously jumps to a BUF2 half area from an addressing area of the channel two access control module, and continuously receives write operation of the secondary bus host to write second frame data into a BUF2 half area; after the peripheral access buffer control module receives the mark signal and transmits the configuration information, the addressing interval of the peripheral access buffer control module jumps to a BUF1 half area, first frame data is read and transmitted to the peripheral module, after the operation is finished, the addressing interval jumps to a BUF2 half area, and a mark pulse signal is transmitted to the channel two access control module; after the second frame data writing is completed by the second channel access control module and the flag signal of the first frame data transmission completed by the peripheral access buffer control module is received, the second channel access control module jumps back to the BUF1 half zone, at the moment, the second channel access control module continues to receive the write operation of the secondary bus host to transmit the third frame data, and after the second frame data completion flag of the second channel access control module is received by the peripheral access buffer control module, the peripheral access buffer control module accesses the BUF2 half zone to transmit the second frame data from the dual-port buffer zone to the peripheral module; and in the same way, the subsequent multi-frame data transmission is completed.
The invention also discloses a method for transmitting data from the peripheral to the on-chip bus based on the buffer interface circuit, firstly, the initialization of the channel selection register is completed, and the MUX unit determines that the first channel access control module or the second channel access control module controls the double-port buffer area;
if the channel selects the access channel and the access control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a channel-access control module;
(2) after the transmission starts, the channel one access control module sends a first frame request pulse mark signal to the peripheral access buffer control module and sends configuration information to the peripheral access buffer control module; after receiving the mark signal and the configuration information, the peripheral access buffer control module reads first frame data in the peripheral module and writes the first frame data into a BUF1 half area of the dual-port buffer, transmits a mark pulse signal which is completed to the channel-access control module through a synchronous module after the operation is completed, and simultaneously jumps to a BUF2 half area of an access address interval; the first channel access control module receives a first frame completion flag signal of the peripheral access buffer control module, immediately sends a second frame request pulse flag signal to the peripheral access buffer control module, the first channel access control module serves as an on-chip primary bus host, simultaneously transmits first frame data from a BUF1 half area to an on-chip primary bus, and after operation is completed, an address interval jumps to a BUF2 half area and sends a completion flag signal to the peripheral access buffer control module; after receiving the second frame request mark signal, the peripheral access buffer control module transmits the second frame data from the peripheral module to the BUF2 half-area of the dual-port buffer, and after the operation is finished, the address interval jumps to the BUF1 half-area and sends a finished mark pulse signal to the channel-one access control module; the channel I access control module completes the transmission of the first frame data from the BUF1 to the on-chip primary bus and receives a second frame transmission completion mark of the peripheral access buffer control module, and then sends a third frame request pulse signal to the peripheral access buffer control module and simultaneously transmits the second frame data from the BUF2 half area to the on-chip primary bus; by parity of reasoning, the transmission of subsequent multi-frame data is completed;
if the channel selects the access channel II to access the control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a second access control module of the channel;
(2) after the transmission starts, the channel two access control module is used as an on-chip secondary bus slave, receives the configuration of a secondary bus host and sends a first frame request pulse mark signal to the peripheral access buffer control module, and simultaneously sends configuration information to the peripheral access buffer control module; after receiving the mark signal and the configuration information, the peripheral access buffer control module reads out and writes first frame data in the peripheral module into a BUF1 half area of the dual-port buffer area, transmits a mark pulse signal after completing the operation to the channel two access control module through the synchronization two module, and simultaneously jumps to a BUF2 half area from an access address area; after receiving a first frame completion flag signal of the peripheral access buffer control module, the channel second access control module receives the configuration of a secondary bus host, transmits a second frame request pulse flag signal to the peripheral access buffer control module, simultaneously receives the reading operation of the secondary bus host, transmits first frame data from a BUF1 half area to an on-chip secondary bus, and after the operation is completed, an address interval jumps to a BUF2 half area and sends a completion flag signal to the peripheral access buffer control module; after receiving the second frame request flag signal, the peripheral access buffer control module transmits the second frame data from the peripheral module to a half-area BUF2 of the dual-port buffer, after the operation is finished, the address interval jumps to a half-area BUF1 and sends a finished flag pulse signal to the channel two access control module; after the channel second access control module finishes the transmission of the first frame data from the BUF1 to the on-chip secondary bus and receives a second frame transmission finishing mark of the peripheral access buffer control module, the channel second access control module receives the configuration of the on-chip secondary bus host and sends a third frame request pulse signal to the peripheral access buffer control module, and simultaneously receives the reading operation of the secondary bus host and transmits the second frame data from the BUF2 half area to the on-chip secondary bus; and in the same way, the transmission of the subsequent multi-frame data is completed.
The invention also discloses the application of the buffer interface circuit in the preparation of the MCU chip.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention discloses a buffer interface circuit, which comprises a channel I access control module, a channel II access control module, a MUX unit, a synchronous I module, a synchronous II module, a double-port buffer area and a peripheral access buffer area control module; the dual-port buffer area adopts a control mode of circularly switching two-stage flow water and double-half area addresses, realizes the simultaneous access of an on-chip control end and an external control end to the data buffer area, and greatly improves the data interaction efficiency of an on-chip bus and the external equipment compared with the traditional time-sharing access buffer area strategy; the access control end of the dual-PORT buffer area PORT1 is switched by the MUX unit to switch different access control channels in the chip, the SEL end of the MUX unit is controlled by the channel selection register, the configuration of the channel selection register is completed before the configuration of the configuration register and the state register of the channel one/two access control module, and the switching control of the access of the multi-level bus in the chip to the dual-PORT buffer area is realized by the simple and easy-to-realize structure.
Furthermore, the control terminals of the PORT1 and the PORT2 access different half areas respectively at the same time, and are in a two-stage pipeline access mechanism in terms of time, and the two-stage pipeline access mechanism enables the two terminals to access the data area simultaneously, so that the data transmission efficiency is greatly improved compared with the traditional time-sharing access strategy.
Furthermore, the dual-port buffer area is realized by adopting a RAM structure with byte enabling or bit enabling or a structure that a plurality of low-bit-width RAMs are spliced into a whole RAM, different access bit width requirements of different access channels are met, and compared with the read-modify-write operation realized by the whole RAM, the access time of the RAM is reduced by fifty percent, and the system access efficiency is improved.
Furthermore, the channel access control unit at the PORT1 end and the peripheral access buffer control unit at the PORT2 end adopt a control mode of interaction of the synchronized pulse handshake signals r1, f1, gnt1, req1, r2, f2, gnt2 and req2, thereby ensuring consistency and correctness in the data transmission process.
Furthermore, the first channel access control module and the second channel access control module are respectively provided with a corresponding configuration register and a corresponding status register, and the configuration register, the status register and the channel selection register are both on-chip secondary bus slaves which are accessed and configured by the on-chip secondary bus. And synchronously processing the control signal in the first-level bus clock domain and the configuration and state register related signal in the second-level bus clock domain in the first-channel access control module.
Furthermore, the synchronous first module and the synchronous second module both adopt a pls2pls structure, and cross-clock domain conversion of the single-cycle pulse signal under different clock domains is realized.
When the first channel access control module/the second channel access control module accesses the BUF1 half area, the peripheral access buffer control module accesses the BUF2 half area, when the first channel access control module/the second channel access control module jumps to the BUF2 half area, the peripheral access buffer control module jumps to the BUF1 half area, and the access time is controlled by synchronous pulse signals. The address ranges controlled by the PORTs PORT1 and PORT2 on two sides of the dual-PORT RAM at the same time correspond to two different half areas forever, the transmission efficiency is improved based on a strategy of accessing different half area data at the same time, the access conflict of the control PORTs on two ends is ensured, and efficient and reliable data transmission is realized.
The circuit structure of the invention is clear, the control logic is simple, and the invention has higher transportability and reusability, and can be applied to various chips with different architectures.
Drawings
FIG. 1 is a block diagram of a buffer interface circuit according to the present invention;
FIG. 2 is a schematic diagram of a dual port RAM access flow;
FIG. 3 is a diagram of a RAM control architecture;
fig. 4 is a circuit configuration diagram of the synchronization module.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
As shown in fig. 1, the buffer interface circuit according to the present invention is a two-stage pipeline control-based cache interface circuit spanning multiple clock domains, and includes a channel one access control module, a channel two access control module, a MUX unit, a synchronous one module, a synchronous two module, a dual-port buffer, and a peripheral access buffer control module.
One end of the channel I access control module is connected with the in-chip primary bus, the other end of the channel I access control module is connected with the dual-port buffer area after being selected by the MUX unit, and meanwhile, the channel I access control module carries out control information interaction with the peripheral access buffer area control module through the synchronous module. One end of the channel two-access control module is connected with the on-chip secondary bus, the other end of the channel two-access control module is connected with the dual-port buffer area after being selected by the MUX unit, and meanwhile, the channel two-access control module carries out control information interaction with the peripheral access buffer area control module through the synchronous two-access module.
The first channel access control module is used as an on-chip primary bus host, and the second channel access control module is used as an on-chip secondary bus slave. One typical configuration is: the channel I access control module is used as a primary bus host in the chip to realize the DMA function of data interaction between the peripheral and the primary bus in the chip; and the channel two access control module is used as a slave on the bus, receives the access of the on-chip secondary bus host and transmits data to the peripheral.
The MUX unit is gated by a SEL signal selection channel one or channel two control signal driven by a channel selection register, a dual-port buffer area is realized by adopting a synchronous dual-port SRAM, one end of the dual-port buffer area is connected with a channel one/channel two access control module control signal from an on-chip bus, and the other end of the dual-port buffer area is connected with a peripheral access buffer area control module control signal.
The dual-port buffer area has 2n addresses, including two half areas of BUF1 and BUF2, and in the access process, the two half areas respectively correspond to the control signals at two ends at the same time. The addressing range of the on-chip bus access control and the peripheral access buffer control is n addresses. For example, at a certain time, the BUF1 corresponds to the access range of n addresses for on-chip bus access control, and at this time, the BUF2 corresponds to the access range of n addresses for the peripheral access buffer control module; at another time, BUF1 corresponds to the access range of n addresses of the peripheral access buffer control module, and BUF2 corresponds to the access range of n addresses of the on-chip bus access control module.
The dual-port buffer area is realized by adopting a RAM structure with byte enabling or bit enabling or a structure that a plurality of low-bit-width RAMs are spliced into a whole RAM, so that different access bit width requirements of different access channels can be met, and the system access efficiency is improved. The specific implementation of the dual-port buffer depends on the system requirements and the specifics of the design implementation.
The other end of the peripheral access buffer control module is connected with a peripheral module data area of the chip except for the port connection, so that data interaction between the dual-port buffer area and the peripheral module is realized. In the transmission process, a double-buffer two-stage flow control mechanism is adopted, when the channel I access control module/the channel II access control module accesses the BUF1 half area, the peripheral access buffer control module accesses the BUF2 half area, when the channel I access control module/the channel II access control module jumps to the BUF2 half area, the peripheral access buffer control module jumps to the access BUF1 half area, and the access time control is realized through synchronous pulse signals. The address ranges controlled by the PORTs PORT1 and PORT2 on two sides of the dual-PORT RAM at the same time correspond to two different half areas forever, the transmission efficiency is improved based on a strategy of accessing different half area data at the same time, the access conflict of the control PORTs on two ends is ensured, and efficient and reliable data transmission is realized.
Based on the buffer interface circuit structure, the step of completely transmitting data from the on-chip bus to the peripheral equipment at one time comprises the following steps: the initialization of the channel selection register is completed firstly, and the MUX unit determines to access the first access control module of the channel or the second access control module of the channel.
If the channel selects to access the channel-access control module, the steps are as follows:
(1) completing initialization of a configuration register and a state register of a channel-one access control module;
(2) at the moment, the channel I access control module is used as a DMA (direct memory access) host of the on-chip primary bus, based on the configuration of a configuration register, the transmission starts, the channel I access control module reads the on-chip primary bus data and writes the data into BUF1 in a dual-port buffer area, after the data of the frame is written, the state f1 setting is completed (hardware maintains a period), meanwhile, necessary configuration information such as the length destination address of the transmission is output to a peripheral access buffer area control module, and f1 is transmitted to the peripheral access buffer area control module after being synchronized by a synchronization module; meanwhile, the address of the first channel access control module accessing the dual-port buffer jumps to the range of BUF2, at this time, the first channel access control unit can continue to transmit second frame data based on configuration, after the second frame transmission starts, the wbosy in the status register is set, after the second frame data is transmitted to the dual-port buffer, the addressing section of the first channel access control module jumps back to the range of BUF1, at this time, if the peripheral access buffer control unit does not finish reading BUF1 data, the wbosy signal cannot be cleared, and after the wbosy is cleared, the first channel access control module can continue to transmit bus data of a new frame to the dual-port buffer;
(3) after receiving the synchronized write transmission completion state f1, the peripheral access buffer control module samples the relevant configuration information of the frame transmission at the same time, starts to access the BUF1 half area of the dual-port buffer, reads the data of the BUF1 half area and transmits the data to the peripheral module;
(4) after the data transmission in the BUF1 is completed, the access range of the control signal of the peripheral access buffer control module is switched to the BUF2, the completion state r1 is set (hardware maintains a period), r1 is transmitted to the channel-access control module through a synchronous module, the wbuty signal is cleared, and at the moment, the channel-access control module can continuously read a new frame of bus data and write the new frame of bus data into the BUF 1.
If the channel selects the access channel II to access the control module, the steps are as follows:
(1) finishing the initialization of a configuration register and a state register of a second access control module of the channel;
(2) the channel two access control module is used as an on-chip secondary bus slave, the write access of a receiving bus writes data into BUF1 in a dual-port buffer area, after the data of the frame is written, the operation of the secondary bus on a configuration state register is received, the on-chip write transmission completion state f2 is set (hardware maintains a period), f2 is synchronized by a synchronization module and then transmitted to an external access buffer area control module, and necessary configuration information such as the length destination address of the transmission is output to the external access buffer area control module; meanwhile, the address of the channel two access control module accessing the dual-port buffer area jumps to the range of BUF2, at the moment, the channel two access control unit can continue to receive the transmission of second frame data of the on-chip secondary bus, after the transmission of the second frame starts, the wbosy in the status register is set, after the second frame data is transmitted to the dual-port buffer area, the addressing area of the channel two access control module jumps back to the range of BUF1, at the moment, if the peripheral access buffer area control unit does not finish reading BUF1 data, the wbosy signal cannot be cleared, and after waiting for wbosy to be cleared, the channel two access control module can continue to receive new bus data and transmit the new bus data to the dual-port buffer area;
(3) after receiving the synchronized write transmission completion state f2, the peripheral access buffer control module samples the relevant configuration information of the frame transmission at the same time, starts to access the BUF1 half area of the dual-port buffer, reads the data of the BUF1 half area and transmits the data to the peripheral module;
(4) after the data transmission in the BUF1 is completed, the control signal access range of the peripheral access buffer control module is switched to the BUF2, meanwhile, the completion state r2 is set (hardware maintains a period), r2 is transmitted to the channel two access control module through the synchronous two modules, the wbuty signal is cleared, and at the moment, the channel two access control module can continuously receive bus access data and write the bus access data into the BUF 1.
Based on the buffer interface circuit structure, the step of completely transmitting data from the peripheral to the on-chip bus at one time comprises the following steps: the initialization of the channel selection register is completed firstly, and the MUX unit determines to access the first access control module of the channel or the second access control module of the channel.
If the channel selects to access the channel-access control module, the steps are as follows:
(1) completing initialization of a configuration register and a state register of a channel-one access control module;
(2) hardware starts transmission based on the configuration of a configuration register, sets a req1 bit, transmits the address length and other related information of the transmission to a peripheral access buffer control module, and sets the rbusy state bit of a channel access control module at the same time;
(3) the req1 is transmitted to the peripheral access buffer control module through a synchronous module, the peripheral access buffer control module receives the req1, samples the configuration information of the current transmission at the same time, and writes the data of the current transmission into a BUF1 half area of the dual-port buffer area based on the configuration information; after the peripheral access buffer control module finishes data transmission, setting the gnt1 state (hardware maintains a period), transmitting a gnt1 signal to a channel access control module through a synchronous module, and simultaneously jumping the access range of the peripheral access buffer control module to a BUF2 half area;
(4) and the first channel access control module resets the status after receiving the synchronized gnt1 signal, sets the watch status if the configured transmission length is finished, and completes the transmission of data from the BUF1 to the first-level bus in the chip. At this time, if the configured transmission is not completed, the first channel access control module sets req1 (hardware maintains a period), transmission of second frame data is started, and rbusy is set again at this time; after receiving the synchronized req1, the peripheral access buffer control module starts to transmit the second frame data to the BUF2 half area; setting a watchdog bit of a simultaneous status register to be 1 while setting req1, jumping an access range of a channel I access control module to a BUF1 half area, and after detecting that the watchdog is 1, reading data in the BUF1 and writing the data to a destination address of a primary bus in a chip by the channel I access control module;
(5) after the second time of rbusy reset, if transmission is to be continued, continuing to perform third frame data transmission related information configuration and req1 initiation in the same step (4); if the frame data is the last frame data, the watch is set to be 1, the access range of the channel one access control module jumps to the BUF2 half area, and the channel one access control module reads the data in the BUF2 half area and writes the data to the destination address of the on-chip primary bus.
If the channel is selected as the second channel access control module, the steps are as follows:
(1) completing initialization of a configuration register and a state register of a second access control module of the channel;
(2) selecting a second access channel, starting transmission by hardware based on the configuration of a configuration register at the moment, setting a req 2bit (the hardware maintains a period), transmitting the address length and other related information of the transmission to a peripheral access buffer control module, and simultaneously setting the rbusy state bit of the second access control module;
(3) the req2 is transmitted to the peripheral access buffer control module through the synchronization module II, the peripheral access buffer control module receives the req2, samples the configuration information of the current transmission at the same time, and writes the data of the current transmission into a BUF1 half area of the dual-port buffer area based on the configuration information; after the peripheral access buffer control module finishes data transmission, setting the gnt2 state (hardware maintains a period), transmitting a gnt2 signal to a channel two access control module through a synchronization module two, and simultaneously jumping the access range of the peripheral access buffer control module to a BUF2 half area;
(4) the second channel access control module resets the status of the rbusy after receiving the synchronized gnt2 signal, if the second level bus in the chip does not have the requirement of continuously transmitting data at the moment, the configuration watch bit of the second level bus is 1, the access range of the second channel access control module jumps to a BUF1 half area, and after detecting that the watch is 1, the second level bus in the chip reads the data in the BUF1 through the second channel access control module; if data transmission requirements exist, the on-chip secondary bus can be configured with related information of second frame data transmission at the moment, a req 2bit is set after configuration is completed (hardware maintains a period), the second frame data transmission is started, and rbusy is set again at the moment; after receiving the synchronized req2, the peripheral access buffer control module starts to transmit the second frame data to the BUF2 half area; when req2 is configured, a watch bit of a state register is configured to be 1, the access range of a channel two access control module jumps to a BUF1 half area, and after the watch is detected to be 1, a chip on-chip secondary bus can read data in the BUF1 through the channel two access control module;
(5) after the second time of rbusy reset, if transmission is to be continued, continuing to perform third frame data transmission related information configuration and req2 initiation in the same step (4); if the data is the last frame data, the watch is configured to be 1, the access range of the channel two access control module jumps to a BUF2 half area, and the on-chip secondary bus host reads second frame data in the BUF2 through the channel two access control unit.
And the first channel access control module and the second channel access control module adopt the same strategy to interact with the peripheral access buffer control module. However, the access control of the first channel and the access control of the second channel respectively correspond to the hardware control circuits under the two clock domains, and different structures can be flexibly selected to realize the access control. The typical structure is that the channel two access control module is used as an on-chip secondary bus slave, receives the access of a bus host to a visible buffer (the visible depth is n) and a channel two configuration register and a status register, and realizes the data interaction of on-chip secondary bus equipment and a peripheral module; the channel I access control module is used as the on-chip primary bus host equipment, and the DMA function is realized based on the information of the channel I configuration register, so that the data interaction between the on-chip primary bus equipment and the peripheral module is completed.
The peripheral access buffer control module and the first channel access control module/the second channel access control module adopt asynchronous clock control, and the synchronous first module and the synchronous second module realize pulse signal synchronization under three clock domains. Based on the control signals r1/r2, f1/f2 and the configuration information transfer, the peripheral access buffer control module completes the transfer of data from the dual-port buffer to the peripheral. Based on the control signals gnt1/gnt2, req1/req2 and the configuration information transmission, the peripheral access buffer control module completes the transmission of data from the peripheral to the dual-port buffer.
Channel one and channel two access are mutually exclusive, and only one channel accesses the dual-port buffer area at the same time. Fig. 2 is a schematic diagram of the access flow of the dual PORT RAM, and it can be seen from fig. 2 that the control terminals of PORT1 and PORT2 access different half-blocks respectively at the same time and are in a two-stage pipeline access mechanism in terms of time, no matter the peripheral is write or read transfer. The two-stage pipelining access mechanism enables the two ends to access the data area simultaneously, and greatly improves the data transmission efficiency.
The implementation structure of the buffer will have a large impact on the transmission efficiency. The access bit width of the RAM is usually different by the on-chip multi-level bus equipment of the large-scale system chip and the peripheral access buffer control module, and if the access bit width is realized by adopting a whole RAM without bit enabling or byte enabling, the write operation with low access bit width needs to be realized by multi-step read, repair and rewrite. For example, for a 32-bit ram, if 8-bit data needs to be written, the original 32-bit data needs to be read first, the 8-bit data to be written is modified to form new 32-bit data, and finally the data is written. If the method is realized by adopting band byte enabling control or a 32-bit RAM structure formed by splicing four 8 bits, single write-in access can be completed only by controlling the byte enabling or the enabling end of each 8-bit RAM, and each operation saves at least one period compared with the read-modify-write operation.
As shown in fig. 3, the dual-port buffer can be implemented by a dual-port RAM with a total capacity of 128 × 32 bits, a half area of the BUF1 of the RAM corresponds to the physical addresses 0 to 63, a half area of the BUF2 of the RAM corresponds to the physical addresses 64 to 127, and the on-chip access and the peripheral access at the same time respectively correspond to the two half areas. The RAM is of a type with byte enable control or a mode of splicing four 8-bit RAM bodies into a 32-bit RAM body, and can realize access of various bit widths of 8bit/16bit/24bit/32bit under different channel control.
The synchronous first module and the synchronous second module both adopt pls2pls structures, and cross-clock domain conversion of single-cycle pulse signals under different clock domains is achieved. The circuit structure of the synchronous module is shown in fig. 4.
In the switching process of the MUX unit, due to the fact that control under two clock domains and switching control of clock signals exist, in order to prevent an unstable state from occurring in the switching process, hardware needs to wait for a certain time to perform RAM access operation after SEL is switched, and specific duration needs to be determined according to a design structure and application conditions.
The invention has been successfully applied to an MCU chip, in the chip, the buffer interface circuit structure is used as an interface of an on-chip primary bus AXI bus, an on-chip secondary bus AHB bus and a peripheral communication module, thereby realizing high-efficiency data interaction between on-chip multi-level bus equipment and a peripheral and ensuring the correctness of different application scene data. The MCU chip completes the procedures of simulation verification, FPGA verification and back-end realization, and the buffer interface circuit in the simulation and FPGA verification is normal in function. The invention has clear design structure, simple control logic, higher portability and reusability, and can be applied to various chips with different architectures. The technology is applicable to both civil and military fields.
Claims (9)
1. A buffer interface circuit is characterized by comprising a channel one access control module, a channel two access control module, a channel selection register, a MUX unit, a synchronous one module, a synchronous two module, a dual-port buffer area and a peripheral access buffer area control module;
one end of the first channel access control module is connected with the first-level bus in the chip, the other end of the first channel access control module is connected with the dual-port buffer area after being selected by the MUX unit, and the first channel access control module is in control information interaction with the peripheral access buffer area control module through the synchronous module;
one end of the channel two access control module is connected with the in-chip secondary bus, the other end of the channel two access control module is connected with the dual-port buffer area after being selected by the MUX unit, and the channel two access control module is in control information interaction with the peripheral access buffer area control module through the synchronous two module;
one end of the peripheral access buffer control module is connected with the dual-port buffer, and the other end of the peripheral access buffer control module is connected with the peripheral module;
the dual-port buffer comprises two half-areas of BUF1 and BUF 2;
the MUX unit is controlled by a channel selection register, and SEL signals driven by the channel selection register select a first channel access control module or a second channel access control module to control signals to be gated to a dual-port buffer area;
the first channel access control module and the second channel access control module respectively comprise corresponding configuration registers and state registers;
the dual-port buffer area has 2n addresses, and the addressing range of the on-chip bus access control module and the peripheral access buffer area control module is n addresses;
in the access process, at the same time, one half area of the dual PORT buffer area corresponds to the signal control access of the PORT1 end, the other half area corresponds to the signal control access of the PORT2 end, and in the data transmission process, the half areas of the dual PORT buffer area controlled by the PORT1 and the PORT2 are continuously and circularly switched.
2. The buffer interface circuit according to claim 1, wherein the dual port buffer employs a byte-enabled or bit-enabled RAM architecture, or a monolithic RAM architecture with multiple low bit-wide RAMs spliced together.
3. The buffer interface circuit of claim 1, wherein the channel-one access control module and the channel-two access control module each interact with the peripheral access buffer control module in a synchronized manner using pulsed handshake signals, the pulsed handshake signals including r1, f1, gnt1, req1, r2, f2, gnt2, and req2 signals.
4. The buffer interface circuit of claim 1, wherein the channel-one access control module is configured to act as an on-chip primary bus host and control interaction between primary bus data and peripheral data; and the channel two access control module is used as an on-chip secondary bus slave, receives control and data of the on-chip secondary bus host and completes data interaction between the peripheral and the bus.
5. The buffer interface circuit of claim 1, wherein the synchronous one module and the synchronous two modules both employ pls2pls structure.
6. The buffer interface circuit of claim 1, wherein the configuration register, the status register, and the channel select register are configured for on-chip secondary bus access;
and synchronously processing the control signal in the first-level bus clock domain and the configuration register and state register signal in the second-level bus clock domain in the first-channel access control module.
7. The method for transmitting data from an on-chip bus to an external device according to any one of claims 1 to 6, wherein the initialization of the channel selection register is first completed, and the MUX unit determines whether the channel one access control module or the channel two access control module controls the dual-port buffer;
if the channel selects the access channel and the access control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a channel-access control module;
(2) after the transmission starts, the channel-I access control module is used as an on-chip primary bus host, primary bus data are written into a BUF1 half area of the dual-port buffer area, a mark pulse signal is output after the operation is finished, configuration information is simultaneously sent to the peripheral access buffer area control module, and meanwhile, the addressing area of the channel-I access control module jumps to a BUF2 half area to continue writing second frame data; after the peripheral access buffer control module receives the mark signal and transmits the configuration information, the addressing interval of the peripheral access buffer control module jumps to a BUF1 half area, first frame data is read and transmitted to the peripheral module, after the operation is finished, the addressing interval jumps to a BUF2 half area, and a mark pulse signal is transmitted to a channel-one access control module; after the first channel access control module finishes writing in the second frame data and receives a mark signal of the first frame data transmission finished by the peripheral access buffer control module, jumping back to a BUF1 half area to continue transmitting the third frame data, and after the peripheral access buffer control module receives the second frame data finish mark of the first channel access control module, accessing a BUF2 half area to transmit the second frame data from the dual-port buffer area to the peripheral module; by parity of reasoning, the subsequent multi-frame data transmission is completed;
if the channel selects the access channel II to access the control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a second access control module of the channel;
(2) after transmission starts, the channel two access control module is used as an on-chip secondary bus slave, receives write operation of a secondary bus host to write data into a BUF1 half area of a dual-port buffer area, outputs a mark pulse signal after operation is finished, simultaneously transmits configuration information to a peripheral access buffer area control module, simultaneously jumps to a BUF2 half area from an addressing area of the channel two access control module, and continuously receives write operation of the secondary bus host to write second frame data into a BUF2 half area; after the peripheral access buffer control module receives the mark signal and transmits the configuration information, the addressing interval of the peripheral access buffer control module jumps to a BUF1 half area, first frame data is read and transmitted to the peripheral module, after the operation is finished, the addressing interval jumps to a BUF2 half area, and a mark pulse signal is transmitted to the channel two access control module; after the second frame data writing is completed by the second channel access control module and the flag signal of the first frame data transmission completed by the peripheral access buffer control module is received, the second channel access control module jumps back to the BUF1 half zone, at the moment, the second channel access control module continues to receive the write operation of the secondary bus host to transmit the third frame data, and after the second frame data completion flag of the second channel access control module is received by the peripheral access buffer control module, the peripheral access buffer control module accesses the BUF2 half zone to transmit the second frame data from the dual-port buffer zone to the peripheral module; and by parity of reasoning, the subsequent multi-frame data transmission is completed.
8. The method for transmitting data from a peripheral device to an on-chip bus by using a buffer interface circuit according to any one of claims 1 to 6, wherein the initialization of the channel selection register is completed first, and the MUX unit determines whether the channel one access control module or the channel two access control module controls the dual-port buffer;
if the channel selects to access the channel-access control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a channel-access control module;
(2) after the transmission starts, the channel one access control module sends a first frame request pulse mark signal to the peripheral access buffer control module and sends configuration information to the peripheral access buffer control module; after receiving the mark signal and the configuration information, the peripheral access buffer control module reads first frame data in the peripheral module and writes the first frame data into a BUF1 half area of the dual-port buffer, transmits a mark pulse signal which is completed to the channel-access control module through a synchronous module after the operation is completed, and simultaneously jumps to a BUF2 half area of an access address interval; the first channel access control module receives a first frame completion flag signal of the peripheral access buffer control module, immediately sends a second frame request pulse flag signal to the peripheral access buffer control module, the first channel access control module serves as an on-chip primary bus host, simultaneously transmits first frame data from a BUF1 half area to an on-chip primary bus, and after operation is completed, an address interval jumps to a BUF2 half area and sends a completion flag signal to the peripheral access buffer control module; after receiving the second frame request mark signal, the peripheral access buffer control module transmits the second frame data from the peripheral module to the BUF2 half-area of the dual-port buffer, and after the operation is finished, the address interval jumps to the BUF1 half-area and sends a finished mark pulse signal to the channel-one access control module; the channel I access control module completes the transmission of first frame data from the BUF1 to the on-chip primary bus and receives a second frame transmission completion mark of the peripheral access buffer control module, and then sends a third frame request pulse signal to the peripheral access buffer control module and simultaneously transmits second frame data from a BUF2 half area to the on-chip primary bus; by parity of reasoning, the transmission of subsequent multi-frame data is completed;
if the channel selects the access channel II to access the control module, the method specifically comprises the following steps:
(1) initializing a configuration register and a state register of a second access control module of the channel;
(2) after the transmission starts, the channel two access control module is used as an on-chip secondary bus slave, receives the configuration of a secondary bus host and sends a first frame request pulse mark signal to the peripheral access buffer control module, and simultaneously sends configuration information to the peripheral access buffer control module; after receiving the mark signal and the configuration information, the peripheral access buffer control module reads and writes first frame data in the peripheral module into a BUF1 half area of the dual-port buffer, transmits a mark pulse signal after completing the operation to the channel two access control module through the synchronization two module, and simultaneously jumps to a BUF2 half area of an access address interval; after receiving a first frame completion flag signal of the peripheral access buffer control module, the channel second access control module receives the configuration of a secondary bus host, transmits a second frame request pulse flag signal to the peripheral access buffer control module, simultaneously receives the reading operation of the secondary bus host, transmits first frame data from a BUF1 half area to an on-chip secondary bus, and after the operation is completed, an address interval jumps to a BUF2 half area and sends a completion flag signal to the peripheral access buffer control module; after receiving the second frame request mark signal, the peripheral access buffer control module transmits the second frame data from the peripheral module to the BUF2 half-area of the dual-port buffer, and after the operation is finished, the address interval jumps to the BUF1 half-area and sends a finished mark pulse signal to the channel two access control module; after the channel second access control module finishes the transmission of the first frame data from the BUF1 to the on-chip secondary bus and receives a second frame transmission finishing mark of the peripheral access buffer control module, the channel second access control module receives the configuration of the on-chip secondary bus host and sends a third frame request pulse signal to the peripheral access buffer control module, and simultaneously receives the reading operation of the secondary bus host and transmits the second frame data from the BUF2 half area to the on-chip secondary bus; and in the same way, the transmission of the subsequent multi-frame data is completed.
9. Use of a buffer interface circuit according to any of claims 1 to 6 in the manufacture of an MCU chip.
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