CN108228517A - I3C circuit arrangements, system and communication means - Google Patents
I3C circuit arrangements, system and communication means Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention belongs to integrated circuit fields, provide a kind of I3C circuit arrangements, system and communication means, which includes internal state machine and control interface；The control interface includes order caching module and command analysis module；The order caching module is used to obtain the control stream of user terminal transmission and be arranged in order, the control command flowed is controlled not to be performed when described, stores the control command；The command analysis module is used to obtain the state of the internal state machine, when the state of the internal state machine is executable command state, I3C output command signals are parsed into after obtaining the control command from the order caching module, the I3C output command signals are then output to the internal state machine；The internal state machine is used to the I3C output command signals being sent to I3C buses connected to it.I3C circuit arrangements provided by the invention, system and implementation method can simplify the interface of I3C controls, increase the robustness of communication system.
Description
Technical field
The invention belongs to integrated circuit fields, are to be related to a kind of I3C circuit arrangements, system and communication party more specifically
Method.
Background technology
IP core (Intellectual Property Core, abbreviation IP kernel) refers to the chip that one party provides
Design module.Designer can carry out application-specific integrated circuit or or field programmable gate array based on IP kernel
The logical design of (Field-Programmable Gate Array, abbreviation FPGA), to shorten the design cycle, improve design matter
Amount and efficiency.
With IC chip application it is growing, using I2C (Inter-Integrated Circuit) agreement
Equipment its drawback gradually appear, move Industry Processor port (Mobile Industry Processor
Interface, abbreviation MIPI) alliance proposes I3C new standard specifications.There is I3C new standards specification effective reduce to integrate electricity
The physical interface of road chip system supports the advantages of low-power consumption, high data rate and other existing interface protocols.
According to the I3C new standard specifications of MIPI alliances, I3C contains the function of more horn of plenty, if using traditional number
Word circuit control interface needs to assign control instruction, the method for transmitting data in strict accordance with clock cycle number when such as transmitting, should
Used time can be troublesome to the control of interface；On the other hand, if ready (ready) signal is configured to control signal, match to data
(valid) signal is set effective, although the control logic of user can be simplified in this way, since I3C standard functions are very abundant,
Interface quantity can be caused very huge, it is therefore desirable to control interface is optimized, it is as simple as possible in control interface
The related communication function of I3C is realized in the case of bright.
Invention content
In order to solve the above technical problem, the present invention provides a kind of I3C circuit arrangements, system and communication means, do not need to
Additional configuration signal, while without the concern for accurate bus timing, the complexity of I3C control interfaces can be reduced.
The invention is realized in this way：
First aspect present invention provides a kind of I3C circuit arrangements, including internal state machine and control interface, the control
Interface circuit processed includes：Order caching module and command analysis module.
The order caching module is used to obtain the control stream of user terminal transmission and be arranged in order, when the control
The control command of stream is not performed, stores the control command.
The command analysis module is used to obtain the state of the internal state machine, when the state of the internal state machine is
During executable command state, I3C output command signals are parsed into after obtaining the control command from the order caching module, so
The I3C output command signals are output to the internal state machine afterwards.
The internal state machine is used to the I3C output command signals being sent to I3C buses connected to it.
Specifically, the order caching module is used for after the control command is output to the internal state machine, remove
The control command.
Specifically, the I3C circuit arrangements further include state display module, the state display module is used for when described
After I3C output command signals are output to the internal state machine, obtain and show the I3C output command signals in the inside
The execution state of state machine.
Compared with prior art, I3C circuit arrangements provided by the invention obtain user terminal by control interface and send
Control stream, be output to internal state after control command is parsed into I3C output command signals according to the state of internal state machine
Machine does not need to accurate clock control and can be achieved with corresponding data communication, and I3C Interface Controllers is cumbersome when simplifying application
Property.
Second aspect of the present invention provides a kind of I3C circuit systems, which sets including I3C buses, user terminal and I3C circuits
Standby, the I3C circuit arrangements include I3C main equipments and slave device, and the I3C main equipments and/or slave device include internal state
Machine and control interface.
The control interface includes order caching module and command analysis module；
The order caching module is used to obtain the control stream that the user terminal is sent and be arranged in order, when described
The control command of control stream is not performed, stores the control command；
The command analysis module is used to obtain the state of the internal state machine, when the state of the internal state machine is
During executable command state, I3C output command signals are parsed into after obtaining the control command from the order caching module, it will
The I3C output command signals are output to the internal state machine；
The internal state machine is used to send bus signals to I3C buses connected to it；
The user terminal, for sending control stream to the I3C main equipments, when the control command of the control stream is writes behaviour
When ordering, data are passed through by the I3C bus transfers to the slave device according to the control command；When the control command
During for read operation order, data are passed through by the I3C bus transfers to I3C main equipments according to the control command.
Compared with prior art, I3C circuit systems provided by the invention, I3C circuit arrangements are obtained by control interface
The control stream that user terminal is taken to send, is output to internal state machine by control command according to the state of internal state machine, does not need to examine
Brave accurate I3C bus timings, control need to be only sent to I3C circuit arrangements flow can realize between I3C master-slave equipments
Data communicate, and simplify the control interface of I3C.
Third aspect present invention provides a kind of communication means of I3C circuits, and the communication means includes the following steps：
The communication means of the I3C circuits includes the following steps：
The I3C circuit arrangements obtain the control stream of user terminal transmission simultaneously by the order caching module of control interface
It is arranged in order, and passes through the state that command analysis module obtains the internal state machine of I3C circuit arrangements；
When the internal state machine is executable command state, the command analysis module is from the order caching module
It obtains the control command of the control stream and is parsed into I3C output command signals, and the I3C output command signals are output to
The internal state machine；
The internal state machine sends bus signals to I3C buses connected to it.
Specifically, when the control command is not performed, the I3C circuit arrangements store institute by order caching module
State control command；After the I3C output command signals are output to the internal state machine, the I3C circuit arrangements pass through shape
State display module obtains and shows execution state of the I3C output command signals in the internal state machine.
Specifically, after the control command exports, the I3C circuit arrangements remove institute by the order caching module
State control command.
Compared with prior art, the communication means of I3C circuits provided by the invention, I3C circuit arrangements pass through control interface
Circuit obtains the state of the control stream that user terminal sends and internal state machine, according to the state of internal state machine by control command solution
The drawbacks of I3C output command signals are transferred to internal state machine, have evaded I2C agreements is analysed into, simplifies user to I3C interfaces
Control, while increase the robustness of communication system.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the structure diagram of I3C circuit arrangements that one embodiment of the invention provides；
Fig. 2 is one of flow diagram of embodiment illustrated in fig. 1；
Fig. 3 is the two of the flow diagram of embodiment illustrated in fig. 1；
Fig. 4 is the status diagram of embodiment illustrated in fig. 1；
Fig. 5 is another structure diagram of embodiment illustrated in fig. 1；
Fig. 6 is the structure diagram for the I3C circuit systems that further embodiment of this invention provides；
Fig. 7 is the flow diagram of the communication means for the I3C circuits that further embodiment of this invention provides.
Wherein, each reference numeral in figure：
10-I3C circuit arrangements；20- control interfaces；30- internal state machines；40-I3C buses；50- user terminals；
101-I3C main equipments；102- slave devices；201- order caching modules；202- command analysis modules；203- state display modules.
Specific embodiment
In order to which technical problems, technical solutions and advantages to be solved are more clearly understood, tie below
Accompanying drawings and embodiments are closed, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only
To explain the present invention, it is not intended to limit the present invention.
It please refers to Fig.1, it illustrates the structure diagrams of I3C circuit arrangements provided in an embodiment of the present invention.
I3C circuit arrangements 10 include：Control interface 20 and internal state machine 30, wherein, control interface 20 wraps
Include order caching module 201 and command analysis module 202.
I3C circuit arrangements 10 can be main equipment either slave device, it should be appreciated that main equipment here is to support
The main equipment of I3C agreements, slave device can be the I2C for supporting the slave device of I3C agreements or I3C buses that can be compatible with
Slave device or it is other can be the bus compatible slave devices of I3C.
It is sent specifically, I3C circuit arrangements 10 obtain user terminal by the order caching module 201 of control interface 20
Control stream, and according to control stream sequence arranged, wherein, control stream be user terminal give control interface 20 input
Multigroup control command, data communication or the other functions being used to implement between I3C master-slave equipments；User terminal can be processor
Can also be software.
As a kind of embodiment, the control command for controlling stream is the order that I3C agreements are supported, including：Start
(START), stop (STOP), send address (ADDRESS), read-write data (DATA), interior interruption (IBI) request and be thermally connected
(HOT-JOIN) etc. the function that I3C are supported, user can control stream according to the needs of oneself according to the Standard compilation of I3C agreements,
It can realize corresponding function.
For example, please refer to Fig.2, it illustrates flow diagram of the control stream for write operation order, user can according to
Under mode write data write-in control stream：
(1) initiation command is set；
(2) input value (i.e. 7 slave device addresses and 1 read-write position) of setting main equipment；
(3) input value (i.e. 8 slave device register address) of main equipment is set；
(4) input value (i.e. 8 data) of main equipment is set；
(5) multiple data can be sent by repeating step (4)；
(6) setting is ceased and desisted order.
For another example please refer to Fig.3, it illustrates flow diagram of the control stream for read operation order, user can be according to
Following mode writes the control stream of digital independent：
(1) initiation command is set；
(2) input value (i.e. 7 slave device addresses and 1 read-write position) of setting main equipment；
(3) input value (i.e. 8 slave device register address) of main equipment is set；
(4) input value (i.e. 7 slave device addresses and 1 read-write position) of setting main equipment；
(5) input value (i.e. 8 data) of slave device is set；
(6) multiple data can be received by repeating step (5)；
(7) setting is ceased and desisted order.
When control stream control command be not performed, I3C circuit arrangements 10 by order caching module 201 store not by
The order of execution.
I3C circuit arrangements 10 obtain the state of internal state machine 30 by command analysis module 202, when internal state machine 30
State be executable command state when, from order cache module 201 obtain control command after be parsed into I3C output order letter
Number, control command is then output to internal state machine 30.
Wherein, the state of internal state machine 30 includes：Start (START), send address (ADDRESS), read-write data
(DATA), sky closes (IDLE) and stops (STOP) these states, please refers to Fig.4, it illustrates the schematic diagrames of internal state machine 30.
As a kind of embodiment, executable command state refers to that internal state machine 30 is in idle or carries out state
When redirecting, redirecting for 30 state of internal state machine is redirected according to I3C agreements, for example, internal state machine 30 is from address
(ADDRESS) it when redirecting state, obtains next control command in will being flowed from control and performs.
After I3C output command signals are output to internal state machine 30 from order parsing module 202, I3C circuit arrangements lead to
It crosses order caching module 201 and removes the control command, make to come the control command after the control command and become next and wait to hold
Capable control command.
Fig. 5 is please referred to, it illustrates another structure diagrams of control interface provided in an embodiment of the present invention.
Control interface 20 further includes：State display module 203.
After I3C output command signals are output to internal state machine 30, control interface 10 passes through state display module
203 obtain I3C output command signals in the executive condition of internal state machine 30 and are shown, can monitor control command in real time
Executive condition.
I3C circuit arrangements provided in an embodiment of the present invention obtain the control stream of user terminal transmission by control interface,
Internal state machine is output to after control command is parsed into I3C output command signals according to the state of internal state machine, is not needed to
Accurate clock control can be achieved with corresponding data communication, the triviality of I3C Interface Controllers when simplifying application.
Fig. 6 is please referred to, it illustrates the structure diagrams of I3C circuit systems provided in an embodiment of the present invention.
I3C circuit systems include I3C circuit arrangements 10, I3C buses 40 and user terminal 50, are equipped in I3C circuit arrangements 10
Control interface 20 and internal state machine 30, I3C circuit arrangements 10 include I3C main equipments 101 shown in figure and slave device
102；Wherein, I3C buses 40 are to support the bus of I3C agreements.
Control interface 20 includes order caching module 201 and command analysis module 202.
I3C main equipments 101 obtain the control stream of the transmission of user terminal 50 by order caching module 201 and carry out in order
When the control command of stream is controlled not to be performed, the control command not being performed is stored by order caching module 201 for arrangement；
The state of the internal state machine 30 of I3C main equipments 101 is obtained by command analysis module 202, when the state of internal state machine 30
For can be with exectorial state when, control command is obtained from order cache module 201 by command analysis module 202 and is solved
I3C output command signals are analysed into, I3C output command signals are then output to internal state machine 30.
Wherein, executable command state refers to that internal state machine 30 is in idle condition or carries out when redirecting of state,
Redirecting for internal state machine 30 is redirected according to I3C agreements.
Control command in control is flowed is not performed, and I3C circuit arrangements 10 are stored not by order caching module 201
The control command being performed.
After I3C output command signals are output to internal state machine 30 from order parsing module 202, I3C circuit arrangements lead to
It crosses order caching module 201 and removes the control command, make to come the control command after the control command and become next and wait to hold
Capable control command.
User terminal 50, for sending control stream to I3C main equipments 101 or slave device 102, it should be understood that user
End 50 can be processor either software.
It is to input write operation command stream when user terminal 50 sends write operation command stream to I3C circuit arrangements 10
To I3C main equipments 101, I3C main equipments 101 are sent according to control command after the extraction data of user terminal 50 by I3C buses 40
To slave device 102.
When user terminal 50 to I3C circuit arrangements 10 send read operation command stream when, be by read operation command stream according to
Need to input I3C main equipments 101 and slave device 102 respectively, when carrying out data transmission, slave device 102 according to control command from
I3C main equipments 101 are sent to by I3C buses 40 after the extraction data of user terminal 50.
As a kind of embodiment, control interface 20 further includes state display module 203, for working as I3C output lives
After signal is enabled to be output to internal state machine 30, executive condition and the progress of the I3C output command signals of internal state machine 30 are obtained
Display.
The control command that user terminal 50 is sent is the control command of I3C standards, including：Start (START), stop
(STOP), address (ADDRESS), read-write data (DATA), interior interruption (IBI) request are sent and is thermally connected (HOT-JOIN) etc.
The function that I3C is supported.User can control stream, it is possible to realize phase according to the needs of oneself according to the Standard compilation of I3C agreements
The function of answering.
As a kind of embodiment, also there is the data-interface of data acquisition between I3C circuit arrangements 10 and user terminal 50,
User terminal 50 can the gathered data from I3C circuit arrangements 10 as needed, so as to verify the correctness of transmission.
I3C circuit systems provided in an embodiment of the present invention, I3C circuit arrangements obtain user terminal by control interface and send out
Control command is output to internal state machine by the control stream sent according to the state of internal state machine, when not needing to examine brave accurate
Sequence need to only send control to I3C circuit arrangements and flow the data communication that can be realized between I3C master-slave equipments, simplify I3C
Control interface.
Fig. 7 is please referred to, it illustrates the flow diagrams of the communication means of I3C circuits provided in an embodiment of the present invention.
The communication means of I3C circuits includes the following steps：
Step S301, I3C circuit arrangement 10 obtains user terminal by the order caching module 201 of control interface 20 and sends out
The control stream that send simultaneously is arranged in order, and passes through the internal state machine that command analysis module 202 obtains I3C circuit arrangements 10
30 state.
When control command is not performed, I3C circuit arrangements 10 store the control not being performed by order caching module 201
System order.
Step S302, judge internal state machine 30 state whether be executable command state.
Wherein, executable command state refers to that internal state machine 30 is in idle condition or carries out when redirecting of state,
Redirecting for internal state machine 30 is redirected according to I3C agreements.
If judge the state of internal state machine 30 for can not exectorial state when, in return to step S301 is continued waiting for
The state transition of portion's state machine 30；If judge the state of internal state machine 30 for the state of executable command, enter step
S303。
Step S303, I3C circuit arrangement 10 obtains control by command analysis module 202 from order cache module 201
It orders and is parsed into I3C output command signals, and I3C output command signals are output to internal state machine 30.
After control command is output to internal state machine from order parsing module 202, I3C circuit arrangements 10 are slow by ordering
Storing module 201 removes the control command, and using the next command controlled in flowing as next pending order.
I3C output command signals are sent to I3C buses 40 connected to it by step S304, internal state machine 30.
As a kind of embodiment, I3C circuit arrangements 10 can also pass through the status display mould in control interface 20
Block 203 obtains control command in the executive condition of internal state machine 30 and is shown, user is made to will be seen that control command is held
Capable situation.
The communication means of I3C circuits provided in an embodiment of the present invention, I3C circuit arrangements are obtained by control interface and used
The control stream and the state of internal state machine that family end is sent, it is defeated by control command to be parsed into I3C according to the state of internal state machine
The drawbacks of going out command signal and be transferred to internal state machine, having evaded I2C agreements simplifies control of the user to I3C interfaces, simultaneously
Increase the robustness of communication system.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of I3C circuit arrangements, which is characterized in that including internal state machine and control interface；
The control interface includes order caching module and command analysis module；
The order caching module is used to obtain the control stream of user terminal transmission and be arranged in order, when the control stream
Control command is not performed, stores the control command；
The command analysis module is used to obtain the state of the internal state machine, when the state of the internal state machine is can hold
During line command state, I3C output command signals are parsed into after obtaining the control command from the order caching module, then will
The I3C output command signals are output to the internal state machine；
The internal state machine is used to the I3C output command signals being sent to I3C buses connected to it.
2. I3C circuit arrangements as described in claim 1, which is characterized in that the order caching module is additionally operable to when by described in
After control command is output to the internal state machine, the control command is removed.
3. I3C circuit arrangements as claimed in claim 2, which is characterized in that the I3C circuit arrangements further include status display mould
Block；The state display module is used for after the I3C output command signals are output to the internal state machine, is obtained and is shown
The I3C output command signals are in the execution state of the internal state machine.
4. a kind of I3C circuit systems, which is characterized in that including I3C buses, user terminal and I3C circuit arrangements；
The I3C circuit arrangements include I3C main equipments and slave device, and the I3C main equipments and/or slave device include internal state
Machine and control interface；
The control interface includes order caching module and command analysis module；
The order caching module is used to obtain the control stream that the user terminal is sent and be arranged in order, when the control
The control command of stream is not performed, stores the control command；
The command analysis module is used to obtain the state of the internal state machine, when the state of the internal state machine is can hold
During line command state, I3C output command signals are parsed into after obtaining the control command from the order caching module, by described in
I3C output command signals are output to the internal state machine；
The internal state machine is used to send bus signals to I3C buses connected to it；
The user terminal, for sending control stream to the I3C main equipments, when the control command of the control stream is ordered for write operation
When enabling, data are passed through by the I3C bus transfers to the slave device according to the control command；When the control command is reads
During operational order, data are passed through by the I3C bus transfers to I3C main equipments according to the control command.
5. control interface system as claimed in claim 4, which is characterized in that the order caching module is additionally operable to work as institute
It states after control command is output to the internal state machine, removes the control command.
6. control interface system as claimed in claim 5, which is characterized in that the I3C circuit arrangements further include state
Display module；The state display module is used for after the I3C output command signals are output to the internal state machine, is passed through
The state display module obtains the I3C output command signals in the executive condition of the internal state machine and is shown.
7. control interface system as claimed in claim 6, which is characterized in that the control command is the control of I3C standards
System order, including：Start, stop, sending address, read-write data, interior interrupt requests and thermal connection.
8. a kind of communication means of I3C circuits, which is characterized in that the communication means of the I3C circuits includes the following steps：
I3C circuit arrangements by the order caching module of control interface obtain control stream that user terminal sends and in order into
Row arrangement, and pass through the state that command analysis module obtains the internal state machine of I3C circuit arrangements；
When the internal state machine is executable command state, the command analysis module is obtained from the order caching module
The control command of the control stream is simultaneously parsed into I3C output command signals, and the I3C output command signals is output to described
Internal state machine；
The internal state machine sends I3C output command signals to I3C buses connected to it.
9. the communication means of control interface as claimed in claim 8, which is characterized in that when the control command is not held
During row, the I3C circuit arrangements store the control command by order caching module；When the I3C output command signals are defeated
Go out to after the internal state machine, the I3C circuit arrangements are obtained by state display module and show the I3C outputs order
Signal is in the execution state of the internal state machine.
10. the implementation method of control interface as claimed in claim 9, which is characterized in that when the control command exports
Afterwards, the I3C circuit arrangements remove the control command by the order caching module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110489361A (en) * | 2019-07-31 | 2019-11-22 | 广东高云半导体科技股份有限公司 | The I3C interface circuit of compatible SRAM bus |
| CN113031486A (en) * | 2021-03-18 | 2021-06-25 | 深圳市度信科技有限公司 | FPGA-based I3C logic controller implementation method, I3C read-write test device and system |
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| CN110489361A (en) * | 2019-07-31 | 2019-11-22 | 广东高云半导体科技股份有限公司 | The I3C interface circuit of compatible SRAM bus |
| CN110489361B (en) * | 2019-07-31 | 2020-08-25 | 广东高云半导体科技股份有限公司 | I3C interface circuit compatible with SRAM bus |
| CN113031486A (en) * | 2021-03-18 | 2021-06-25 | 深圳市度信科技有限公司 | FPGA-based I3C logic controller implementation method, I3C read-write test device and system |
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