CN114489220A

CN114489220A - Low-power-consumption over-temperature protection circuit without operational amplifier and reference

Info

Publication number: CN114489220A
Application number: CN202210001743.5A
Authority: CN
Inventors: 樊华; 谢华江; 岳慧超; 冯全源; 苏华英; 王国松
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2022-05-13
Anticipated expiration: 2042-01-04
Also published as: CN114489220B

Abstract

The invention discloses a low-power-consumption over-temperature protection circuit without operational amplifier and reference, and relates to the field of microelectronics and solid electronics. The invention mainly uses the voltage which is negatively correlated with the temperature as a signal input source, the conversion is carried out by a front-stage detection circuit, and a Schmitt trigger is added at the rear stage, thereby increasing the threshold window. The invention is characterized in that the competition current capability of the PMOS tube and the MOS tube is changed by injecting voltage and current related to the temperature, so that the jump of the input signal is related to the temperature. The temperature-adjustable circuit is simple in structure, does not need extra reference voltage and a comparator, saves power consumption and circuit area, is set to be in an adjustable temperature protection range, reduces the influence of a power supply and a process, and increases a temperature threshold window, so that the stability of the whole circuit is ensured.

Description

Low-power-consumption over-temperature protection circuit without operational amplifier and reference

Technical Field

The invention relates to the field of microelectronics and solid-state electronics, in particular to an over-temperature protection related circuit in the field.

Background

With the increasing development of integrated circuits, the performance and the integration level of the chip are greatly improved, and meanwhile, higher requirements are provided for the safety and the reliability of the chip, so that the guarantee of the safe, stable and reliable operation of the chip becomes a great concern in the industry, and the chip receives wide attention. Among them, the temperature is one of the factors in the PVT (process, voltage, temperature) and is a critical point affecting the stability of the chip. When the chip and the surrounding circuits run, the internal temperature of the chip rises due to power consumption, short circuit, energy consumption caused by load change and temperature change of the surrounding environment, if a certain threshold value is reached, irreversible damage is caused to related devices, so that the service life and the performance of the chip are greatly reduced, and the performance and the stability of the whole system are further influenced, therefore, the working temperature of the circuit needs to be maintained within a certain range in the design of the related chip, an over-temperature protection circuit needs to be integrated in the chip, and the whole chip gives a signal to stop the system when the temperature is too high; when the temperature returns to normal, the system is enabled to return to normal operation by outputting signals, and a threshold window with a certain size needs to be set between the stop operation state and the recovery state, so that the phenomenon that the power consumption and the system are frequently turned on and off due to repeated jumping of signal output, the abnormal function of the whole system and the loss of components are caused is prevented. Therefore, it is very important to see the characteristics of the over-temperature protection circuit.

The traditional over-temperature protection circuit structure is generally divided into two major structures, the first structure combines a bipolar transistor and a device with a positive temperature coefficient, such as a voltage stabilizing diode, and the like, so as to play a role of controlling the switch of a related circuit and generate the required control signal, the over-temperature protection circuit has a simple structure, but has low precision and poor dynamic range, is greatly influenced by the process, can generate large error, and is easy to cause an output signal to generate a thermal oscillation phenomenon; the second class of over-temperature protection circuits generally requires a reference voltage and a constant temperature-dependent voltage, such as the V of a transistor_BEOr the voltage values of other components are compared by adding a comparator, so that the required temperature signal is obtained, the temperature detection of the structure is relatively accurate, the complexity of the circuit is increased, and an additional band gap reference circuit and the comparator are required, so that the whole over-temperature protection is realizedThe power consumption and area of the circuit increase.

Disclosure of Invention

The invention provides a new circuit structure and a new method aiming at the problems of the traditional over-temperature protection circuit method.

The over-temperature protection circuit without the operational amplifier and the reference voltage has certain advantages in power consumption compared with the traditional structure. The main content of the device comprises a basic detection structure unit which is four cascaded MOS (metal oxide semiconductor) tubes, wherein the first PMOS tube is connected with a voltage which is negatively related to the temperature, and the second PMOS tube is connected with a clock control signal; the third and fourth NMOS transistors, wherein the third NMOS transistor is connected with a clock control signal, and the fourth PMOS transistor is connected with a voltage which is in negative correlation with the temperature; and the drain electrode of the second PMOS tube, namely the drain electrode of the third NMOS tube, is connected with a subsequent Schmidt trigger structure through a lead wire, so that a threshold window is generated, the repeated jumping of the output of the whole over-temperature protection system is avoided, and finally the output of the circuit is output through a cascade inverter playing a buffering role, namely the output signal of the over-temperature protection circuit. The structure aims to adjust the threshold temperature of over-temperature protection, so that the overall robustness is improved, and the influence of a power supply and a process on a system is reduced.

The invention has the technical scheme that the low-power consumption over-temperature protection circuit without operational amplifier and reference comprises: preceding stage and back stage, the preceding stage includes: an M1 integer, a fifth PMOS transistor M2, a first NMOS transistor M3 and an M4 integer, wherein the M1 integer includes: the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c, the fourth PMOS transistor M1d, and the M4 integrally include: a second NMOS transistor M4a, a third NMOS transistor M4b, a fourth NMOS transistor M4c, and a fifth NMOS transistor M4 d; the first PMOS tube M1a, the fifth PMOS tube M2, the first NMOS tube M3 and the second NMOS tube M4a are sequentially connected in series; the grid electrodes of the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c and the fourth PMOS transistor M1d are connected in common and connected with a voltage VCTAT signal which is in negative correlation with the temperature; the drains of the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c and the fourth PMOS transistor M1d are connected in common; the source electrode of the first PMOS transistor M1a is connected with a power supply signal VDD, the source electrode of the first PMOS transistor M1a is separated from the source electrode of the second PMOS transistor M1b by a switch S1, the source electrode of the second PMOS transistor M1b is separated from the source electrode of the third PMOS transistor M1c by a switch S2, and the source electrode of the third PMOS transistor M1c is separated from the source electrode of the fourth PMOS transistor M1d by a switch S3;

the grid electrode of the fifth PMOS tube M2 is connected with a clock signal CLKN;

the grid electrode of the first NMOS tube M3 is connected with a clock signal CLK;

the gates of the second NMOS transistor M4a, the third NMOS transistor M4b, the fourth NMOS transistor M4c and the fifth NMOS transistor M4d are connected in common and connected with a voltage VCTAT signal which is in negative correlation with temperature; the source electrodes of the second NMOS transistor M4a, the third NMOS transistor M4b, the fourth NMOS transistor M4c and the fifth NMOS transistor M4d are connected in common and grounded; the source electrode of the second NMOS transistor M4a is isolated from the source electrode of the third NMOS transistor M4b by a switch S4, the source electrode of the third NMOS transistor M4b is isolated from the source electrode of the fourth NMOS transistor M4c by a switch S4, and the source electrode of the fourth NMOS transistor M4c is isolated from the source electrode of the fifth NMOS transistor M4d by a switch S6;

the latter stage comprises: a sixth PMOS transistor M5, a seventh PMOS transistor M7, an eighth PMOS transistor M9, a sixth NMOS transistor M6, a seventh NMOS transistor M8, and an eighth NMOS transistor M10; the grid electrode of the sixth PMOS tube M5 and the grid electrode of the sixth NMOS tube M6 are connected with the drain electrode of the fifth PMOS tube M2 after being connected in common; the source electrode of the sixth PMOS transistor M5, the source electrode of the seventh PMOS transistor M7 and the source electrode of the eighth PMOS transistor M9 are connected in common and connected with a power supply signal VDD; the drain electrode of the sixth PMOS tube M5, the drain electrode of the seventh PMOS tube M7, the gate electrode of the eighth PMOS tube M9, the drain electrode of the sixth NMOS tube M6, the drain electrode of the seventh NMOS tube M8 and the gate electrode of the eighth NMOS tube M10 are connected in common; the source electrode of the sixth NMOS transistor M6, the source electrode of the seventh NMOS transistor M8 and the source electrode of the eighth NMOS transistor M10 are connected in common and grounded; and the grid electrode of the seventh PMOS tube M7, the drain electrode of the eighth PMOS tube M9, the grid electrode of the seventh NMOS tube M8 and the drain electrode of the eighth NMOS tube M10 are connected in common and then serve as the output end of the over-temperature protection circuit.

The element and the whole structure have a method for calibrating the offset of the analog front end of the temperature sensor based on the switched capacitor integrator, a certain time period is additionally consumed in the elimination process, excessive complex circuit structures and excessive power consumption areas are not needed, and self body structures are utilized for self calibration more. In addition, compared with the traditional calibration method, the calibration method can be used in a superposition mode, so that the performance of the circuit is further optimized, the overall calibration efficiency and accuracy are both advantageous, and the additional operational amplifier and the filter are reduced when the calibration method is used alone.

Compared with the two traditional circuit methods, the over-temperature protection circuit structure is simple in structure, does not need additional reference voltage and a comparator, saves power consumption and circuit area, is set to be in an adjustable temperature protection range, reduces influences of a power supply and a process, and increases a temperature threshold window, so that stability of the whole circuit is guaranteed. Compared with the over-temperature protection circuit provided by document 1[ plum town, von full source ], a low-power-consumption CMOS over-temperature protection circuit design and application technology, 2017,44(01):14-17+22 ] and document 2[ Gexingjie, Lufeng, 0.25 μm CMOS novel over-temperature protection circuit design, electronic and packaging, 2018,18(06):22-25 ].

Drawings

Fig. 1 is a schematic structural diagram of an over-temperature protection circuit according to the present invention.

Fig. 2 is a simulation result of the over-temperature protection circuit of the present invention after the power supply voltage changes from 3.3V to 5.5V and the influence is eliminated by circuit trimming.

FIG. 3 is a diagram showing simulation results of the quiescent operating current of the over-temperature protection circuit of the present invention at a temperature around the trip point.

Detailed Description

The invention is explained in detail below with reference to the drawings:

the contents and simulation results of the invention take HGRACE 0.11 μm technology as an example, and the following circuit structure based on the technology has the following main contents in over-temperature protection and practical application; fig. 1 is a diagram of an excess temperature protection circuit without operational amplifier and band gap according to the present invention, which is suitable for the related chips requiring low power consumption for the excess temperature protection circuit, requiring complexity and area, and being capable of being modified by subsequent operations, and is composed of a front stage detection circuit and a rear stage schmitt trigger, wherein the front stage amplification circuit is four cascaded MOS transistors, the first and second are PMOS transistors, the first PMOS transistor is connected to a voltage negatively correlated to temperature, and the second PMOS transistor is connected to a clock control signal; the third and fourth NMOS transistors, wherein the third NMOS transistor is connected with a clock control signal, and the fourth PMOS transistor is connected with a voltage which is in negative correlation with the temperature; and the drain electrode of the second PMOS tube, namely the drain electrode of the third NMOS tube, is connected with a subsequent Schmidt trigger structure through a lead wire, so that a threshold window is generated, the repeated jumping of the output of the whole over-temperature protection system is avoided, and finally the output of the circuit is output through a cascade inverter playing a buffering role, namely the output signal of the over-temperature protection circuit.

The specific working mode is analyzed by the change from low temperature to high temperature, and through reasonable setting of the adjusting circuit, the value of VCTAT signal is larger at low temperature, so that the opening degree of the upper PMOS transistor M1 is lower than that of the lower NMOS transistor M4, and the voltage of the middle output end is pulled down to GND (ground) signal, namely low level is output; and as the temperature gradually rises, the VCTAT signal gradually falls, when the critical point of competing current between the PMOS transistor M1 and the NMOS transistor M4 is reached, the output signal starts to generate reverse jump, and the value of the VCTAT signal is smaller at this time, so the opening degree of the lower NMOS transistor M4 is not as high as that of the upper PMOS transistor M1, the voltage of the middle output end is pulled up to the VDD power supply signal, i.e., a high level is output, and the circuit is turned over. And considering that the temperature change is relatively slow, the over-temperature protection circuit can be turned on and off at regular time by setting the CLK clock signal, so that the power consumption of the whole system is reduced, when the CLK is high level, both M2 and M3 are turned on, and the front stage operates normally, and when the CLK is low level, both M2 and M3 are turned off, and the front stage stops operating and outputs a low level signal. After the parameters and the structure of the circuit are determined, the relative capacity of competing current is not changed greatly under the condition that the process corner, the temperature and the power supply voltage are relatively fixed, so that a signal which is fixedly output and overturned along with the temperature change is obtained through a front-stage circuit. In the application, the conditions of voltage change, process deviation and the like are considered, a plurality of MOS (metal oxide semiconductor) tubes can be connected in parallel at the positions of M1 and M4, the pull-up capability of the PMOS tube and the pull-down capability of the NMOS tube are adjusted by regulating the connection of the MOS tubes, if the turn-off temperature is low, analysis shows that the pull-up capability of the PMOS tube is higher than the pull-down capability of the NMOS tube in advance due to the process deviation and the power supply voltage change, so that the parallel tube connected to M4 needs to be increased, the parallel tube connected to M1 is reduced, the pull-down capability is enhanced, the pull-up capability is weakened, and the temperature of keeping a low level is increased; on the contrary, if the turn-off temperature becomes high, the pull-down capability of the NMOS transistor is inevitably higher than that of the PMOS transistor due to process variation and power supply voltage variation, so that the parallel transistors incorporated in M1 need to be increased, the parallel transistors incorporated in M4 need to be decreased, the pull-up capability needs to be enhanced, the pull-down capability needs to be weakened, and the temperature for keeping the low level needs to be reduced. The output signal of the front stage circuit is used as an input signal, for two input signals with different changing directions of negative descending and positive ascending, the Schmitt trigger has different threshold voltages, so that when the temperature changes from low to high and from high to low, namely the positive and negative directions of the input signal change, corresponding to different thresholds, the final OUT signal has a certain hysteresis window, the phenomenon that the circuit jumps repeatedly near a temperature point to cause irreversible loss is avoided, the size of the specific hysteresis window can be adjusted according to the practical circuit application requirements on the structure of the Schmitt trigger and the parameters of an MOS (metal oxide semiconductor) transistor, the hysteresis temperature is set to be about 3 ℃, and the accurate value of the hysteresis window does not influence the performance of the whole circuit.

Fig. 2 is a simulation result of the over-temperature protection circuit after the power supply voltage changes from 3.3V to 5.5V and the influence is eliminated by circuit trimming, and the principle of the simulation result is analyzed as described above. It can be seen that the circuit can complete jump under the power supply voltage of 3.3V and 5.5V, and the error change of the turn-off temperature can be adjusted to be within 1 ℃.

Fig. 3 shows the magnitude of the quiescent operating current of the total circuit when the over-temperature protection circuit operates at a supply voltage of 3.3V, which is about 2.27 μ a, and it can be seen that the total circuit current suddenly increases during level inversion, but then returns to a low power consumption state.

The over-temperature protection circuit performance versus ratio is shown in table 1 below.

Table 1: over-temperature protection circuit comparison

	Document 1	Document 2	The invention
				Process/. mu.m	0.18	0.25	0.11
Structure and whether there is operational amplifier	The structure is complex, is	Moderate structure whether	Simple structure, no
				Static power consumption/. mu.A	3.12	/	2.27
Retardation temperature/. degree.C	12.11	21	3.00
				Influence of supply voltage on the turn-off point/. degree.C	1.75	1.7	Less than 1

Claims

1. A kind of no operational amplifier is not a low-power consumption over-temperature protection circuit of the benchmark, this circuit includes: preceding stage and back stage, the preceding stage includes: an M1 integer, a fifth PMOS transistor M2, a first NMOS transistor M3 and an M4 integer, wherein the M1 integer includes: the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c, the fourth PMOS transistor M1d, and the M4 integrally include: a second NMOS transistor M4a, a third NMOS transistor M4b, a fourth NMOS transistor M4c, and a fifth NMOS transistor M4 d; the first PMOS tube M1a, the fifth PMOS tube M2, the first NMOS tube M3 and the second NMOS tube M4a are sequentially connected in series; the grid electrodes of the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c and the fourth PMOS transistor M1d are connected in common and connected with a voltage VCTAT signal which is in negative correlation with the temperature; the drains of the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c and the fourth PMOS transistor M1d are connected in common; the source electrode of the first PMOS transistor M1a is connected with a power supply signal VDD, the source electrode of the first PMOS transistor M1a is separated from the source electrode of the second PMOS transistor M1b by a switch S1, the source electrode of the second PMOS transistor M1b is separated from the source electrode of the third PMOS transistor M1c by a switch S2, and the source electrode of the third PMOS transistor M1c is separated from the source electrode of the fourth PMOS transistor M1d by a switch S3;