CN114696587A - Power supply monitoring circuit and switching power supply - Google Patents
Power supply monitoring circuit and switching power supply Download PDFInfo
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- CN114696587A CN114696587A CN202011574949.4A CN202011574949A CN114696587A CN 114696587 A CN114696587 A CN 114696587A CN 202011574949 A CN202011574949 A CN 202011574949A CN 114696587 A CN114696587 A CN 114696587A
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 48
- 238000005070 sampling Methods 0.000 claims abstract description 23
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 description 7
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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Abstract
The invention discloses a power supply monitoring circuit and a switching power supply, wherein the power supply monitoring circuit comprises: the core sampling control module is used for outputting a first control signal with a first logic level according to the level state of the power supply voltage; the charge pump is used for generating corresponding reference voltages according to the effective level states of different reset indicating signals; the logic level conversion module is used for converting the logic level of the first control signal according to the reference voltage so as to output a second control signal with a second logic level; and the output module comprises at least one switching tube, the grid electrode receives a second control signal, the switching tube is used for outputting an effective reset indicating signal at the drain electrode when the switching tube is conducted, and the switching tube is a depletion transistor. The circuit can normally work when the power supply voltage is 0V, and has the advantages of small occupied area, high stability and high accuracy.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a power supply monitoring circuit and a switching power supply.
Background
For circuits such as power supply monitoring chips, the output pin is required to have the capability of providing a correct indication voltage even at a power supply voltage as low as possible, and to provide an output impedance low enough. In order to prevent power failure, a power supply monitoring chip is applied to monitor the system power supply voltage in most circuit systems, and when the power supply voltage is lower than the system working voltage, the power supply monitoring chip outputs a logic high level or a logic low level to a core circuit to realize circuit reset. This requires that the power monitoring chip can provide a correct reset indication to the subsequent chip of the system at an extremely low power voltage, which requires that the reset chip can operate at an extremely low voltage.
A typical circuit configuration of a power supply monitor chip circuit (hereinafter, simply referred to as a power supply monitor circuit) 10 is shown in fig. 1, and includes an output circuit 11 and a core sampling control circuit 12 connected to the output circuit 11, where the output circuit 11 includes a transistor M10 and a transistor M11 connected in series between a power supply voltage VCC input terminal and a ground GND, and gates of the transistor M0 and the transistor M1 are connected to an output terminal of the core sampling control circuit 12. Taking the low level as an example of the active reset level, in order to solve the foregoing problems, the conventional solutions generally increase the width-to-length ratio of the transistor M10 and the transistor M11 in the output circuit 11, reduce the on-resistance of the output circuit 11, and externally connect the external resistor R at the output terminal. For the scheme, the increase of the external resistor R can increase the overall power consumption of the system. Increasing the width-to-length ratio of the transistor M10 and the transistor M11 in the output circuit 11 not only increases the chip area, but also does not completely solve the problem of low voltage operation, which generally requires the core circuit to be able to operate at low voltage.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a power supply monitoring circuit and a switching power supply, wherein the power supply monitoring circuit can normally work when the power supply voltage is 0V, and has the advantages of small occupied area, high stability and high accuracy.
According to a first aspect of the present disclosure, there is provided a power supply monitoring circuit comprising: the core sampling control module is connected with a power supply voltage input end and used for outputting a first control signal with a first logic level according to the level state of the power supply voltage;
the charge pump is used for generating corresponding reference voltages according to the effective level states of different reset indicating signals;
a logic level conversion module, connected to the output module, the core sampling control module and the charge pump, respectively, for converting a logic level of the first control signal according to the reference voltage to output a second control signal having a second logic level;
an output module, configured to provide a reset indication signal according to the second control signal, where the reset indication signal is used to represent a level state of the power supply voltage,
the output module comprises at least one switching tube, a grid electrode receives the second control signal, the switching tube is used for outputting an effective reset indication signal at a drain electrode when the switching tube is conducted, and the switching tube is a depletion transistor.
Optionally, the output module includes: a first switch tube and a second switch tube,
the first switch tube and the second switch tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the first switch tube receives the first control signal or the second control signal, the grid electrode of the second switch tube receives the second control signal,
the first switch tube is an enhancement type PMOS transistor, the second switch tube is a depletion type NMOS transistor, the output module outputs the reset indicating signal at the drain electrode of the second switch tube, and the reset indicating signal is effective when in a low level state.
Optionally, the output module includes: a first resistor and a third switch tube,
the first resistor and the third switching tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the third switching tube receives the second control signal,
the third switching tube is a depletion type NMOS transistor, the output module outputs the reset indicating signal at the drain of the third switching tube, and the reset indicating signal is effective when in a low level state.
Optionally, the output module includes: a fourth switching tube and a fifth switching tube,
the fourth switching tube and the fifth switching tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the fourth switching tube receives the first control signal or the second control signal, the grid electrode of the fifth switching tube receives the second control signal,
the fourth switch tube is a depletion type PMOS transistor, the fifth switch tube is an enhancement type NMOS transistor, the output module outputs the reset indicating signal at the drain electrode of the fourth switch tube, and the reset indicating signal is effective when in a high level state.
Optionally, the output module includes: a sixth switch tube and a second resistor,
the sixth switching tube and the second resistor are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the sixth switching tube receives the second control signal,
the sixth switching tube is a depletion type PMOS transistor, the output module outputs the reset indication signal at the drain of the sixth switching tube, and the reset indication signal is effective when in a high level state.
Optionally, the charge pump is to generate a reference voltage having a negative voltage.
Optionally, the charge pump is configured to generate a reference voltage having a voltage greater than the supply voltage.
Optionally, when the first logic level is the power supply voltage, the second logic level is also the power supply voltage;
when the first logic level is 0, the second logic level is the reference voltage.
Optionally, when the first logic level is the power supply voltage, the second logic level is 0;
when the first logic level is 0, the second logic level is the reference voltage.
According to a second aspect of the present disclosure, there is provided a switching power supply comprising a control circuit and a power circuit, the control circuit comprising a control module and a power supply monitoring circuit as described above.
The invention has the beneficial effects that: the present disclosure relates to a power supply monitoring circuit and a switching power supply, in which a depletion transistor is used as an output stage transistor for outputting a reset indication signal, and due to the conduction characteristic of the depletion transistor, the power supply monitoring circuit can be normally conducted even when the power supply voltage is low, and correctly outputs an effective reset indication signal. Meanwhile, the power supply monitoring circuit is also provided with a charge pump and a logic level conversion module, and the logic level conversion module is used for converting the logic level of the control signal output to the switching tube based on the reference voltage output by the charge pump, so that the switching tube can still be correctly turned on and off after the power supply voltage rises and the core circuit normally works, and the accuracy of the output reset indication signal is effectively ensured.
On the other hand, the circuit can realize correct reset indication signal output under the condition that an external resistor is not connected, and therefore the occupied area is small.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram showing a circuit configuration of a power supply monitoring circuit in the prior art;
FIG. 2 shows a block diagram of a power supply monitoring circuit provided according to an embodiment of the disclosure;
fig. 3 shows a schematic circuit configuration diagram of a power supply monitoring circuit provided according to a first embodiment of the present disclosure;
fig. 4 shows a schematic circuit configuration diagram of a power supply monitoring circuit provided according to a second embodiment of the present disclosure;
fig. 5 shows a schematic circuit configuration diagram of a power supply monitoring circuit provided according to a third embodiment of the present disclosure;
fig. 6 shows a schematic circuit structure diagram of a power supply monitoring circuit provided according to a fourth embodiment of the present disclosure.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 shows a block diagram of a power supply monitoring circuit provided according to an embodiment of the present disclosure.
As shown in fig. 2, in the present disclosure, the power supply monitoring chip mainly includes a power supply voltage VCC input terminal, an output terminal OUT, and a ground GND. And, the power monitoring circuit 20, which is an internal circuit structure of the power monitoring chip, mainly includes a core sampling control module 21, a charge pump 22, a logic level conversion module 23, and an output module 24.
The core sampling control module 21 and the output module 24 are respectively connected between the power supply voltage VCC input terminal and the ground GND, the logic level conversion module 23 is connected between the output terminal of the core sampling control module 21 and the control terminal of the output module 24, and the charge pump 22 is connected with the logic level conversion module 23.
The core sampling control module 21 is configured to output a first control signal having a first logic level according to a level state of the power supply voltage VCC. The charge pump 22 is used for generating corresponding reference voltages according to the active level states of different reset indication signals. The logic level converting module 23 is configured to convert a logic level of the first control signal according to the reference voltage to output a second control signal having a second logic level. The output module 24 is configured to provide a reset indication signal according to the second control signal, where the reset indication signal is used to indicate a level state of the power supply voltage VCC (e.g., when the reset indication signal is valid, the power supply voltage VCC is less than a threshold voltage, and when the reset indication signal is invalid, the power supply voltage VCC is greater than the threshold voltage). Optionally, the valid reset indication signal may also be used to trigger the core circuit generating the power supply voltage VCC to reset.
In the present disclosure, the output module 24 includes at least one switching tube, a gate of the switching tube receives the second control signal, and the switching tube is configured to output an effective reset indication signal at a drain of the switching tube when the switching tube is turned on. And further, in the present disclosure, the switching tube is a depletion transistor. In this manner, the power supply monitoring circuit 20 is enabled to be normally turned on even when the power supply voltage is low based on the on characteristic of the depletion transistor, and correctly outputs an effective reset instruction signal.
Meanwhile, the reference voltage generated by the charge pump 22 has a logic level capable of cutting off the switching tube, so that the logic level conversion module 23 converts the logic level of the control signal output to the switching tube based on the reference voltage output by the charge pump 22, so that the switching tube can be correctly turned on and off after the power supply voltage VCC rises and the core circuit normally works, and the accuracy of the reset indication signal output in the change process of the power supply voltage VCC is effectively ensured.
The following describes a specific operation principle of the power monitoring circuit 20 in the present disclosure with reference to a specific embodiment:
example one
In this embodiment, the reset indication signal is active in a low state.
Referring to fig. 3, the output module 24 includes: a first switch tube MP0 and a second switch tube MN 0. The first switch tube MP0 and the second switch tube MN0 are sequentially connected in series between the power voltage VCC input terminal and the ground GND, the gate of the first switch tube MP0 receives the first control signal or the second control signal a, and the gate of the second switch tube MN0 receives the second control signal a. The first switch MP0 is an enhancement PMOS transistor, and the second switch MN0 is a depletion NMOS transistor. The output module 24 outputs a reset indication signal to the output terminal OUT at the drain of the second switch MN 0.
Further, in the present embodiment, the charge pump 22 generates the reference voltage with the negative voltage VSS.
The specific working principle is as follows:
1) when the voltage value of the power supply voltage VCC is very low and is lower than the normal operating voltage of the core sampling control module 21, none of the core sampling control module 21, the charge pump 22 and the logic conversion module 23 operate. At this time, the logic level of the second control signal a received by the control terminal of the output module 24 is almost 0V.
Since the depletion NMOS transistor can be turned on at 0V, the first switch MP0 is in an off state and the second switch MN0 is in an on state, so that the reset indication signal outputted from the output module 24 to the output terminal OUT is in an active state with a low level. Meanwhile, the second switch tube MN0 in the on state can provide an extremely low on-resistance, so that when the power supply voltage VCC is in a range from 0V to the lowest working voltage of the core sampling control module 21, the output terminal OUT always provides a low-resistance circuit to ground, so that the voltage of the output terminal OUT is 0V, and thus a low-level effective reset indication signal is correctly output.
2) When the power supply voltage VCC rises to the working voltage of the core sampling control module 21, the charge pump 22 and the logic conversion module 23 all start to work normally. The charge pump 22 provides a negative voltage VSS to ground as a reference voltage, and the voltage is lower than the cut-off level of the depletion mode second switch MNO.
At this time, if the power supply voltage VCC is smaller than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage VCC, and the second logic level of the second control signal a output by the logic level conversion module 23 is also the power supply voltage VCC, so that the second control signal a can control the first switch tube MP0 to be in the off state, and control the second switch tube MN0 to be in the on state, so that the reset indication signal output by the output module 24 to the output end OUT is in the low-level effective state.
At this time, if the power supply voltage VCC is greater than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage 0V, and the second logic level of the second control signal a output by the logic level conversion module 23 is converted to the negative voltage VSS of the reference voltage, so that the second control signal a can control the first switch tube MP0 to be in the on state, and control the second switch tube MN0 to be in the off state, so that the reset indication signal output by the output module 24 to the output end OUT is in the high-level invalid state. That is, the reset function of the reset instruction signal is released.
As can be seen from the above description, the power monitoring circuit 20 disclosed in this embodiment can operate when the power voltage VCC is 0V, so as to provide a correct reset indication signal for the system. Meanwhile, after each module of the circuit 20 works, a correct reset indication signal can still be provided, so that the correct on and off of the switching power supply core circuit is controlled and realized.
Example two
In this embodiment, the reset indication signal is active in a high state.
Referring to fig. 4, the output module 24 includes: fourth switching tube MP1 and fifth switching tube MN 1. The fourth switching tube MP1 and the fifth switching tube MN1 are sequentially connected in series between the power supply voltage VCC input terminal and the ground GND, the gate of the fourth switching tube MP1 receives the first control signal or the second control signal a, and the gate of the fifth switching tube MN1 receives the second control signal a. The fourth switch MP1 is a depletion PMOS transistor, and the fifth switch MN1 is an enhancement NMOS transistor. And the output module 24 outputs a reset indication signal to the output terminal OUT at the drain of the fourth switch MP 1.
Further, in the present embodiment, the charge pump 22 generates the reference voltage greater than the power supply voltage VCC.
The specific working principle is as follows:
1) when the voltage value of the power supply voltage VCC is very low and is lower than the normal operating voltage of the core sampling control module 21, none of the core sampling control module 21, the charge pump 22 and the logic conversion module 23 is operated. At this time, the logic level of the second control signal a received by the control terminal of the output module 24 is almost 0V.
Since the depletion PMOS transistor can be turned on at 0V, the fourth switching transistor MP1 is in an on state and the fifth switching transistor MN1 is in an off state at this time, so that the reset indication signal output to the output terminal OUT by the output module 24 is in an active state of high level. Meanwhile, the fourth switching tube MP1 in the on state can provide an extremely low on resistance, so that when the power supply voltage VCC is in a range from 0V to the lowest working voltage of the core sampling control module 21, the output terminal OUT always provides a low-resistance circuit for the power supply voltage input terminal, so that the voltage of the output terminal OUT is at a high level, and thus a high-level effective reset indication signal is correctly output.
2) When the power supply voltage VCC rises to the working voltage of the core sampling control module 21, the charge pump 22 and the logic conversion module 23 all start to work normally. The charge pump 22 provides a voltage greater than the power supply voltage VCC as a reference voltage, and the voltage is lower than the cut-off level of the depletion type fourth switch tube MP 1.
At this time, if the power supply voltage VCC is smaller than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage VCC, and the second logic level of the second control signal a output by the logic level conversion module 23 is 0V, so that the second control signal a can control the fourth switching tube MP1 to be in the on state, and control the fifth switching tube MN1 to be in the off state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in the high-level effective state.
At this time, if the power supply voltage VCC is greater than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage 0V, and the second logic level of the second control signal a output by the logic level conversion module 23 is converted to a voltage value greater than the power supply voltage VCC of the reference voltage, so that the second control signal a can control the fourth switching tube MP1 to be in the off state, and control the fifth switching tube MN1 to be in the on state, so that the reset indication signal output by the output module 24 to the output end OUT is in the invalid state of the low level. That is, the reset function of the reset instruction signal is released.
Based on the above description, it can be seen that, in the embodiment of the present disclosure, for different valid states of the reset indication signal, only the types of the switching tubes in the output module 24 and the output levels of the corresponding charge pump 22 and the logic level conversion module 23 need to be appropriately changed, so that the power monitoring circuit 20 can correctly output the reset indication signal when the VCC voltage of the power supply voltage is 0V or after the modules of the circuit 20 operate.
Further, the principle description parts in the first and second embodiments are described by taking the gate of the enhancement transistor receiving the second control signal a as an example, but it is understood that the description is also applicable when the gate of the enhancement transistor receiving the first control signal, and therefore, the description is not repeated here.
EXAMPLE III
In this embodiment, the reset indication signal is active in a low state.
Referring to fig. 5, the output module 24 includes: a first resistor R1 and a third switch tube MN 2. The first resistor R1 and the third switch tube MN2 are sequentially connected in series between the power supply voltage VCC input end and the ground GND, and the gate of the third switch tube MN2 receives the second control signal A. The third switching tube MN2 is a depletion NMOS transistor. And the output module 24 outputs a reset indication signal at the drain of the third switch tube MN 2.
Further, in the present embodiment, the charge pump 22 generates the reference voltage with the negative voltage VSS.
Compared to the power monitoring circuit 20 in the first embodiment, the power monitoring circuit 20 in the present embodiment only replaces the PMOS transistor in the output module 24 with the resistor, and the specific working principle thereof is substantially the same as that described in the first embodiment, and therefore, the detailed description thereof is omitted, and the details can be understood with reference to the first embodiment.
Example four
In this embodiment, the reset indication signal is active in a high state.
Referring to fig. 6, the output module 24 includes: a sixth switching tube MP2 and a second resistor R2. The sixth switch MP2 and the second resistor R2 are sequentially connected in series between the power voltage VSS input terminal and the ground GND, and the gate of the sixth switch MP2 receives the second control signal a. The sixth switching transistor MP2 is a depletion PMOS transistor. And the output module 24 outputs a reset indication signal at the drain of the sixth switch MP 2.
Further, in the present embodiment, the charge pump 22 generates the reference voltage larger than the power voltage VCC.
Compared to the power monitoring circuit 20 in the second embodiment, the power monitoring circuit 20 in this embodiment only changes the NMOS transistor in the output module 24 into a resistor, and the specific working principle thereof is basically the same as that described in the second embodiment, so that the detailed description is omitted here and can be understood with reference to the second embodiment.
Compared with the push-pull output mode of the output module 24 in the first or second embodiment of the present disclosure, the output module 24 in the third and fourth embodiments of the present disclosure is an output structure with an open source, but may also correspondingly implement the same function. Thus, more choices can be provided for the user.
The disclosure also relates to a switching power supply comprising a control circuit and a power circuit. Wherein the control circuit in the switching power supply further comprises a control module and a power supply monitoring circuit 20 as described in fig. 2 to 6.
In summary, in the power supply monitoring circuit and the switching power supply according to the present disclosure, the depletion transistor is used as the output stage transistor for outputting the reset instruction signal, and due to the conduction characteristic of the depletion transistor, the power supply monitoring circuit can be normally turned on even when the power supply voltage is low, and can correctly output the effective reset instruction signal. Meanwhile, the power supply monitoring circuit is also provided with a charge pump and a logic level conversion module, and the logic level conversion module is used for converting the logic level of the control signal output to the switching tube based on the reference voltage output by the charge pump, so that the switching tube can still be correctly turned on and off after the power supply voltage rises and the core circuit normally works, and the accuracy of the output reset indication signal is effectively ensured.
And the circuit can realize correct reset indication signal output under the condition of no external resistor, thereby occupying small area.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A power supply monitoring circuit, comprising:
the core sampling control module is connected with a power supply voltage input end and used for outputting a first control signal with a first logic level according to the level state of the power supply voltage;
the charge pump is used for generating corresponding reference voltages according to the effective level states of different reset indicating signals;
a logic level conversion module, connected to the output module, the core sampling control module and the charge pump, respectively, for converting a logic level of the first control signal according to the reference voltage to output a second control signal having a second logic level;
an output module, configured to provide a reset indication signal according to the second control signal, where the reset indication signal is used to represent a level state of the power supply voltage,
the output module comprises at least one switching tube, the grid electrode receives the second control signal, the switching tube is used for outputting the effective reset indicating signal at the drain electrode when the switching tube is conducted, and the switching tube is a depletion transistor.
2. The power supply monitoring circuit of claim 1, wherein the output module is a power supply comprising: a first switch tube and a second switch tube,
the first switch tube and the second switch tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the first switch tube receives the first control signal or the second control signal, the grid electrode of the second switch tube receives the second control signal,
the first switch tube is an enhancement type PMOS transistor, the second switch tube is a depletion type NMOS transistor, the output module outputs the reset indicating signal at the drain electrode of the second switch tube, and the reset indicating signal is effective when in a low level state.
3. The power supply monitoring circuit of claim 1, wherein the output module is a circuit comprising: a first resistor and a third switch tube,
the first resistor and the third switching tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the third switching tube receives the second control signal,
the third switching tube is a depletion type NMOS transistor, the output module outputs the reset indicating signal at the drain of the third switching tube, and the reset indicating signal is effective when in a low level state.
4. The power supply monitoring circuit of claim 1, wherein the output module is a circuit comprising: a fourth switching tube and a fifth switching tube,
the fourth switching tube and the fifth switching tube are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the fourth switching tube receives the first control signal or the second control signal, the grid electrode of the fifth switching tube receives the second control signal,
the fourth switch tube is a depletion type PMOS transistor, the fifth switch tube is an enhancement type NMOS transistor, the output module outputs the reset indicating signal at the drain electrode of the fourth switch tube, and the reset indicating signal is effective when in a high level state.
5. The power supply monitoring circuit of claim 1, wherein the output module is a circuit comprising: a sixth switching tube and a second resistor,
the sixth switching tube and the second resistor are sequentially connected in series between a power supply voltage input end and a reference ground, the grid electrode of the sixth switching tube receives the second control signal,
the sixth switching tube is a depletion type PMOS transistor, the output module outputs the reset indication signal at the drain of the sixth switching tube, and the reset indication signal is effective when in a high level state.
6. A power supply monitoring circuit as claimed in any one of claims 2 and 3, wherein the charge pump is to generate a reference voltage having a negative voltage.
7. A power supply monitoring circuit according to any of claims 4 and 5, in which the charge pump is arranged to generate a reference voltage having a value greater than the supply voltage.
8. The power supply monitoring circuit of claim 6, wherein when the first logic level is the supply voltage, the second logic level is also the supply voltage;
when the first logic level is 0, the second logic level is the reference voltage.
9. The power supply monitoring circuit of claim 7, wherein when the first logic level is the power supply voltage, the second logic level is 0;
when the first logic level is 0, the second logic level is the reference voltage.
10. A switching power supply comprising a control circuit and a power circuit, wherein the control circuit comprises a control module and a power supply monitoring circuit as claimed in any one of claims 1 to 9.
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| CN202011574949.4A CN114696587A (en) | 2020-12-28 | 2020-12-28 | Power supply monitoring circuit and switching power supply |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115865074A (en) * | 2022-12-23 | 2023-03-28 | 锐石创芯(深圳)科技股份有限公司 | Level conversion circuit, radio frequency switch control circuit and radio frequency front end module |
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| CN208580375U (en) * | 2018-06-27 | 2019-03-05 | 宗仁科技(平潭)有限公司 | A kind of power-on reset signal generation circuit and IC chip |
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| US7705659B1 (en) * | 2007-07-02 | 2010-04-27 | Altera Corporation | Power regulator circuitry with power-on-reset control |
| JP2010124131A (en) * | 2008-11-18 | 2010-06-03 | Denso Corp | Control circuit |
| US20110074470A1 (en) * | 2009-09-29 | 2011-03-31 | Texas Instruments Incorporated | Low current power-on reset circuit and method |
| CN201774453U (en) * | 2010-08-26 | 2011-03-23 | Bcd半导体制造有限公司 | Power supply voltage detection circuit of switching power supply |
| US20130082749A1 (en) * | 2011-10-04 | 2013-04-04 | Analog Devices, Inc. | Reset generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115865074A (en) * | 2022-12-23 | 2023-03-28 | 锐石创芯(深圳)科技股份有限公司 | Level conversion circuit, radio frequency switch control circuit and radio frequency front end module |
| CN115865074B (en) * | 2022-12-23 | 2023-11-03 | 锐石创芯(深圳)科技股份有限公司 | Level conversion circuit, radio frequency switch control circuit and radio frequency front end module |
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