CN110187923A - A kind of CPU starting method and apparatus applied to multi -CPU board - Google Patents
A kind of CPU starting method and apparatus applied to multi -CPU board Download PDFInfo
- Publication number
- CN110187923A CN110187923A CN201910389880.9A CN201910389880A CN110187923A CN 110187923 A CN110187923 A CN 110187923A CN 201910389880 A CN201910389880 A CN 201910389880A CN 110187923 A CN110187923 A CN 110187923A
- Authority
- CN
- China
- Prior art keywords
- cpu
- cpld
- spi
- spi bus
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
Abstract
The application provides a kind of CPU starting method and apparatus applied to multi -CPU board.Started using the load that CPLD carrys out CPU management bootstrap, is sequentially communicated with each CPU foundation, after any CPU start completion, the spi bus between the CPU and CPLD is just in idle condition.Continue to communicate with next CPU foundation until each CPU start completion.The application carries out the read-write operation of external memory by spi bus.Bootstrap version different problems are not only solved, while having used less external memory, decline hardware cost.
Description
Technical field
This application involves Internet technical fields more particularly to a kind of CPU applied to multi -CPU board to start method and dress
It sets.
Background technique
CPU is answered as indispensable kernel control chip needed for all trades and professions in the fields such as industrial production and consumer electronics
With extensive.With the increase to CPU use demand, occurs multi-CPU architecture in more and more boards, mainstream is existing at present
Application scheme is used together using CPU collocation external memory chip external memory, and CPU is responsible for the read-write of storage chip, deposits
Store up program code memory of the chip as CPU.
It include multiple CPU and multiple external memories in board in traditional scheme, particular hardware framework refers to Fig. 1, often
A CPU, which can be corresponded to, is equipped with external main memory and external standby memory.When CPU starting is with online upgrading, inside CPU
Bootloader can first guide the code in external main memory to internal RAM to run, if CPU starting failure, CPLD continue
Piece selects external standby memory, and the external code in memory of bootloader guidance to the internal RAM inside CPU is run.CPU
The upgrading of code is realized by spi bus in access and external memory to external memory external memory.
Since a CPU corresponds to active and standby two external memories in traditional scheme, and multiple CPU will make in a board
At the bootstrap of multiple external memories storage CPU, it is excessive to be likely to result in bootstrap version, program version between CPU
Disunity, and the presence of excessive external memory also can be such that the hardware cost of board increases therewith.
Summary of the invention
In view of the above technical problems, the embodiment of the present application provides a kind of CPU starting method and dress applied to multi -CPU board
It sets, technical solution is as follows:
It is described according to the embodiment of the present application in a first aspect, providing a kind of CPU applied to multi -CPU board starts method
Board includes CPLD, several CPU and active and standby two external memories, which comprises
CPL establishes SPI communication with external main memory and the first CPU respectively by spi bus；
After CPLD receives the loaded status signal that the first CPU is sent, the SPI between release and the first CPU is total
Line, the loaded status signal is the first CPU by spi bus, by the first CPU's corresponding in external main memory
The signal of CPLD is sent to after boot program loads；
CPLD continues through spi bus and the 2nd CPU establishes SPI communication, and the load for waiting the 2nd CPU to be received to send is complete
Finish status signal, until the boot program loads of each CPU in the board finish.
According to the second aspect of the embodiment of the present application, a kind of CPU starter applied to multi -CPU board is provided, it is described
Board includes CPLD, several CPU and active and standby two external memories, and described device includes:
Communication building block: it for controlling CPL by spi bus, is established respectively with external main memory and the first CPU
SPI communication；
Bus release block: after the loaded status signal for receiving the first CPU transmission for controlling CPLD, release and institute
The spi bus between the first CPU is stated, the loaded status signal is the first CPU by spi bus, and outside is main
The signal of CPLD is sent in memory after the boot program loads of corresponding first CPU；
Communication control module: CPLD continues through spi bus and the 2nd CPU establishes SPI communication for controlling, and waits waiting
The loaded status signal for receiving the 2nd CPU transmission, until the boot program loads of each CPU in the board finish.
Technical solution provided by the embodiment of the present application is started, sequence using the load that CPLD carrys out CPU management bootstrap
It is communicated with each CPU foundation, after any CPU start completion, the spi bus between the CPU and CPLD is just in idle condition.
Continue to communicate with next CPU foundation until each CPU start completion.The application passes through the read-write operation of external memory
Spi bus carries out.Bootstrap version different problems are not only solved, while having used less external memory, are made hard
The decline of part cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The embodiment of the present application can be limited.
In addition, any embodiment in the embodiment of the present application does not need to reach above-mentioned whole effects.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application embodiment can also obtain according to these attached drawings for those of ordinary skill in the art
Obtain other attached drawings.
Fig. 1 is a kind of hardware block diagram of multi -CPU board in traditional scheme shown in one exemplary embodiment of the application；
Fig. 2 is a kind of hardware block diagram of the multi -CPU board shown in one exemplary embodiment of the application；
Fig. 3 is a kind of process of the CPU starting method applied to multi -CPU board shown in one exemplary embodiment of the application
Figure；
Fig. 4 is another stream of the CPU starting method applied to multi -CPU board shown in one exemplary embodiment of the application
Cheng Tu；
Fig. 5 is a kind of signal of the CPU starter applied to multi -CPU board shown in one exemplary embodiment of the application
Figure；
Fig. 6 is a kind of structural schematic diagram of computer equipment shown in one exemplary embodiment of the application.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects be described in detail in claims, the application.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not departing from
In the case where the application range, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determination ".
CPU is answered as indispensable kernel control chip needed for all trades and professions in the fields such as industrial production and consumer electronics
With extensive.With the increase to CPU use demand, occurs multi-CPU architecture in more and more boards, mainstream is existing at present
Application scheme is used together using CPU collocation external memory chip external memory, and CPU is responsible for the read-write of storage chip, deposits
Store up program code memory of the chip as CPU.
It include multiple CPU and multiple external memories in board in traditional scheme, particular hardware framework refers to Fig. 1, often
A CPU, which can be corresponded to, is equipped with external main memory and external standby memory.When CPU starting is with online upgrading, inside CPU
Bootloader can first guide the code in external main memory to internal RAM to run, if CPU starting failure, CPLD continue
Piece selects external standby memory, and the external code in memory of bootloader guidance to the internal RAM inside CPU is run.CPU
The upgrading of code is realized by spi bus in access and external memory to external memory.
Since a CPU corresponds to active and standby two external memories in traditional scheme, and multiple CPU will make in a board
At the bootstrap of multiple external memories storage CPU, it is excessive to be likely to result in bootstrap version, program version between CPU
Disunity, and the presence of excessive external memory also can be such that the hardware cost of board increases therewith.
In view of the above problems, the embodiment of the present application provides a kind of CPU starting method applied to multi -CPU board, Yi Jiyi
Plant the CPU starter applied to multi -CPU board for executing this method.First to this application involves concept solve
It releases, as follows:
Central processing unit (CPU, Central Processing Unit): central processing unit is one piece of ultra-large collection
It is the arithmetic core (Core) and control core (Control Unit) of a computer at circuit.Its function mainly solves
It releases computer instruction and handles the data in computer software.Central processing unit mainly includes arithmetic unit (arithmetic logical operation
Unit, ALU, Arithmetic Logic Unit) and cache memory (Cache) and realize the number contacted between them
According to the bus (Bus) of (Data), control and state.It is collectively referred to as with internal storage (Memory) and input/output (I/O) equipment
For the big core component of electronic computer three.
CPLD (Complex Programmable Logic Device): CPLD is a kind of Complex Programmable Logic Devices,
It is the device come out from PAL and GAL device development, in contrast scale is big, and structure is complicated, belongs to large scale integrated circuit model
It encloses.It is a kind of user according to respective the need and voluntarily digital integrated electronic circuit of constitutive logic function.Its basic design method is to borrow
Integrated Development software platform is helped, with the methods of schematic diagram, hardware description language, generates corresponding file destination, passes through downloading electricity
Code is transmitted in objective chip by cable (" in system " programming), realizes the digital display circuit of design.
SPI (serial peripheral interface): SPI is a kind of Serial Peripheral Interface, is a kind of common
Clock synchronous serial communication interface.
This application involves the CPU starting method applied to multi -CPU board be applied to multi -CPU board, the board includes
CPLD, several CPU and active and standby two external memories, particular hardware framework refer to Fig. 2.Wherein, it is only existed in total in board
Active and standby two external memories are saved compared with being that active and standby two external memories of each CPU outfit are compared in traditional scheme
Hardware cost.
Below to this application involves applied to multi -CPU board CPU starting method be described in detail, referring to Fig. 3 institute
Show, this method may comprise steps of:
S301, CPLD establish SPI communication with external main memory and the first CPU respectively by spi bus；
The bootstrap of CPU is stored in external memory, and the bootstrap of each CPU is store in external memory,
After board powers on, reset state of all CPU all in default.
Specifically, CPLD selects external main memory by chip selection signal, passes through spi bus and the external main memory
Establish SPI communication；CPLD demultiplexes bit manipulation to the first CPU execution by control signal wire, after the completion of demultiplexing bit manipulation, passes through
Spi bus and the first CPU establish SPI communication.
Wherein, external memory can be selected according to concrete application scene, such as: can be used SPI Flash as outer
Portion's memory.
After S302, CPLD receive the loaded status signal that the first CPU is sent, between release and the first CPU
Spi bus, the loaded status signal is the first CPU by spi bus, by external main memory corresponding first
The signal of CPLD is sent to after the boot program loads of CPU；
S303, CPLD continue through spi bus and the 2nd CPU establishes SPI communication, and the 2nd CPU to be received is waited to send
Loaded status signal, until the boot program loads of each CPU in the board finish.
Wherein, the control module for sequentially loading CPU has been pre-configured in CPLD, in this step, CPLD can be pre-
The loading sequence of each CPU is read in the configuration file set, with next the 2nd CPU for establishing SPI communication of determination.
As can be seen that CPLD establishes SPI communication by spi bus and the 2nd CPU, and wait the 2nd CPU and external storage
Data interaction between device terminates, after the 2nd CPU sends loaded status signal.Spi bus and the 3rd CPU will be continued through
SPI communication is established, and is repeated the above steps, until needing to carry out data load CPU whole loaded.
It is shown in Figure 4, after the data interaction between CPU and external storage fails, another spare outside can be enabled and deposited
Reservoir continues data interaction, can specifically include following steps:
S401, CPLD and any CPU establish SPI communication；
Do S402, CPLD receive the loaded status signal that the CPU is sent? if receiving adding for the CPU transmission
Load finishes status signal, then determines CPU bootload program success from the external main memory, execute step
S403；If not receiving the loaded status signal that the CPU is sent, determine the CPU from the external main memory
Bootload procedure failure executes step S404；
S403, continues through spi bus and next CPU establishes SPI communication, and the load for waiting next CPU to be received to send
Status signal is finished, until the boot program loads of each CPU in the board finish；
Spi bus between S404, CPLD release and the external main memory, and pass through the spi bus and outside
Standby memory establishes SPI communication, carries out data interaction between external standby memory and each CPU to use.
The application makes improvement on the basis of conventional solution.Because making in board there are CPLD logical device
Access and CPU of the CPU to the load, CPU of bootstrap to external memory are realized with the part logical resource of CPLD
To functions such as edition upgradings in external memory.The application passes through the hardware structure and plate between CPU, CPLD and external memory
The logical resource of CPLD is realized to bootstrap version in the control of CPU boot program loads sequence, external memory in card
Upgrading and CPU are to functions such as external memory access.
It is the hardware structure schematic diagram of technical solution provided by the present application, wherein the quantity of CPU is only in figure with reference to Fig. 2
A kind of example in addition to including CPU0, outside these three CPU of CPU1, CPU2, may include more or number in practical applications
Measure more CPU.
Below with reference to it is shown in Fig. 2 include three CPU hardware block diagram to provided by the present application for multi -CPU board
CPU starting method is specifically described:
The bootstrap of CPU is stored in external memory, and the bootstrap of each CPU is store in external memory,
After board powers on, reset state of all CPU all in default.
PLD elder generation piece selects SPI Flash0, subsequent CPLD to carry out demultiplexing bit manipulation, Xie Fuwei to CPU0 by control signal wire
After the completion of operation, CPLD establishes the SPI communication between CPU0,
CPU0 passes through the bootstrap of CPU0 of the spi bus load store in SPI Flash0, CPU0 after the completion of load
It sends after a status signal receives this status signal to CPLD, CPLD, it is total to start the SPI discharged between CPU0 and CPLD
Line.
After the completion of spi bus release, CPLD carries out CPU1 by control signal wire to demultiplex bit manipulation, and it is complete to demultiplex bit manipulation
Cheng Hou, CPLD establish the SPI communication between CPU1, and CPU1 passes through CPU1 of the spi bus load store in SPI Flash0
Bootstrap, CPU1 is sent after a status signal receives this status signal to CPLD, CPLD after the completion of load, starts to release
Put the spi bus between CPU1 and CPLD.
After the completion of spi bus release, CPLD carries out CPU2 by control signal wire to demultiplex bit manipulation, and it is complete to demultiplex bit manipulation
Cheng Hou, CPLD establish the SPI communication between CPU2, and CPU2 passes through CPU2 of the spi bus load store in SPI Flash0
Bootstrap, CPU2 is sent after a status signal receives this status signal to CPLD, CPLD after the completion of load, starts to release
The spi bus between CPU2 and CPLD is put, hereafter spi bus is in idle condition.
When certain CPU wants to access SPI Flash0, the SPI communication between CPU need to be only established by CPLD, and it is right
In the upgrading of bootstrap version, CPU0 is only needed to carry out online upgrading i.e. to the bootstrap in SPI Flash0 by CPLD
It can.
When CPU cannot the bootload program from SPI Flash0 when, CPLD is selected standby by chip selection signal CS1 at this time
SPI Flash1 and CPU carries out data interaction, guides in the hereafter control of each CPU boot program loads sequence, SPI Flash
The upgrading of program version, CPU SPI Flash is accessed and CPU by the load of the main Flash bootstrap realized, access,
The step of line upgrades is consistent.
Corresponding to above method embodiment, the embodiment of the present application also provides a kind of CPU starting dress applied to multi -CPU board
It sets, it is shown in Figure 5, the apparatus may include: communication building block 510, bus release block 520 and communication control module
530。
Communication building block 510: it for controlling CPLD by spi bus, is built respectively with external main memory and the first CPU
Vertical SPI communication；
Bus release block 520: after the loaded status signal for receiving the first CPU transmission for controlling CPLD, release
With the spi bus between the first CPU, the loaded status signal is the first CPU by spi bus, will be outer
The signal of CPLD is sent in portion's main memory after the boot program loads of corresponding first CPU；
Communication control module 530: CPLD continues through spi bus and the 2nd CPU establishes SPI communication for controlling, and waits
The loaded status signal that 2nd CPU to be received is sent, until the boot program loads of each CPU in the board are complete
Finish.
The embodiment of the present application also provides a kind of computer equipment, includes at least memory, processor and is stored in storage
On device and the computer program that can run on a processor, wherein processor realizes aforementioned applications in more when executing described program
The CPU of CPU board card starts method, and the board includes CPLD, and several CPU and active and standby two external memories, the method is extremely
Include: less
CPLD establishes SPI communication with external main memory and the first CPU respectively by spi bus；
After CPLD receives the loaded status signal that the first CPU is sent, the SPI between release and the first CPU is total
Line, the loaded status signal is the first CPU by spi bus, by the first CPU's corresponding in external main memory
The signal of CPLD is sent to after boot program loads；
CPLD continues through spi bus and the 2nd CPU establishes SPI communication, and the load for waiting the 2nd CPU to be received to send is complete
Finish status signal, until the boot program loads of each CPU in the board finish.
Fig. 6 shows one kind provided by the embodiment of the present application and more specifically calculates device hardware structural schematic diagram, should
Equipment may include: processor 1110, memory 1120, input/output interface 1130, communication interface 1140 and bus 1150.
Wherein processor 1110, memory 1120, input/output interface 1130 and communication interface 1140 are realized each other by bus 1150
Between communication connection inside equipment.
Processor 1110 can use general CPU (Central Processing Unit, central processing unit), micro- place
Reason device, application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or one
Or the modes such as multiple integrated circuits are realized, for executing relative program, to realize technical solution provided by the embodiment of the present application.
Memory 1120 can use ROM (Read Only Memory, read-only memory), RAM (Random Access
Memory, random access memory), static storage device, the forms such as dynamic memory realize.Memory 1120 can store
Operating system and other applications are realizing technical solution provided by the embodiment of the present application by software or firmware
When, relevant program code is stored in memory 1120, and execution is called by processor 1110.
Input/output interface 1130 is for connecting input/output module, to realize information input and output.Input and output/
Module can be used as component Configuration (not shown) in a device, can also be external in equipment to provide corresponding function.Wherein
Input equipment may include keyboard, mouse, touch screen, microphone, various kinds of sensors etc., output equipment may include display,
Loudspeaker, vibrator, indicator light etc..
Communication interface 1140 is used for connection communication module (not shown), to realize the communication of this equipment and other equipment
Interaction.Wherein communication module can be realized by wired mode (such as USB, cable etc.) and be communicated, can also be wirelessly
(such as mobile network, WIFI, bluetooth etc.) realizes communication.
Bus 1150 include an access, equipment various components (such as processor 1110, memory 1120, input/it is defeated
Outgoing interface 1130 and communication interface 1140) between transmit information.
It should be noted that although above equipment illustrates only processor 1110, memory 1120, input/output interface
1130, communication interface 1140 and bus 1150, but in the specific implementation process, which can also include realizing normal fortune
Other assemblies necessary to row.In addition, it will be appreciated by those skilled in the art that, it can also be only comprising real in above equipment
Component necessary to existing the embodiment of the present application scheme, without including all components shown in figure.
The embodiment of the present application also provides a kind of computer readable storage medium, is stored thereon with computer program, the program
Realize that the CPU above-mentioned applied to multi -CPU board starts method when being executed by processor, the method includes at least:
CPLD establishes SPI communication with external main memory and the first CPU respectively by spi bus；
After CPLD receives the loaded status signal that the first CPU is sent, the SPI between release and the first CPU is total
Line, the loaded status signal is the first CPU by spi bus, by the first CPU's corresponding in external main memory
The signal of CPLD is sent to after boot program loads；
CPLD continues through spi bus and the 2nd CPU establishes SPI communication, and the load for waiting the 2nd CPU to be received to send is complete
Finish status signal, until the boot program loads of each CPU in the board finish.
Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be by any method
Or technology come realize information store.Information can be computer readable instructions, data structure, the module of program or other data.
The example of the storage medium of computer includes, but are not limited to phase change memory (PRAM), static random access memory (SRAM), moves
State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable
Programmable read only memory (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM),
Digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices
Or any other non-transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, it calculates
Machine readable medium does not include temporary computer readable media (transitory media), such as the data-signal and carrier wave of modulation.
For device embodiment, since it corresponds essentially to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.The apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize application scheme.Those of ordinary skill in the art are not paying
Out in the case where creative work, it can understand and implement.
As seen through the above description of the embodiments, those skilled in the art can be understood that the application reality
Applying example can realize by means of software and necessary general hardware platform.Based on this understanding, the embodiment of the present application
Substantially the part that contributes to existing technology can be embodied in the form of software products technical solution in other words, the meter
Calculation machine software product can store in storage medium, such as ROM/RAM, magnetic disk, CD, including some instructions are used so that one
Platform computer equipment (can be personal computer, server or the network equipment etc.) executes each implementation of the embodiment of the present application
Method described in certain parts of example or embodiment.
The above is only the specific embodiment of the embodiment of the present application, it is noted that for the common of the art
For technical staff, under the premise of not departing from the embodiment of the present application principle, several improvements and modifications can also be made, these change
Into the protection scope that also should be regarded as the embodiment of the present application with retouching.
Claims (10)
1. a kind of CPU applied to multi -CPU board starts method, the board includes CPLD, and several CPU are outer with active and standby two
Portion's memory, which comprises
CPLD establishes SPI communication with external main memory and the first CPU respectively by spi bus；
After CPLD receives the loaded status signal that the first CPU is sent, the spi bus between the first CPU, institute are discharged
Stating loaded status signal is the first CPU by spi bus, by the guidance of the first CPU corresponding in external main memory
The signal of CPLD is sent to after program loaded；
CPLD continues through spi bus and the 2nd CPU establishes SPI communication, and the loaded shape for waiting the 2nd CPU to be received to send
State signal, until the boot program loads of each CPU in the board finish.
2. the method as described in claim 1, the CPU applied to multi -CPU starts method, further includes:
If after CPLD and any CPU establish SPI communication, not receiving the loaded status signal that the CPU is sent, then determining institute
State CPU bootload procedure failure from the external main memory；
Spi bus between CPLD release and the external main memory, and built by the spi bus and external standby memory
Vertical SPI communication carries out data interaction between external standby memory and each CPU to use.
3. the method as described in claim 1, the CPU is built with external main memory and the first CPU respectively by spi bus
Vertical SPI communication, comprising:
CPLD selects external main memory by chip selection signal, and it is logical to establish SPI by spi bus and the external main memory
Letter；
CPLD by control signal wire to the first CPU execution demultiplex bit manipulation, after the completion of demultiplexing bit manipulation, by spi bus with
First CPU establishes SPI communication.
4. the method as described in claim 1, after the spi bus between the release and the first CPU, further includes:
CPLD reads the loading sequence of each CPU in preset configuration file, establishes the second of SPI communication so that determination is next
CPU。
5. the method as described in claim 1, the CPU applied to multi -CPU starts method, further includes:
After CPLD receives the active access instruction that any CPU initiates external memory, respectively with the CPU and external primary storage
Device establishes SPI communication, so as to carry out data interaction by spi bus between external main memory and the CPU.
6. a kind of CPU starter applied to multi -CPU board, the board includes CPLD, and several CPU are outer with active and standby two
Portion's memory, described device include:
Communication building block: for controlling CPLD by spi bus, it is logical that SPI is established with external main memory and the first CPU respectively
Letter；
Bus release block: for controlling release and described the after CPLD receives the loaded status signal that the first CPU is sent
Spi bus between one CPU, the loaded status signal is the first CPU by spi bus, by external primary storage
The signal of CPLD is sent in device after the boot program loads of corresponding first CPU；
Communication control module: CPLD continues through spi bus and the 2nd CPU establishes SPI communication for controlling, and waits to be received
The loaded status signal that two CPU are sent, until the boot program loads of each CPU in the board finish.
7. device as claimed in claim 6, the CPU starter applied to multi -CPU, further includes:
If after CPLD and any CPU establish SPI communication, not receiving the loaded status signal that the CPU is sent, then determining institute
State CPU bootload procedure failure from the external main memory；
Spi bus between CPLD release and the external main memory, and built by the spi bus and external standby memory
Vertical SPI communication carries out data interaction between external standby memory and each CPU to use.
8. device as claimed in claim 6, the CPU is built with external main memory and the first CPU respectively by spi bus
Vertical SPI communication, comprising:
CPLD selects external main memory by chip selection signal, and it is logical to establish SPI by spi bus and the external main memory
Letter；
CPLD by control signal wire to the first CPU execution demultiplex bit manipulation, after the completion of demultiplexing bit manipulation, by spi bus with
First CPU establishes SPI communication.
9. device as claimed in claim 6, after the spi bus between the release and the first CPU, further includes:
CPLD reads the loading sequence of each CPU in preset configuration file, establishes the second of SPI communication so that determination is next
CPU。
10. device as claimed in claim 6, the CPU starter applied to multi -CPU, further includes:
After CPLD receives the active access instruction that any CPU initiates external memory, respectively with the CPU and external primary storage
Device establishes SPI communication, so as to carry out data interaction by spi bus between external main memory and the CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910389880.9A CN110187923A (en) | 2019-05-10 | 2019-05-10 | A kind of CPU starting method and apparatus applied to multi -CPU board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910389880.9A CN110187923A (en) | 2019-05-10 | 2019-05-10 | A kind of CPU starting method and apparatus applied to multi -CPU board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110187923A true CN110187923A (en) | 2019-08-30 |
Family
ID=67715958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910389880.9A Pending CN110187923A (en) | 2019-05-10 | 2019-05-10 | A kind of CPU starting method and apparatus applied to multi -CPU board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110187923A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078596A (en) * | 2019-11-28 | 2020-04-28 | 杭州华澜微电子股份有限公司 | Flash chip control method, device and system and readable storage medium |
| CN111240753A (en) * | 2019-12-31 | 2020-06-05 | 京信通信***（中国）有限公司 | Loading method of bootstrap program, storage medium and embedded terminal |
| CN112783438A (en) * | 2020-12-24 | 2021-05-11 | 展讯半导体(成都)有限公司 | Memory using method of functional mobile phone and related product |
| WO2021190252A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip starting method and apparatus and computer device |
| CN114265799A (en) * | 2021-12-28 | 2022-04-01 | 南昌勤胜电子科技有限公司 | SPI read-write system and server based on CPLD |
| CN114461142A (en) * | 2022-01-07 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for reading and writing Flash data |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102830982A (en) * | 2011-06-14 | 2012-12-19 | 中兴通讯股份有限公司 | Processor configuring method, device and processor |
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
| CN106325857A (en) * | 2016-08-11 | 2017-01-11 | 迈普通信技术股份有限公司 | Electronic equipment and electronic equipment control method |
-
2019
- 2019-05-10 CN CN201910389880.9A patent/CN110187923A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102830982A (en) * | 2011-06-14 | 2012-12-19 | 中兴通讯股份有限公司 | Processor configuring method, device and processor |
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
| CN106325857A (en) * | 2016-08-11 | 2017-01-11 | 迈普通信技术股份有限公司 | Electronic equipment and electronic equipment control method |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078596A (en) * | 2019-11-28 | 2020-04-28 | 杭州华澜微电子股份有限公司 | Flash chip control method, device and system and readable storage medium |
| CN111240753A (en) * | 2019-12-31 | 2020-06-05 | 京信通信***（中国）有限公司 | Loading method of bootstrap program, storage medium and embedded terminal |
| WO2021136200A1 (en) * | 2019-12-31 | 2021-07-08 | 京信网络***股份有限公司 | Bootloader loading method, storage medium, and embedded terminal |
| WO2021190252A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip starting method and apparatus and computer device |
| CN112783438A (en) * | 2020-12-24 | 2021-05-11 | 展讯半导体(成都)有限公司 | Memory using method of functional mobile phone and related product |
| CN112783438B (en) * | 2020-12-24 | 2024-01-16 | 展讯半导体(成都)有限公司 | Memory using method of functional mobile phone and related products |
| CN114265799A (en) * | 2021-12-28 | 2022-04-01 | 南昌勤胜电子科技有限公司 | SPI read-write system and server based on CPLD |
| CN114265799B (en) * | 2021-12-28 | 2024-03-26 | 南昌勤胜电子科技有限公司 | SPI read-write system and server based on CPLD |
| CN114461142A (en) * | 2022-01-07 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for reading and writing Flash data |
| CN114461142B (en) * | 2022-01-07 | 2023-08-08 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for reading and writing Flash data |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110187923A (en) | A kind of CPU starting method and apparatus applied to multi -CPU board | |
| CN108614726B (en) | Virtual machine creation method and device | |
| KR101807897B1 (en) | Cross―platform application framework | |
| JP5916881B2 (en) | Method and PCD for showing a peripheral component interface express (PCIE) coupling device to an operating system operable on a portable computing device (PCD) | |
| US8555280B2 (en) | Terminal device of non-android platform for executing android applications, and computer readable recording medium for storing program of executing android applications on non-android platform | |
| US20150186161A1 (en) | Platform system, method for changing support hardware configuration of universal extensible firmware interface basic input output system and computer program product | |
| WO2021031472A1 (en) | Intelligent contract processing method and device, computer device and storage medium | |
| CN110945475A (en) | System and method for providing patchable ROM firmware | |
| CN104156234B (en) | Start the method and device of multi-core processor, the big small end mode adaptives of bootloader | |
| JP6998991B2 (en) | Information processing methods and equipment | |
| CN111176761A (en) | Micro-service calling method and device | |
| CN114564435A (en) | Inter-core communication method, device and medium for heterogeneous multi-core chip | |
| US20200401384A1 (en) | Electronic device and operation method thereof | |
| CN106126241A (en) | A kind of linux system starts method and system | |
| CN116541142A (en) | Task scheduling method, device, equipment, storage medium and computer program product | |
| CN115421787A (en) | Instruction execution method, apparatus, device, system, program product, and medium | |
| WO2024108800A1 (en) | Data processing method and apparatus, electronic device, and computer-readable storage medium | |
| KR102501542B1 (en) | Method and apparatus for blockchain system startup, device, and storage medium | |
| CN112540772B (en) | Application publishing method and system, electronic device and storage medium | |
| CN108292265B (en) | Memory management for high performance memory | |
| CN113934635B (en) | Method for providing cloud service with equal computing power based on heterogeneous processor and application | |
| CN112035133A (en) | Homepage upgrading method and terminal | |
| CN110472977A (en) | A kind of the transaction record generation method and relevant device of block chain | |
| US10402454B1 (en) | Obtaining platform-specific information in a firmware execution environment | |
| KR20200118980A (en) | An electronic device for executing different operating system and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |