CN114400261A - Battery back structure, preparation method thereof and battery - Google Patents
Battery back structure, preparation method thereof and battery Download PDFInfo
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- CN114400261A CN114400261A CN202111617968.5A CN202111617968A CN114400261A CN 114400261 A CN114400261 A CN 114400261A CN 202111617968 A CN202111617968 A CN 202111617968A CN 114400261 A CN114400261 A CN 114400261A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 285
- 239000010409 thin film Substances 0.000 claims abstract description 285
- 238000009792 diffusion process Methods 0.000 claims abstract description 132
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 230000005641 tunneling Effects 0.000 claims abstract description 66
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims description 74
- 238000000137 annealing Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical group ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 16
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 12
- 239000012495 reaction gas Substances 0.000 claims description 12
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 239000012159 carrier gas Substances 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 229910000077 silane Inorganic materials 0.000 claims description 8
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 235000013842 nitrous oxide Nutrition 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 239000005922 Phosphane Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 229910000064 phosphane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000005498 polishing Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
- H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
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- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
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Abstract
The invention provides a battery back structure, which comprises a substrate, a tunneling oxide layer, a doped polycrystalline silicon thin film layer, a diffused polycrystalline silicon thin film layer, a silicon nitride layer and an electrode, wherein the tunneling oxide layer is formed on the substrate; the tunneling oxide layer is arranged on the surface of the substrate; the doped polycrystalline silicon thin film layer is arranged on the surface of the tunneling oxide layer; the diffusion polycrystalline silicon thin film layer is arranged on the surface of the doped polycrystalline silicon thin film layer, and the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer; the silicon nitride layer is arranged on the surface of the diffusion polycrystalline silicon thin film layer; the electrode penetrates through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and the electrode and the doped polycrystalline silicon thin film layer are arranged in a separated mode. The invention also provides a preparation method of the back structure of the battery and the battery.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a cell back structure, a preparation method thereof and a cell.
Background
Solar cells are devices that directly convert light energy into electrical energy by the photoelectric or photochemical effect. At present, the photoelectric conversion efficiency of a battery manufactured by a solar Passivated emitter and back Passivation (PERC) technology reaches 23%, but the efficiency bottleneck is prominent when the battery is faced with the phenomena of narrow resistivity window, low Electroluminescent (EL) yield, double-sided Potential Induced Degradation (PID) and Light-heat Induced Degradation (LeTID). TOPCon cells, which have higher conversion efficiencies and are compatible with most of the existing production facilities of PERC technology, are the most economically viable next generation technology recognized in the industry.
The technology of tunneling oxidation passivation contact (TOPCon) is a technology of a tunneling oxidation layer passivation contact solar cell based on a selective carrier principle, the front side of the technology is not essentially different from a conventional N-type solar cell or an N-passivated emitter back surface fully diffused cell (N-PERT), the core technology of the cell is back side passivation contact, and the back side of a silicon wafer is composed of a layer of ultrathin silicon oxide (1-2 nm) and a layer of phosphorus-doped microcrystalline amorphous mixed silicon film. The passivation property is activated by an annealing process, and the crystallinity of the silicon film is changed in the annealing process, so that the silicon film is changed into polycrystal from a microcrystal amorphous mixed phase. A battery back structure in the prior art is shown in fig. 1, and includes a substrate, a tunneling oxide layer, a doped polysilicon thin film layer, a silicon nitride layer, and an electrode, where the electrode penetrates through the silicon nitride layer and contacts with the doped polysilicon thin film layer, and a contact resistance between the electrode and the doped polysilicon thin film layer in the prior art is relatively large, which results in a relatively large contact resistance between the battery back structure and other devices; and the manufacturing cost of the doped polysilicon thin film layer is higher.
Therefore, it is necessary to develop a back structure of a battery, a method for manufacturing the back structure of the battery, and a battery, so as to avoid the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a battery back structure, a preparation method thereof and a battery, which solve the problem of large contact resistance between an electrode and a doped polycrystalline silicon thin film layer.
In order to achieve the above object, the present invention provides a battery back structure, including:
a substrate;
the tunneling oxide layer is arranged on the surface of the substrate;
the doped polycrystalline silicon thin film layer is arranged on the surface of the tunneling oxide layer;
the diffused polycrystalline silicon thin film layer is arranged on the surface of the doped polycrystalline silicon thin film layer, and the sheet resistance of the diffused polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer;
the silicon nitride layer is arranged on the surface of the diffusion polycrystalline silicon thin film layer;
and the electrode penetrates through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and is separated from the doped polycrystalline silicon thin film layer.
The back structure of the battery has the advantages that: the tunneling oxide layer is arranged on the surface of the substrate; the doped polycrystalline silicon thin film layer is arranged on the surface of the tunneling oxide layer; the diffusion polycrystalline silicon thin film layer is arranged on the surface of the doped polycrystalline silicon thin film layer, and the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer; the silicon nitride layer is arranged on the surface of the diffusion polycrystalline silicon thin film layer; the electrode penetrates through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and the electrode and the doped polycrystalline silicon thin film layer are arranged in a separated mode. Because the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer, the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is lower than that between the electrode and the doped polycrystalline silicon thin film layer by adding the diffusion polycrystalline silicon thin film layer, and the electrode and the doped polycrystalline silicon thin film layer are arranged separately, the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, and the manufacturing cost of the diffusion polycrystalline silicon thin film layer is lower than that of the doped polycrystalline silicon thin film layer, so that the manufacturing cost of a battery back structure is reduced, and the problem of larger contact resistance between the electrode and the doped polycrystalline silicon thin film layer is solved, and the manufacturing cost of the battery back structure is reduced.
Optionally, the thickness of the tunneling oxide layer is 1-3 nm, the thickness of the doped polycrystalline silicon thin film layer is 60-130 nm, the thickness of the diffusion polycrystalline silicon thin film layer is 10-30 nm, and the thickness of the silicon nitride layer is 80-100 nm. The beneficial effects are that: the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is approximately equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, so that the diffusion polycrystalline silicon thin film layer is added, the process time is not increased, and the process capacity is not sacrificed.
Optionally, the sheet resistance of the diffusion polysilicon thin film layer is 10-80 ohms per side. The beneficial effects are that: the sheet resistance of the diffusion polycrystalline silicon thin film layer is small, so that the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is small.
Another object of the present invention is to provide a method for preparing a battery back structure, comprising the steps of:
s30: providing a substrate;
s31: forming a tunneling oxide layer on the surface of the substrate;
s32: forming a doped polycrystalline silicon thin film layer on the surface of the tunneling oxide layer;
s33: forming a diffusion polycrystalline silicon thin film layer on the surface of the doped polycrystalline silicon thin film layer, wherein the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer;
s34: forming a silicon nitride layer on the surface of the diffusion polycrystalline silicon thin film layer;
s35: and forming an electrode on the silicon nitride layer, enabling the electrode to penetrate through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and enabling the electrode and the doped polycrystalline silicon thin film layer to be arranged in a separated mode.
The preparation method of the battery back structure has the beneficial effects that: because the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer, the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is lower than that between the electrode and the doped polycrystalline silicon thin film layer by adding the diffusion polycrystalline silicon thin film layer, the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, and the manufacturing cost of the diffusion polycrystalline silicon thin film layer is lower than that of the doped polycrystalline silicon thin film layer, so that the manufacturing cost of a back structure of the battery is reduced, and the problem of larger contact resistance between the electrode and the doped polycrystalline silicon thin film layer is solved, while the manufacturing cost of the battery back structure is reduced.
Optionally, the step of forming a diffusion polysilicon thin film layer on the surface of the doped polysilicon thin film layer in step S33 includes: and annealing the doped polycrystalline silicon thin film layer, and diffusing the doped polycrystalline silicon thin film layer at the tail section of the annealing treatment to obtain the diffused polycrystalline silicon thin film layer.
Optionally, the temperature of the annealing treatment is 800-1000 ℃, the time of the annealing treatment is 20-40 min, the temperature of the diffusion treatment is 700-900 ℃, and the time of the diffusion treatment is 10-25 min.
Optionally, the diffusion source of the diffusion treatment is phosphorus oxychloride. The beneficial effects are as follows: the diffusion source of the diffusion treatment is phosphorus oxychloride, and the cost of the phosphorus oxychloride is lower than that of the phosphane, so that the process cost is reduced.
Optionally, the diffusion source of the diffusion treatment is any one of boron trichloride and boron tribromide. The beneficial effects are as follows: the diffusion source for diffusion treatment is any one of boron trichloride and boron tribromide, and the cost of the diffusion source is lower than that of a doping source, so that the process cost is reduced.
Optionally, the step of forming a tunnel oxide layer on the surface of the substrate in step S31 includes: the temperature for forming the tunneling oxide layer is controlled to be 100-600 ℃, and the reaction gas for forming the tunneling oxide layer is oxygen or laughing gas.
Optionally, the step of forming a doped polysilicon thin film layer on the surface of the tunneling oxide layer in step S32 includes: the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of phosphine and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
Optionally, the step of forming a doped polysilicon thin film layer on the surface of the tunneling oxide layer in step S32 includes: the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of diborane and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
It is still another object of the present invention to provide a battery, which includes a battery front structure and the battery back structure, wherein the front structure is located on another surface of the substrate, and the other surface of the substrate is opposite to the surface of the substrate on which the tunneling oxide layer is disposed.
The battery has the beneficial effects that: because the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer, the electrode penetrates through part of the diffusion polycrystalline silicon thin film layer by adding the diffusion polycrystalline silicon thin film layer, and the electrode and the doped polycrystalline silicon thin film layer are arranged in a separated mode, so that the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is lower than that between the electrode and the doped polycrystalline silicon thin film layer, and the resistance between the obtained battery and other devices is smaller; the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is approximately equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, and the manufacturing cost of the diffusion polycrystalline silicon thin film layer is lower than that of the doped polycrystalline silicon thin film layer, so that the manufacturing cost of a back structure of the battery is reduced.
Drawings
FIG. 1 is a schematic diagram of a back structure of a conventional battery;
FIG. 2 is a schematic diagram of a back structure of a battery according to an embodiment of the invention;
fig. 3 is a schematic flow chart illustrating a method for manufacturing a back structure of a battery according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a substrate according to an embodiment of the present invention;
FIG. 5 is a schematic structural view of the structure shown in FIG. 4 after a tunnel oxide layer is formed thereon;
FIG. 6 is a schematic structural view of the structure shown in FIG. 5 after a doped polysilicon thin film layer is formed thereon;
FIG. 7 is a schematic view of a structure obtained after forming a diffused polysilicon thin film layer on the structure shown in FIG. 6;
FIG. 8 is a schematic view of a silicon nitride layer formed over the structure of FIG. 7;
fig. 9 is a sectional view of an N-type battery in an embodiment of the invention;
fig. 10 is a sectional view of a P-type battery in a first embodiment of the invention;
fig. 11 is a sectional view of a P-type battery in a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item preceding the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
Fig. 2 is a schematic diagram of a battery back structure according to an embodiment of the invention.
In an embodiment of the present invention, referring to fig. 2, a battery back structure includes:
a substrate 1;
the tunneling oxide layer 2 is arranged on the surface of the substrate 1;
the doped polycrystalline silicon thin film layer 3 is arranged on the surface of the tunneling oxide layer 2;
the diffusion polycrystalline silicon thin film layer 6 is arranged on the surface of the doped polycrystalline silicon thin film layer 3, and the sheet resistance of the diffusion polycrystalline silicon thin film layer 6 is smaller than that of the doped polycrystalline silicon thin film layer 3;
the silicon nitride layer 4 is arranged on the surface of the diffusion polycrystalline silicon thin film layer 6;
and the electrode 5 penetrates through the silicon nitride layer 4 and part of the diffusion polycrystalline silicon thin film layer 6, and the electrode 5 and the doped polycrystalline silicon thin film layer 3 are arranged in a separated mode.
Specifically, the tunneling oxide layer is arranged on the surface of the substrate; the tunneling oxide layer is arranged on the surface of the substrate; the doped polycrystalline silicon thin film layer is arranged on the surface of the tunneling oxide layer; the diffusion polycrystalline silicon thin film layer is arranged on the surface of the doped polycrystalline silicon thin film layer, and the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer; the silicon nitride layer is arranged on the surface of the diffusion polycrystalline silicon thin film layer; the electrode penetrates through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and the electrode and the doped polycrystalline silicon thin film layer are arranged in a separated mode. Because the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer, the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is lower than that between the electrode and the doped polycrystalline silicon thin film layer by adding the diffusion polycrystalline silicon thin film layer, the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is approximately equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, the manufacturing cost of the diffusion polycrystalline silicon thin film layer is lower than that of the doped polycrystalline silicon thin film layer, so that the manufacturing cost of a back structure of the battery is reduced, and the problem of large contact resistance between the electrode and the doped polycrystalline silicon thin film layer is solved, and the manufacturing cost of the battery back structure is reduced.
In some embodiments of the invention, the thickness of the tunneling oxide layer is 1-3 nm, the thickness of the doped polycrystalline silicon thin film layer is 60-130 nm, the thickness of the diffusion polycrystalline silicon thin film layer is 10-30 nm, and the thickness of the silicon nitride layer is 80-100 nm. The total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is approximately equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, so that the diffusion polycrystalline silicon thin film layer is added, the process time is not increased, and the process capacity is not sacrificed.
In some embodiments of the present invention, the sheet resistance of the diffusion polysilicon thin film layer is 10-80 ohms per square. The sheet resistance of the diffusion polycrystalline silicon thin film layer is small, so that the contact resistance between the electrode and the diffusion polycrystalline silicon thin film layer is small.
Fig. 3 is a schematic flow chart illustrating a method for manufacturing a battery back structure according to an embodiment of the present invention.
In an embodiment of the present invention, referring to fig. 2 and 3, a method for manufacturing a back structure of a battery includes the steps of:
s30: providing a substrate 1;
s31: forming a tunneling oxide layer 2 on the surface of the substrate 1;
s32: forming a doped polycrystalline silicon thin film layer 3 on the surface of the tunneling oxide layer 2;
s33: forming a diffusion polycrystalline silicon thin film layer 6 on the surface of the doped polycrystalline silicon thin film layer 3, wherein the sheet resistance of the diffusion polycrystalline silicon thin film layer 6 is smaller than that of the doped polycrystalline silicon thin film layer 3;
s34: forming a silicon nitride layer 4 on the surface of the diffusion polysilicon thin film layer 6;
s35: and forming an electrode 5 on the silicon nitride layer 4, enabling the electrode 5 to penetrate through the silicon nitride layer 4 and part of the diffusion polysilicon thin film layer 6, and enabling the electrode 5 and the doped polysilicon thin film layer 3 to be arranged in a separated mode.
Specifically, because the sheet resistance of the diffusion polysilicon thin film layer is smaller than that of the doped polysilicon thin film layer, the contact resistance between the electrode and the diffusion polysilicon thin film layer is reduced compared with the contact resistance between the electrode and the doped polysilicon thin film layer by adding the diffusion polysilicon thin film layer, the total thickness of the doped polysilicon thin film layer and the diffusion polysilicon thin film layer is approximately equal to the thickness of the doped polysilicon thin film layer in the prior art, and the manufacturing cost of the diffusion polysilicon thin film layer is lower than that of the doped polysilicon thin film layer, so that the manufacturing cost of the battery back structure is reduced, and the invention solves the problem that the contact resistance between the electrode and the doped polysilicon thin film layer is larger, while the manufacturing cost of the battery back structure is reduced.
In some possible embodiments of the present invention, the step of forming a diffusion polysilicon thin film layer on the surface of the doped polysilicon thin film layer in step S33 includes: and annealing the doped polycrystalline silicon thin film layer, and diffusing the doped polycrystalline silicon thin film layer at the tail section of the annealing treatment to obtain the diffused polycrystalline silicon thin film layer.
In some embodiments of the invention, the temperature of the annealing treatment is 800-1000 ℃, the time of the annealing treatment is 20-40 min, the temperature of the diffusion treatment is 700-900 ℃, and the time of the diffusion treatment is 10-25 min.
In some possible embodiments of the invention, the diffusion source of the diffusion treatment is phosphorus oxychloride. The diffusion source of the diffusion treatment is phosphorus oxychloride, and the cost of the phosphorus oxychloride is lower than that of the phosphane, so that the process cost is reduced.
In other possible embodiments of the present invention, the diffusion source of the diffusion treatment is any one of boron trichloride and boron tribromide. The diffusion source for diffusion treatment is any one of boron trichloride and boron tribromide, and the cost of the diffusion source is lower than that of a doping source, so that the process cost is reduced.
In some embodiments of the present invention, the step of forming a tunneling oxide layer on the surface of the substrate in the step S31 includes: the temperature for forming the tunneling oxide layer is controlled to be 100-600 ℃, and the reaction gas for forming the tunneling oxide layer is oxygen or laughing gas.
In some embodiments of the present invention, the step of forming the doped polysilicon thin film layer on the surface of the tunneling oxide layer in the step S32 includes: the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of phosphine and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
In other embodiments of the present invention, the step of forming a doped polysilicon thin film layer on the surface of the tunnel oxide layer in step S32 includes: the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of diborane and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
In an embodiment of the invention, the battery includes a battery front structure and a battery back structure, the front structure is located on the other surface of the substrate, and the other surface of the substrate is opposite to the surface of the substrate on which the tunneling oxide layer is disposed.
Specifically, because the sheet resistance of the diffusion polysilicon thin film layer is smaller than that of the doped polysilicon thin film layer, by adding the diffusion polysilicon thin film layer, the electrode penetrates through part of the diffusion polysilicon thin film layer, and the electrode and the doped polysilicon thin film layer are arranged in a separated manner, so that the contact resistance between the electrode and the diffusion polysilicon thin film layer is lower than the contact resistance between the electrode and the doped polysilicon thin film layer, and the resistance between the obtained battery and other devices is smaller; the total thickness of the doped polycrystalline silicon thin film layer and the diffusion polycrystalline silicon thin film layer is approximately equal to the thickness of the doped polycrystalline silicon thin film layer in the prior art, and the manufacturing cost of the diffusion polycrystalline silicon thin film layer is lower than that of the doped polycrystalline silicon thin film layer, so that the manufacturing cost of a back structure of the battery is reduced.
FIG. 4 is a schematic structural diagram of a substrate according to an embodiment of the present invention; FIG. 5 is a schematic view of a tunneling oxide layer formed on the structure shown in FIG. 4; FIG. 6 is a schematic structural view of the structure shown in FIG. 5 after a doped polysilicon thin film layer is formed thereon; FIG. 7 is a schematic view of a structure obtained after forming a diffused polysilicon thin film layer on the structure shown in FIG. 6; fig. 8 is a schematic view of a structure obtained after a silicon nitride layer is formed on the structure shown in fig. 7.
In some embodiments of the present invention, referring to fig. 4, the substrate 1 is subjected to texturing or polishing in an alkaline solution at a temperature of 75 to 85 ℃, and then cleaned with an HF solution having a volume concentration of 2 to 8% to obtain the substrate 1.
In some embodiments of the present invention, referring to fig. 5, the tunneling oxide layer 2 is disposed on the upper surface of the substrate 1, the lower surface of the tunneling oxide layer 2 completely covers the upper surface of the substrate 1, the temperature for forming the tunneling oxide layer is controlled to be 100 to 600 ℃, and the reaction gas for forming the tunneling oxide layer is oxygen or nitrous oxide.
In some embodiments of the present invention, referring to fig. 6, a doped polysilicon thin film layer 3 is formed on the upper surface of the tunneling oxide layer 2, and the lower surface of the doped polysilicon thin film layer 3 completely covers the upper surface of the tunneling oxide layer 2.
In some possible embodiments of the present invention, the doped polysilicon thin film layer is a phosphorus-doped polysilicon thin film layer, and the step of forming the phosphorus-doped polysilicon thin film layer on the surface of the tunnel oxide layer in step S32 includes: the temperature for forming the phosphorus-doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the phosphorus-doped polycrystalline silicon thin film layer is a mixed gas of phosphine and silane, and the carrier gas for forming the phosphorus-doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
In other possible embodiments of the present invention, the doped polysilicon thin film layer is a boron-doped polysilicon thin film layer, and the step of forming the boron-doped polysilicon thin film layer on the surface of the tunnel oxide layer in step S32 includes: the temperature for forming the boron-doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the boron-doped polycrystalline silicon thin film layer is a mixed gas of diborane and silane, and the carrier gas for forming the boron-doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
In some embodiments of the present invention, referring to fig. 7, a diffused polysilicon thin film layer 6 is formed on the surface of the doped polysilicon thin film layer 3, and the lower surface of the diffused polysilicon thin film layer 6 completely covers the upper surface of the doped polysilicon thin film layer 3.
In some possible embodiments of the present invention, the doped polysilicon thin film layer is a phosphorus-doped polysilicon thin film layer, the diffused polysilicon thin film layer is a phosphorus-expanded polysilicon thin film layer, and the step of forming the phosphorus-expanded polysilicon thin film layer on the surface of the phosphorus-doped polysilicon thin film layer in step S33 includes: annealing the phosphorus-doped polycrystalline silicon thin film layer, and performing diffusion treatment on the phosphorus-doped polycrystalline silicon thin film layer at the tail section of the annealing treatment to obtain a phosphorus-doped polycrystalline silicon thin film layer; the temperature of the annealing treatment is 800-1000 ℃, and the time of the annealing treatment is 20-40 min; the temperature of the diffusion treatment is 700-900 ℃, the time of the diffusion treatment is 10-25 min, and the diffusion source of the diffusion treatment is phosphorus oxychloride.
In other possible embodiments of the present invention, the doped polysilicon thin film layer is a boron-doped polysilicon thin film layer, the diffused polysilicon thin film layer is a boron-expanded polysilicon thin film layer, and the step of forming the boron-expanded polysilicon thin film layer on the surface of the boron-doped polysilicon thin film layer in step S33 includes: annealing the boron-doped polycrystalline silicon thin film layer, and performing diffusion treatment on the boron-doped polycrystalline silicon thin film layer at the tail section of the annealing treatment to obtain a boron-diffused polycrystalline silicon thin film layer; the temperature of the annealing treatment is 800-1000 ℃, and the time of the annealing treatment is 20-40 min; the temperature of the diffusion treatment is 700-900 ℃, the time of the diffusion treatment is 10-25 min, and the diffusion source of the diffusion treatment is any one of boron trichloride and boron tribromide.
In some embodiments of the present invention, referring to fig. 8, a silicon nitride layer 4 is formed on the surface of the diffusion polysilicon thin film layer 6, and the lower surface of the silicon nitride layer 4 completely covers the upper surface of the phosphorus diffusion polysilicon thin film layer 6.
In some embodiments of the present invention, referring to fig. 2, an electrode 5 is formed on the silicon nitride layer 4, the electrode 5 penetrates through the silicon nitride layer 4 and a portion of the diffusion polysilicon thin film layer 6, and the electrode 5 is spaced apart from the doped polysilicon thin film layer 3.
In some embodiments of the present invention, the method for preparing the battery comprises the following steps:
s0: using an N-type silicon wafer or a P-type silicon wafer as the substrate, namely, texturing the N-type silicon wafer or the P-type silicon wafer in an alkaline solution at 75-85 ℃, and cleaning with an HF solution with the volume concentration of 2-8% after texturing to obtain a clean substrate; the alkaline solution consists of an alkaline substance, an additive and deionized water, wherein the mass ratio of the alkaline substance to the additive to the deionized water is 20:5: 130;
s1: carrying out a boron diffusion process on the front surface of the substrate to form a boron diffusion junction on the front surface of the clean substrate to prepare a first matrix; wherein the diffusion temperature is 900-1100 ℃, and the sheet resistance of the first substrate is 70-200 ohms per side;
s2: removing the boron diffusion junction on the back surface of the first substrate, and reserving borosilicate glass on the front surface of the first substrate to prepare a second substrate;
s3: depositing a tunneling oxide layer, a doped polycrystalline silicon thin film layer and a diffusion polycrystalline silicon thin film layer on the back of the second substrate in sequence to obtain a third substrate; depositing a plurality of second substrates in a tubular PECVD (plasma enhanced chemical vapor deposition) device to prepare the tunneling oxide layer and the doped polycrystalline silicon thin film layer, wherein the power frequency of the tubular PECVD device is 40kHz, the power of the tubular PECVD device is 10-30 kW, and the graphite boat page pitch of the tubular PECVD device is 8-12 mm; depositing the diffusion polycrystalline silicon thin film layer in annealing diffusion equipment, wherein the annealing temperature is 840-880 ℃, the annealing time is 20-40 min, the diffusion temperature is 720-800 ℃, the diffusion time is 10-25 min, the sheet resistance of the diffusion polycrystalline silicon thin film layer is 20-80 ohm per square, and a plurality of second substrates are vertically or horizontally placed back to back in tubular PECVD equipment;
s4: cleaning the front surface of the third substrate by using an HF solution, and then cleaning the third substrate by using an NaOH solution at a high temperature to prepare a fourth substrate; wherein the volume concentration of the HF solution is 7-18%; the NaOH solution is prepared according to the volume ratio of NaOH to water of 1:9, and the high-temperature condition is 60-85 ℃;
s5: depositing an aluminum oxide layer on the front surface of the fourth substrate to obtain a fifth substrate;
s6: depositing silicon nitride layers on the front surface and the back surface of the fifth substrate respectively to obtain a sixth substrate;
s7: screen printing and sintering the sixth substrate to obtain the battery; wherein the sintering peak temperature is 750-800 ℃, and the sintering time is 25-60 s.
Fig. 9 is a sectional view of an N-type battery in an embodiment of the invention; fig. 10 is a sectional view of a P-type battery in a first embodiment of the present invention; fig. 11 is a sectional view of a P-type battery in a second embodiment of the present invention.
In some possible embodiments of the present invention, referring to fig. 9, the cell is an N-type cell 8, and includes a cell front structure 80 and the cell back structure (not labeled in the figure), the cell front structure 80 is located on another surface of the substrate 1, the other surface of the substrate 1 is opposite to the surface of the substrate 1 on which the tunneling oxide layer 2 is disposed, and the substrate 1 is an N-type silicon wafer. The cell front structure 80 comprises a boron-doped emitter layer 81, an aluminum oxide layer 82, a silicon nitride layer 83 and an electrode 84, wherein the boron-doped emitter layer 81 is arranged on the upper surface of the substrate 1, the aluminum oxide layer 82 is arranged on the upper surface of the boron-doped emitter layer 81, the silicon nitride layer 83 is arranged on the upper surface of the aluminum oxide layer 82, and the electrode 84 penetrates through the aluminum oxide layer 82 and the silicon nitride layer 83 and is arranged in contact with the boron-doped emitter layer 81; the cell back structure (not marked in the figure) comprises a tunneling oxide layer 2, a phosphorus-doped polycrystalline silicon thin film layer 3, a phosphorus-doped polycrystalline silicon thin film layer 6, a silicon nitride layer 4 and an electrode 5, wherein the tunneling oxide layer 2 is positioned on the lower surface of the substrate 1, the phosphorus-doped polycrystalline silicon thin film layer 3 is positioned on the lower surface of the tunneling oxide layer 2, the phosphorus-doped polycrystalline silicon thin film layer 6 is positioned on the lower surface of the phosphorus-doped polycrystalline silicon thin film layer 3, the silicon nitride layer 4 is positioned on the lower surface of the phosphorus-doped polycrystalline silicon thin film layer 6, the electrode 5 penetrates through the silicon nitride layer 4 and part of the phosphorus-doped polycrystalline silicon thin film layer 6, and the electrode 5 and the phosphorus-doped polycrystalline silicon thin film layer 3 are arranged in a separated mode.
In other possible embodiments of the present invention, referring to fig. 10, the cell is a first P-type cell 9, and includes a cell front structure 90 and the cell back structure (not labeled in the figure), the cell front structure 90 is located on another surface of the substrate 1, the other surface of the substrate 1 is opposite to the surface of the substrate 1 on which the tunneling oxide layer 2 is disposed, and the substrate 1 is a P-type silicon wafer. The cell front structure 90 comprises an aluminum oxide layer 91, a silicon nitride layer 92 and an electrode 93, the substrate 1 comprises a local heavily doped region 94, the aluminum oxide layer 91 is arranged on the upper surface of the substrate 1, the silicon nitride layer 92 is arranged on the upper surface of the aluminum oxide layer 91, and the electrode 93 penetrates through the aluminum oxide layer 91 and the silicon nitride layer 92 and is arranged in contact with the local heavily doped region 94; the back structure (not marked in the figure) of the battery comprises a tunneling oxidation layer 2, a phosphorus-doped polycrystalline silicon thin film layer 3, a phosphorus-doped polycrystalline silicon thin film layer 6, a silicon nitride layer 4 and an electrode 5, wherein the tunneling oxidation layer 2 is positioned on the lower surface of the substrate 1, the phosphorus-doped polycrystalline silicon thin film layer 3 is positioned on the lower surface of the tunneling oxidation layer 2, the phosphorus-doped polycrystalline silicon thin film layer 6 is positioned on the lower surface of the phosphorus-doped polycrystalline silicon thin film layer 3, the silicon nitride layer 4 is positioned on the lower surface of the phosphorus-doped polycrystalline silicon thin film layer 6, the electrode 5 penetrates through the silicon nitride layer 4 and part of the phosphorus-doped polycrystalline silicon thin film layer 6, and the electrode 5 and the phosphorus-doped polycrystalline silicon thin film layer 3 are arranged in a separated mode.
In some possible embodiments of the present invention, referring to fig. 11, the cell is a second P-type cell 10, and includes a cell front structure 100 and the cell back structure (not labeled in the figure), the cell front structure 100 is located on another surface of the substrate 1, the other surface of the substrate 1 is opposite to the surface of the substrate 1 on which the tunneling oxide layer 2 is disposed, and the substrate 1 is a P-type silicon wafer. The cell front structure 100 comprises a phosphorus-doped emitter layer 101, a tunneling oxide layer 102, an in-situ phosphorus-doped polycrystalline silicon thin film layer 103, a transparent conductive layer 104 and an electrode 105, wherein the phosphorus-doped emitter layer 101 is arranged on the upper surface of the substrate 1, the tunneling oxide layer 102 is arranged on the upper surface of the phosphorus-doped emitter layer 101, the in-situ phosphorus-doped polycrystalline silicon thin film layer 103 is arranged on the upper surface of the tunneling oxide layer 102, the transparent conductive layer 104 is arranged on the upper surface of the in-situ phosphorus-doped polycrystalline silicon thin film layer 103, and the electrode 105 penetrates through the transparent conductive layer 104 and is arranged in contact with the in-situ phosphorus-doped polycrystalline silicon thin film layer 103. The back structure (not shown) of the battery comprises a tunneling oxide layer 2, a boron-doped polycrystalline silicon thin film layer 3, a boron-doped polycrystalline silicon thin film layer 6, a silicon nitride layer 4 and an electrode 5, wherein the tunneling oxide layer 2 is located on the lower surface of the substrate 1, the boron-doped polycrystalline silicon thin film layer 3 is located on the lower surface of the tunneling oxide layer 2, the boron-doped polycrystalline silicon thin film layer 6 is located on the lower surface of the boron-doped polycrystalline silicon thin film layer 3, the silicon nitride layer 4 is located on the lower surface of the boron-doped polycrystalline silicon thin film layer 6, the electrode 5 penetrates through the silicon nitride layer 4 and part of the boron-doped polycrystalline silicon thin film layer 6, and the electrode 5 and the boron-doped polycrystalline silicon thin film layer 3 are arranged in a separated mode.
The foregoing examples are merely illustrative and serve to explain some of the features of the method of the present invention. The appended claims are intended to claim as broad a scope as is contemplated, and the examples presented herein are merely illustrative of selected implementations in accordance with all possible combinations of examples. Accordingly, it is applicants' intention that the appended claims are not to be limited by the choice of examples illustrating features of the invention. Also, where numerical ranges are used in the claims, subranges therein are included, and variations in these ranges are also to be construed as possible being covered by the appended claims.
Claims (12)
1. A battery back structure, comprising:
a substrate;
the tunneling oxide layer is arranged on the surface of the substrate;
the doped polycrystalline silicon thin film layer is arranged on the surface of the tunneling oxide layer;
the diffusion polycrystalline silicon thin film layer is arranged on the surface of the doped polycrystalline silicon thin film layer, and the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer;
the silicon nitride layer is arranged on the surface of the diffusion polycrystalline silicon thin film layer;
and the electrode penetrates through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and is separated from the doped polycrystalline silicon thin film layer.
2. The battery back structure of claim 1, wherein the tunneling oxide layer has a thickness of 1-3 nm, the doped polysilicon thin film layer has a thickness of 60-130 nm, the diffused polysilicon thin film layer has a thickness of 10-30 nm, and the silicon nitride layer has a thickness of 80-100 nm.
3. The battery back structure of claim 1, wherein the sheet resistance of the diffused polysilicon thin film layer is 10-80 ohms per square.
4. A preparation method of a battery back structure is characterized by comprising the following steps:
s30: providing a substrate;
s31: forming a tunneling oxide layer on the surface of the substrate;
s32: forming a doped polycrystalline silicon thin film layer on the surface of the tunneling oxide layer;
s33: forming a diffusion polycrystalline silicon thin film layer on the surface of the doped polycrystalline silicon thin film layer, wherein the sheet resistance of the diffusion polycrystalline silicon thin film layer is smaller than that of the doped polycrystalline silicon thin film layer;
s34: forming a silicon nitride layer on the surface of the diffusion polycrystalline silicon thin film layer;
s35: and forming an electrode on the silicon nitride layer, enabling the electrode to penetrate through the silicon nitride layer and part of the diffusion polycrystalline silicon thin film layer, and enabling the electrode and the doped polycrystalline silicon thin film layer to be arranged in a separated mode.
5. The method for preparing the back structure of the battery as claimed in claim 4, wherein the step of forming the diffusion polysilicon thin film layer on the surface of the doped polysilicon thin film layer in the step S33 comprises:
and annealing the doped polycrystalline silicon thin film layer, and diffusing the doped polycrystalline silicon thin film layer at the tail section of the annealing treatment to obtain the diffused polycrystalline silicon thin film layer.
6. The method for preparing the back structure of the battery according to claim 5, wherein the temperature of the annealing treatment is 800-1000 ℃, the time of the annealing treatment is 20-40 min, the temperature of the diffusion treatment is 700-900 ℃, and the time of the diffusion treatment is 10-25 min.
7. The method of manufacturing a battery back structure according to claim 6, wherein a diffusion source of the diffusion treatment is phosphorus oxychloride.
8. The method of manufacturing a battery back structure according to claim 6, wherein a diffusion source of the diffusion treatment is any one of boron trichloride and boron tribromide.
9. The method for preparing the back structure of the battery as claimed in claim 4, wherein the step of forming a tunneling oxide layer on the surface of the substrate in the step S31 comprises:
the temperature for forming the tunneling oxide layer is controlled to be 100-600 ℃, and the reaction gas for forming the tunneling oxide layer is oxygen or laughing gas.
10. The method for preparing the back structure of the battery as claimed in claim 4, wherein the step of forming the doped polysilicon thin film layer on the surface of the tunneling oxide layer in the step S32 comprises:
the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of phosphine and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
11. The method for preparing the back structure of the battery as claimed in claim 4, wherein the step of forming the doped polysilicon thin film layer on the surface of the tunneling oxide layer in the step S32 comprises:
the temperature for forming the doped polycrystalline silicon thin film layer is controlled to be 250-550 ℃, the reaction gas for forming the doped polycrystalline silicon thin film layer is a mixed gas of diborane and silane, and the carrier gas for forming the doped polycrystalline silicon thin film layer is any one of argon or hydrogen.
12. A battery comprising a front-side structure of the battery and a back-side structure of the battery as claimed in any one of claims 1 to 3, wherein the front-side structure is located on another surface of the substrate, and the other surface of the substrate is opposite to the surface of the substrate on which the tunnel oxide layer is disposed.
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