CN114400253A - Semiconductor structure and preparation method - Google Patents

Semiconductor structure and preparation method Download PDF

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Publication number
CN114400253A
CN114400253A CN202210059897.XA CN202210059897A CN114400253A CN 114400253 A CN114400253 A CN 114400253A CN 202210059897 A CN202210059897 A CN 202210059897A CN 114400253 A CN114400253 A CN 114400253A
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layer
metal
dielectric layer
barrier layer
metal layer
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查天庸
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210059897.XA priority Critical patent/CN114400253A/en
Priority to PCT/CN2022/081218 priority patent/WO2023137851A1/en
Publication of CN114400253A publication Critical patent/CN114400253A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor

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Abstract

The embodiment of the application provides a semiconductor structure and a preparation method, wherein the semiconductor structure comprises: the stacked structure comprises a dielectric layer, an isolation layer, a metal layer and a polycrystalline silicon layer which are positioned on the surface of the substrate and stacked in sequence; wherein the material of the isolation layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.

Description

Semiconductor structure and preparation method
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method for manufacturing the same.
Background
With the continuous development of Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs), the thickness of a gate Oxide layer, which is a key indicator of the Transistor, is continuously reduced, but the thickness of the gate Oxide layer is reduced to a limit, and silicon dioxide (SiO) within 2 nanometers (nm) is used2) SiO, no longer being an ideal insulator2The thickness of the film is less than 2nm, obvious tunneling leakage begins to appear, the leakage is increased exponentially along with the continuous reduction of the thickness of the SiO2, and the SiO with the thickness of less than 1nm2The performance in terms of leakage performance is completely unacceptable.
In the related art, SiO is replaced by a substance having a high dielectric constant2As a gate oxide layer,however, the absence of oxygen in some high dielectric constant materials can cause device leakage, which can cause device reliability problems.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same.
In a first aspect, an embodiment of the present application provides a semiconductor structure, which at least includes:
the stacked structure comprises a dielectric layer, an isolation layer, a metal layer and a polycrystalline silicon layer which are positioned on the surface of the substrate and stacked in sequence;
wherein the material of the isolation layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
In some embodiments, the semiconductor structure further comprises:
and the dielectric layer is positioned between the substrate and the dielectric layer and is used for adjusting the interface state between the substrate and the dielectric layer.
In some embodiments, the semiconductor structure further comprises:
and the work function metal layer is positioned between the metal layer and the isolation layer and is used for adjusting the work function of the semiconductor structure.
In some embodiments, the dielectric layer is an HK dielectric layer;
the HK dielectric layer includes at least one of: hafnium oxide, hafnium oxynitride, aluminum oxide, zirconium oxide, or lanthanum oxide.
In a second aspect, embodiments of the present application provide a method for manufacturing a semiconductor structure, the method including:
providing a substrate, and depositing a dielectric layer on the substrate;
forming a barrier layer and a metal layer on the dielectric layer in sequence;
forming a polysilicon layer on the metal layer to form a stacked structure;
carrying out heat treatment on the stacked structure to convert the barrier layer into an isolation layer so as to form the semiconductor structure;
wherein the material of the isolation layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
In some embodiments, said sequentially forming a barrier layer and a metal layer on said dielectric layer comprises:
forming the barrier layer and the metal layer on the dielectric layer by using a first reaction gas as a reaction precursor through the first reaction gas, an inert gas and a metal target;
the first reactant gas comprises an element X; the metal target comprises an M element; the inert gas comprises at least one of: argon, neon or helium.
In some embodiments, the first reactive gas with a first flow rate is used as a reactive precursor, and the barrier layer is formed on the dielectric layer through the first reactive gas with a first flow rate, an inert gas and the metal target;
and taking the first reaction gas with the second flow rate as a reaction precursor, and forming the metal layer on the barrier layer through the first reaction gas with the second flow rate, the inert gas and the metal target.
In some embodiments, the ratio of the X element to the M element in the barrier layer is smaller than the ratio of the X element to the M element in the metal layer.
In some embodiments, the volume flow of the first reactive gas is increased from a third flow to a fourth flow in a preset flow increasing manner, and the barrier layer is formed on the dielectric layer through the first reactive gas, the inert gas and the metal target during the flow increasing process;
forming the metal layer on the barrier layer by a first reactive gas having a fourth flow rate, an inert gas, and the metal target.
In some embodiments, the ratio of the X element to the M element in the barrier layer is smaller than the ratio of the X element to the M element in the metal layer.
In some embodiments, the first reactive gas comprises at least one of: nitrogen or ammonia; the nitrogen content in the barrier layer tends to increase in a direction perpendicular to and away from the substrate.
In some embodiments, prior to forming the dielectric layer, the method further comprises:
and forming a dielectric layer on the surface of the substrate, wherein the dielectric layer is used for adjusting the interface state between the substrate and the dielectric layer.
In some embodiments, prior to forming the metal layer, the method further comprises:
and forming a work function metal layer on the surface of the barrier layer, wherein the work function metal layer is used for adjusting the work function of the semiconductor structure.
In some embodiments, the material of the metal layer comprises at least one of: titanium nitride or tantalum nitride.
In some embodiments, the heat treatment comprises an annealing process.
According to the semiconductor structure and the preparation method provided by the embodiment of the application, the stacking structure composed of the dielectric layer, the barrier layer, the metal layer and the polycrystalline silicon layer is stacked on the surface of the substrate, the stacking structure is subjected to heat treatment, the barrier layer is converted into the isolation layer, so that the isolation layer can isolate oxygen atoms in the dielectric layer from diffusing to the metal layer and the polycrystalline silicon layer, silicon dioxide is prevented from being formed on an interface between the metal layer and the polycrystalline silicon layer, and the performances of electric leakage, contact resistance value, stability and the like of the semiconductor structure are effectively improved.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1A to fig. 1C are schematic partial structural diagrams of a semiconductor structure according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 3A to 3G are schematic partial structural diagrams corresponding to a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
description of reference numerals:
101-a substrate; 102-a stacked structure; 1021-a dielectric layer; 1022-an isolation layer; 1023-a metal layer; 1024-a polysilicon layer; 103-a dielectric layer; 104-work function metal layer; 301-a substrate; 302-a dielectric layer; 303-a barrier layer; 304-a metal layer; 305-a barrier layer; 306-a metal layer; 307-a polysilicon layer; 308-an isolation layer; 309-a dielectric layer; 310-workfunction metal layer.
Detailed Description
Specific technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present application, and have no specific meaning in themselves. Thus, "module" or "unit" may be used mixedly.
The High dielectric constant (High-K) gate dielectric layer technique in the related art is to replace SiO with a High dielectric constant material2As the gate oxide layer, for example, hafnium oxide (HfO)2)，HfO2Has a dielectric constant of 25 to SiO2The dielectric layer thickness is about 6 times higher, which means that the dielectric layer thickness can be increased by about 6 times under the same voltage and electric field strength, thereby greatly reducing the grid leakage, and simultaneously, the Equivalent Oxide Thickness (EOT) of the High-k dielectric layer can be very low, and the grid capacitance can be effectively reduced. The reason why the Metal gate (Metal gate) technology and the High-K dielectric layer technology supplement each other is that the gate electric field of the transistor using the High-K dielectric layer can be made stronger, and the conventional polysilicon cannot cope with the problems of gate depletion and the like.
The current High-K metal gate (HKMG) requires several requirements for the High-K material selection, such as good thermal stability, proper band gap, and High dielectric constant (e.g., dielectric constant around 25). The related art will usually employ HfO2As a High-k dielectric layer, titanium nitride (TiN) is typically chosen for the metal gate material due to its excellent thermal stability and tunable effective work function.
However, HfO in the HKMG structure used in the related art2The dielectric layer has a certain amount of oxygen vacancies, and the missing oxygen can be diffused in other layers of the HKMG structure, and when the oxygen diffuses to the contact surface of the metal gate and the polysilicon, problems of resistance, electric leakage and reliability can be caused.
Based on the problems in the related art, embodiments of the present application provide a semiconductor structure capable of preventing oxygen atoms in a dielectric layer from diffusing, and fig. 1A to 1C are schematic partial structures of the semiconductor structure provided in embodiments of the present application. As shown in fig. 1A, an embodiment of the present application provides a semiconductor structure, where the semiconductor structure includes a substrate 101 and a stacked structure 102, and the stacked structure 102 includes a dielectric layer 1021, an isolation layer 1022, a metal layer 1023, and a polysilicon layer 1024 on a surface of the substrate 101. Wherein, the isolation layer 1022 is obtained after performing a heat treatment on the barrier layer (not shown in fig. 1A) on the surface of the dielectric layer 1021, and the isolation layer 1022 is used to prevent oxygen atoms in the dielectric layer 1021 from diffusing to the metal layer 1023 and the polysilicon layer 1024.
In some embodiments, the isolation layer 1022 is obtained after performing a heat treatment on the barrier layer on the surface of the dielectric layer 1021, and the isolation layer 1022 is used to prevent oxygen atoms in the dielectric layer 1021 from diffusing to the metal layer 1023 and the polysilicon layer 1024, so as to avoid the problem that oxygen atoms in the high-K dielectric layer 1021 form silicon dioxide at the interface between the metal layer 1023 and the polysilicon layer 1024, which leads to a failure of the semiconductor structure.
The semiconductor structure that this application embodiment provided changes the barrier layer into the isolation layer through thermal treatment to make the isolation layer can completely cut off the oxygen atom diffusion in the dielectric layer to metal level and polycrystalline silicon layer, avoid forming silicon dioxide at the interface between metal level and polycrystalline silicon layer, effectual performances such as electric leakage, contact resistance and stability that have promoted semiconductor structure.
In some embodiments, the semiconductor structure further includes a dielectric layer 103, as shown in fig. 1B, the dielectric layer 103 is located between the substrate 101 and the dielectric layer 1021, the material of the dielectric layer 103 may be silicon oxynitride or modified nano-silicon dioxide, and the interface state between the high-K dielectric material and the substrate may be effectively improved by using the silicon oxynitride or modified nano-silicon dioxide as a transition layer between the dielectric layer 302 and the substrate 301, and the influence of the dipole vibration on the carrier mobility may also be improved.
In some embodiments, the semiconductor structure further includes a work function metal layer 104, as shown in fig. 1C, the work function metal layer 104 is located on the surface of the isolation layer 1022, and is used for adjusting the work function of the semiconductor structure to solve the pinning phenomenon of the fermi level. The material of the work function metal layer 104 may be lanthanum or the like.
In some embodiments, dielectric layer 1021 is a high-K dielectric layer that includes at least one of: hafnium oxide (HfO)2) Hafnium oxynitride (HfON), aluminum oxide (Al)2O3) Zirconium oxide (ZrO)2) Hafnium silicon oxynitride (HfSiON), hafnium silicon oxide (HfSiO), and zirconium silicon oxide (ZrSiO)x) Tantalum oxide (Ta)2O5) Lanthanum oxide (La)2O3) Rare earth element oxides, rare earth element hydrides, and the like.
Based on the semiconductor structure provided in the foregoing embodiments, an embodiment of the present application provides a method for manufacturing a semiconductor structure, please refer to fig. 2, where fig. 2 is a schematic flow chart of the method for manufacturing a semiconductor structure provided in the embodiment of the present application, and the semiconductor structure provided in the embodiment of the present application may be formed through the following steps:
step S201, providing a substrate, and depositing a dielectric layer on the substrate.
Step S202, forming a barrier layer and a metal layer on the dielectric layer in sequence.
Step S203, a polysilicon layer is formed on the metal layer to form a stacked structure.
Step S204, carrying out heat treatment on the stacked structure to convert the barrier layer into an isolation layer so as to form a semiconductor structure; wherein, the material of the isolating layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
With reference to fig. 3A to 3G, a method for fabricating a semiconductor structure according to an embodiment of the present disclosure is described in detail.
As shown in fig. 3A, step S201 is performed, a substrate 301 is provided, and a dielectric layer 302 is deposited on the substrate 301.
In some embodiments, the substrate 301 may be made of a semiconductor material, such as one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
In the embodiment of the present application, the dielectric layer 302 may be formed on the surface of the substrate by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
In some embodiments, the dielectric layer 302 may be a dielectric layer formed of a high-K (high dielectric constant) material, and the material of the dielectric layer 302 may be a high-K material such as hafnium oxide, hafnium oxynitride, aluminum oxide, zirconium oxide, or lanthanum oxide.
Referring to fig. 3B and fig. 3C, step S202 is performed to sequentially form a barrier layer 303 and a metal layer 304 on the dielectric layer 302, in which the barrier layer 303 and the metal layer 304 may be formed on the dielectric layer 302 by using a first reaction gas as a reaction precursor, and by using the first reaction gas, an inert gas and a metal target.
In some embodiments, the first reactive gas may include an element X, for example, the element X may be an element nitrogen, and the first reactive gas may be nitrogen; the metal target comprises an element M, for example, the element M may be a titanium element, and the metal target may be a titanium target; the inert gas includes at least argon, neon or helium.
In the embodiment of the present application, forming the barrier layer 303 and the metal layer 304 may be implemented by:
step S2021, forming a barrier layer on the dielectric layer by using the first reaction gas with the first flow rate as a reaction precursor, and passing the first reaction gas with the first flow rate, the inert gas, and the metal target.
In the embodiment of the present invention, the barrier layer 303 may be formed on the dielectric layer 302 by physical vapor deposition, for example, when the first reactive gas is nitrogen, the metal target is titanium target, and the inert gas is one of argon, neon or helium, the barrier layer 303 may be formed on the dielectric layer 302 by physical vapor deposition.
In some embodiments, the first reactant gas may also be ammonia.
In this embodiment, the first flow rate may be 0 milliliter per minute (sccm), that is, when the barrier layer 303 is formed by physical vapor deposition, the first reaction gas is not introduced, only any one inert gas is introduced as a working gas during physical vapor deposition, a titanium target is ionized by the inert gas, and titanium ions are deposited on the surface of the dielectric layer 302 to form the barrier layer 303, where the material of the barrier layer 303 is pure titanium, that is, the barrier layer 303 includes only M element and does not include X element.
Step S2022, using the first reaction gas with the second flow rate as a reaction precursor, and forming a metal layer on the barrier layer through the first reaction gas with the second flow rate, the inert gas, and the metal target.
In some embodiments, after forming the barrier layer 303, the volume flow rate of the first reactive gas is changed, and the metal layer 304 may be formed on the barrier layer 303 by physical vapor deposition through the first reactive gas having the second flow rate, the inert gas and the metal target, as shown in fig. 3B, where the material of the metal layer 304 is titanium nitride.
In some embodiments, the second flow rate of the first reactive gas may be 5 to 200 sccm.
In the embodiment of the present application, in the barrier layer 303 and the metal layer 304, a ratio of the X element to the M element in the barrier layer 303 is smaller than a ratio of the X element to the M element in the metal layer 304, for example, ratios of the X element (i.e., an element corresponding to the first reaction gas) to the M element (i.e., an element corresponding to the metal target) in the barrier layer 303 and the metal layer 304 are a first ratio and a second ratio, respectively, and the first ratio is smaller than the second ratio.
In some embodiments, the predetermined ratio may refer to a ratio of X element to M element when the metal layer 304 is in a saturated state, for example, when the metal layer is titanium nitride, a ratio of Ti-N bonds reaches a ratio of nitrogen element to titanium element when the metal layer is in a saturated state, and at this time, the metal layer 304 has no extra Ti bonds (titanium bonds) and cannot be combined with more N bonds (nitrogen bonds), and the predetermined ratio is equal to the second ratio of the metal layer 304.
In some embodiments, the barrier layer 303 is pure titanium, i.e., there is no X element in the barrier layer 303, the first ratio (i.e., the ratio of the X element to the M element in the barrier layer 303) is 0, and during the thermal treatment, oxygen atoms in the dielectric layer 302 diffuse into the barrier layer 303, and the oxygen atoms combine with titanium atoms in the barrier layer 303 to form a barrier layer, which is titanium oxide at this time, so that the oxygen atoms in the dielectric layer 302 do not further diffuse.
In some embodiments, the thermal treatment process may be an annealing process, and annealing the semiconductor structure may eliminate lattice defects and improve the performance of the semiconductor device.
In some embodiments, forming the barrier layer and the metal layer may also be achieved by:
step S2023, increasing the volume flow of the first reactive gas from the third flow to a fourth flow according to a preset flow increasing manner, and forming a barrier layer on the dielectric layer by using the first reactive gas, the inert gas, and the metal target.
In some embodiments, the preset flow rate increasing manner may be that the volume flow rate of the first reaction gas is gradually increased with the passage of time until the target volume flow rate of the first reaction gas is reached; it is also possible that the volume flow rate of the first reaction gas is maintained for a certain period of time every time the volume flow rate of the first reaction gas increases until the target volume flow rate of the first reaction gas is reached.
In the embodiment of the present application, the barrier layer 305 may be formed on the dielectric layer 302 by physical vapor deposition, as shown in fig. 3C, and the volume flow rate of the first reaction gas when forming the barrier layer 305 may be increased by a predetermined flow rate increase manner.
In some embodiments, when the first reactive gas is nitrogen gas, the nitrogen content in the barrier layer 305 gradually increases from the surface in contact with the dielectric layer 302 as the volume flow rate of the nitrogen gas gradually increases, that is, the barrier layer 305 formed by vapor deposition has a concentration gradient of nitrogen element, the nitrogen content is the lowest at the position where the barrier layer 305 is in contact with the dielectric layer 302, the nitrogen content in the barrier layer 305 changes in a trend of increasing gradient, and the nitrogen content is the largest at the upper surface of the barrier layer 305.
In some embodiments, the barrier layer 305 is formed when or after the volumetric flow rate of the first reactant gas is gradually increased to the fourth flow rate for a period of time.
In some embodiments, when the volume flow rate of the first reactive gas is the fourth flow rate, the amount of the X element and the M element in the partial barrier layer 305 is saturated, the partial barrier layer 305 is MX, the partial barrier layer 305 has no excess M bonds, and the partial barrier layer 305 has excess M bonds during the increase of the volume flow rate of the first reactive gas, the partial barrier layer 305 has an unsaturated state.
In the embodiment, when the first reactive gas is nitrogen, the metal target is a titanium target, and the inert gas is one of argon, neon, or helium, the Ti — N bond in the barrier layer 305 is in an unsaturated state, and has an excess Ti bond.
Step S2024, forming a metal layer on the barrier layer by the first reactive gas with the fourth flow rate, the inert gas, and the metal target.
In some embodiments, after forming the barrier layer 305 with a concentration gradient, a metal layer 306 may be formed on the barrier layer 305 by physical vapor deposition by using a first reactive gas with a fourth flow rate, an inert gas and a metal target, as shown in fig. 3C.
In some embodiments, in the barrier layer 305 and the metal layer 306, a ratio of the X element to the M element in the barrier layer 305 is smaller than a ratio of the X element to the M element in the metal layer 306, for example, a ratio of the X element (i.e., the element corresponding to the first reaction gas) to the M element (i.e., the element corresponding to the metal target) in the barrier layer 305 and the metal layer 306 is a third ratio and a fourth ratio, respectively, where the third ratio is smaller than the fourth ratio.
In some embodiments, the predetermined ratio may refer to a ratio of X element to M element when the metal layer 306 is in a saturated state, for example, when the metal layer is titanium nitride, a ratio of Ti-N bond reaches the ratio of nitrogen element to titanium element when the metal layer is in a saturated state, and at this time, the metal layer 306 has no extra Ti bond (titanium bond) and cannot be combined with more N bond (nitrogen bond), and the predetermined ratio may be equal to a fourth ratio of the metal layer 306.
In some embodiments, when the thermal treatment is performed, oxygen atoms in the dielectric layer 302 diffuse into the barrier layer 305, the oxygen atoms combine with excess Ti bonds in the barrier layer 305 to form Ti-O bonds and Ti-O-N bonds, forming a barrier layer having titanium oxide and titanium oxynitride, where the barrier layer is a mixture of titanium oxide, titanium oxynitride, and titanium nitride, and the excess Ti bonds in the barrier layer 305 consume the diffused oxygen atoms so that the oxygen atoms in the dielectric layer 302 do not further diffuse.
Referring to fig. 3D, step S203 is performed to form a polysilicon layer 307 on the metal layer 304 or the metal layer 306 to form a stacked structure. It should be noted that fig. 3D illustrates an example of forming the polysilicon layer 307 on the metal layer 304.
In the embodiment of the present application, the polysilicon layer 307 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition, as shown in fig. 3D, a schematic structural diagram of forming the polysilicon layer 307 on the metal layer 304 is exemplarily shown in fig. 3D, and a material of the polysilicon layer 307 may be polysilicon.
In some embodiments, the metal layer (304 or 306) and the polysilicon layer 307 may constitute a gate of the semiconductor structure, and the dielectric layer 302 may constitute a gate oxide of the semiconductor structure.
Referring to fig. 3E, step S204 is performed to perform a thermal treatment on the stacked structure to transform the barrier layer 303 or the barrier layer 305 into the isolation layer 308.
In some embodiments, the thermal treatment may be an annealing treatment, and annealing the semiconductor structure may eliminate lattice defects and improve the performance of the semiconductor device.
In some embodiments, the time for heat treating the stacked structure may be between 10 and 60 seconds, the annealing atmosphere may be a nitrogen atmosphere, an inert gas atmosphere, or a nitrogen-hydrogen mixed atmosphere, and the annealing temperature may be between 400 degrees celsius (° c) and 1100 ℃.
In some embodiments, the stacked structure is subjected to a heat treatment, the barrier layer 303 or the barrier layer 305 is transformed into the isolation layer 308, and a material of the isolation layer 308 after the heat treatment includes MX, M represents a metal element, the metal element may be titanium, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
It should be noted that the preset proportioning value refers to a proportioning value of the X element and the M element in the metal layer 304 or the metal layer 305, and when the proportioning value of the X element and the M element in the isolation layer 308 is smaller than the preset proportioning value, the M bond of the isolation layer 308 is not saturated; when the ratio of the X element to the M element in the isolation layer 308 is equal to the predetermined ratio, the M bond of the isolation layer 308 is saturated.
In some embodiments, when the barrier layer 303 is made of pure titanium, when the stacked structure is subjected to a heat treatment, oxygen atoms in the dielectric layer 302 diffuse into the barrier layer 303, Ti bonds in the barrier layer 303 react with the oxygen atoms to form Ti — O bonds, at this time, the Ti bonds in the barrier layer 303 consume the oxygen atoms diffused into the barrier layer 303 to form the isolation layer 308 made of titanium oxide, and the isolation layer 308 blocks the oxygen atoms from continuing to diffuse into the polysilicon layer 307, so that the problem of failure of the semiconductor structure due to formation of silicon dioxide between the oxygen atoms and the polysilicon layer 307 is avoided, and the performance of the semiconductor structure is improved.
In some embodiments, when the oxygen atoms diffused into the dielectric layer 302 are insufficient, the Ti bonds in the isolation layer 308 remain after the isolation layer 308 is formed, the isolation layer 308 is unsaturated titanium oxide, and when the oxygen atoms are subsequently diffused, the oxygen atoms are bonded with the Ti bonds in the isolation layer 308 again to block the diffusion of the oxygen atoms.
In some embodiments, when the barrier layer 305 is titanium nitride with a nitrogen concentration gradient, the stacked structure is subjected to a heat treatment, oxygen atoms in the dielectric layer 302 diffuse to the barrier layer 305, and excess Ti bonds in the barrier layer 303 react with the oxygen atoms to form Ti-O bonds and Ti-O-N bonds, at this time, the isolation layer 308 has Ti-O bonds, Ti-O-N bonds, and Ti-N bonds, and titanium oxide, titanium oxynitride, and titanium nitride in the isolation layer 308 block oxygen atoms from continuing to diffuse to the polysilicon layer 307, so as to avoid the problem that the oxygen atoms and the polysilicon layer 307 form silicon dioxide, which results in failure of the semiconductor structure, and improve the performance of the semiconductor structure.
According to the preparation method of the semiconductor structure, the stacked structure composed of the dielectric layer, the barrier layer, the metal layer and the polycrystalline silicon layer is sequentially formed on the substrate, the stacked structure is subjected to heat treatment, the barrier layer is converted into the isolation layer, so that the isolation layer can isolate missing oxygen in the dielectric layer from diffusing to the metal layer and the polycrystalline silicon layer, and the performances of the semiconductor structure such as electric leakage, contact resistance and stability are effectively improved.
Referring to fig. 3F, before forming the dielectric layer 302, the embodiment of the present invention further includes forming a dielectric layer 309 on the surface of the substrate 301 for adjusting an interface state between the substrate 301 and the dielectric layer 302.
In some embodiments, the material of the dielectric layer 309 may be silicon oxynitride, and the silicon oxynitride is used as a transition layer between the dielectric layer 302 and the substrate 301, so that the interface state between the high-K dielectric material and the substrate can be effectively improved, and the influence of the dipole vibration on the carrier mobility can also be improved.
Referring to fig. 3G, before forming the metal layer 304 or the metal layer 306, the embodiment of the present application further includes forming a work function metal layer 310 on a surface of the barrier layer (i.e., the isolation layer 308 after the heat treatment in fig. 3G), wherein the work function metal layer 310 is used for adjusting a work function of the semiconductor structure.
In some embodiments, the material of the work function metal layer 310 may be lanthanum (La), and the work function metal layer 310 may solve the pinning phenomenon of the fermi level.
In some embodiments, the ratio of the flow rate of the first reaction gas to the total gas flow rate during the formation of the barrier layer and the metal layer is 0-0.5, and the volume flow rate of the inert gas is 2 to 40 sccm.
In some embodiments, the first reactive gas comprises at least one of: nitrogen or ammonia; the material of the metal layer (304 or 306) comprises at least one of: titanium nitride and tantalum nitride.
In some embodiments, the dielectric layer 302 is an HK dielectric layer, the HK dielectric layer comprising at least one of: hafnium oxide (HfO)2) Hafnium oxynitride (HfON), aluminum oxide (Al)2O3) Zirconium oxide (ZrO)2) Hafnium silicon oxynitride (HfSiON), hafnium silicon oxide (HfSiO), and zirconium silicon oxide (ZrSiO)x) Tantalum oxide (Ta)2O5) Lanthanum oxide (La)2O3) Rare earth element oxides, rare earth element hydrides, and the like.
In some embodiments, the dc power supply power may be 500 watts (W) to 5KW during deposition of the metal layer (304 or 306).
In some embodiments, the metal layer (304 or 306) comprises at least one of: titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), tantalum aluminum nitride (TaAlN), titanium aluminum nitride (TiAlN), and the like.
In some embodiments, the dielectric layer 302 may be 2 to 10 nanometers (nm) thick and the metal layer (304 or 306) 1 to 100nm thick.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A semiconductor structure, comprising:
the stacked structure comprises a dielectric layer, an isolation layer, a metal layer and a polycrystalline silicon layer which are positioned on the surface of the substrate and stacked in sequence;
wherein the material of the isolation layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
2. The semiconductor structure of claim 1, further comprising:
a dielectric layer located between the substrate and the dielectric layer.
3. The semiconductor structure of claim 1, further comprising:
a work function metal layer located between the metal layer and the isolation layer.
4. The semiconductor structure of claim 1, wherein the dielectric layer is an HK dielectric layer;
the HK dielectric layer includes at least one of: hafnium oxide, hafnium oxynitride, aluminum oxide, zirconium oxide, or lanthanum oxide.
5. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate, and depositing a dielectric layer on the substrate;
forming a barrier layer and a metal layer on the dielectric layer in sequence;
forming a polysilicon layer on the metal layer to form a stacked structure;
carrying out heat treatment on the stacked structure to convert the barrier layer into an isolation layer so as to form the semiconductor structure;
wherein the material of the isolation layer comprises MX, M represents a metal element, and X represents at least one of the following: oxygen element or nitrogen element, and the ratio of the X element to the M element in MX is not more than the preset ratio.
6. The method of claim 5, wherein the sequentially forming a barrier layer and a metal layer on the dielectric layer comprises:
forming the barrier layer and the metal layer on the dielectric layer by using a first reaction gas as a reaction precursor through the first reaction gas, an inert gas and a metal target;
the first reactant gas comprises an element X;
the metal target comprises an M element;
the inert gas comprises at least one of: argon, neon or helium.
7. The method of claim 6, wherein the barrier layer is formed on the dielectric layer by the first reactive gas with a first flow rate, the inert gas, and the metal target as a reactive precursor;
and taking the first reaction gas with the second flow rate as a reaction precursor, and forming the metal layer on the barrier layer through the first reaction gas with the second flow rate, the inert gas and the metal target.
8. The method of claim 7, wherein the ratio of the X element to the M element in the barrier layer is smaller than the ratio of the X element to the M element in the metal layer.
9. The method according to claim 6, wherein the volume flow rate of the first reactive gas is increased from a third flow rate to a fourth flow rate in a preset flow rate increasing manner, and the barrier layer is formed on the dielectric layer by the first reactive gas, the inert gas and the metal target material during the flow rate increasing process;
forming the metal layer on the barrier layer by a first reactive gas having a fourth flow rate, an inert gas, and the metal target.
10. The method of claim 9, wherein the ratio of the X element to the M element in the barrier layer is smaller than the ratio of the X element to the M element in the metal layer.
11. The method of claim 9, wherein the first reactant gas comprises at least one of: nitrogen or ammonia;
the nitrogen content in the barrier layer tends to increase in a direction perpendicular to and away from the substrate.
12. The method of claim 5, wherein prior to forming the dielectric layer, the method further comprises:
and forming a dielectric layer on the surface of the substrate, wherein the dielectric layer is used for adjusting the interface state between the substrate and the dielectric layer.
13. The method of claim 5, wherein prior to forming the metal layer, the method further comprises:
and forming a work function metal layer on the surface of the barrier layer, wherein the work function metal layer is used for adjusting the work function of the semiconductor structure.
14. The method of claim 5, wherein the material of the metal layer comprises at least one of: titanium nitride or tantalum nitride.
15. The method of claim 5, wherein the heat treatment comprises an annealing process.
CN202210059897.XA 2022-01-19 2022-01-19 Semiconductor structure and preparation method Pending CN114400253A (en)

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