CN114371596A - Mask and correction method thereof - Google Patents
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- CN114371596A CN114371596A CN202210279764.3A CN202210279764A CN114371596A CN 114371596 A CN114371596 A CN 114371596A CN 202210279764 A CN202210279764 A CN 202210279764A CN 114371596 A CN114371596 A CN 114371596A
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- 238000012937 correction Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000013461 design Methods 0.000 claims abstract description 33
- 210000000746 body region Anatomy 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 26
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
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Abstract
The invention provides a mask and a correction method thereof. The correction method of the mask comprises the steps of providing the mask, wherein a plurality of grid patterns are formed in the mask, the grid patterns comprise a first grid pattern and a second grid pattern, the designed distance between the first grid pattern and the second grid pattern is smaller than a set value, the first grid pattern and the second grid pattern are opposite in position, and when the mask is subjected to pattern correction, the boundary of the part, close to the second grid pattern, of the first grid pattern is moved outwards in the direction away from the second grid pattern. When the mask is used for manufacturing the grid, each grid pattern corresponds to a grid, the shape of the grid corresponding to the first grid pattern and the second grid pattern with the design interval smaller than a set value is closer to the design shape and is not easy to contact with each other, the short circuit problem between the grids can be improved, and the electrical property of a semiconductor device is improved. The invention also provides a mask plate corrected by the mask plate correction method.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a mask and a correction method thereof.
Background
The photolithography technique is a crucial technique in the semiconductor manufacturing technology, and can transfer a pattern from a mask to a silicon wafer to form a semiconductor product meeting design requirements.
Semiconductor products such as CMOS (Complementary Metal Oxide Semiconductor) transistors typically include a gate. In advanced processes, the step of forming the gate typically includes: and transferring the grid pattern on the mask plate to the semiconductor substrate by utilizing the mask plate through photoetching and etching processes to form the grid.
However, when the gate pattern on the mask is transferred onto the semiconductor substrate, the gate pattern may be deformed, so that the shape of the gate obtained actually deviates from the designed shape, and thus the gates are easily contacted with each other to cause short circuit, and the turn-on voltage of the gate of the semiconductor device deviates from a predetermined value, which affects the electrical performance of the semiconductor device.
Disclosure of Invention
The invention provides a mask and a correction scheme thereof, which can improve the short circuit problem between grids, improve the electrical property of the grids and further improve the electrical property of a semiconductor device.
In order to achieve the above object, an aspect of the present invention provides a reticle correcting method. The correction method of the mask comprises the following steps: providing a mask, wherein a plurality of gate patterns are formed in the mask, the plurality of gate patterns comprise a first gate pattern and a second gate pattern, the design interval of the first gate pattern and the design interval of the second gate pattern are smaller than a set value, the first gate pattern and the second gate pattern are opposite in position, and when the mask is subjected to pattern correction, the middle part of the boundary, close to the second gate pattern, of the first gate pattern is moved outwards in the direction away from the second gate pattern.
Optionally, the first gate pattern is U-shaped, the second gate pattern is I-shaped, and one end of the second gate pattern is located in the opening of the first gate pattern; when the mask is subjected to pattern correction, the middle part of the boundary of the first grid pattern and the second grid pattern, which is opposite to the long edge, is moved outwards in the direction away from the second grid pattern.
Optionally, the first gate pattern and the second gate pattern both extend in the same direction, and when the mask is subjected to pattern correction, the middle part of the first gate pattern close to the long side of the second gate pattern is moved outward in a direction away from the second gate pattern.
Optionally, the gate pattern includes a body region corresponding to the active region and an end cap region located at an end of the body region, where the end cap region corresponds to the isolation region located at the side of the active region; when the pattern of the mask is corrected, the end face width of the end cover area far away from the main body area is larger than the end face width of the main body area.
Optionally, the top view shape of the end cap region is trapezoidal, or the end face of the end cap region far away from the main body region is connected with the end face arc close to the main body region.
Optionally, in an extension direction of the gate pattern, a length of the body region is equal to a width of the active region, and a length of the cap region is 10nm to 24 nm.
Optionally, the set value is less than or equal to 45 nm.
Optionally, when the mask is subjected to pattern correction, the moving amount of the partial boundary of the first gate pattern close to the second gate pattern moving outwards in the direction away from the second gate pattern is 5nm to 10 nm.
Another aspect of the present invention provides a mask, wherein a plurality of gate patterns are formed in the mask, and the gate patterns are patterns corrected by the correction method of the mask.
According to the mask and the correction method thereof, a plurality of grid patterns are formed in the mask, wherein the grid patterns comprise a first grid pattern and a second grid pattern, the design interval of the first grid pattern and the second grid pattern is smaller than a set value, the first grid pattern and the second grid pattern are opposite in position, and when the mask is subjected to pattern correction, the middle part of the first grid pattern, which is close to the boundary of the second grid pattern, is moved outwards in the direction away from the second grid pattern. When the mask is used for manufacturing the grid, each grid pattern corresponds to one grid, and the middle part of the first grid pattern close to the boundary of the second grid pattern is moved outwards along the direction far away from the second grid pattern, so that the shapes of the grids corresponding to the first grid pattern and the second grid pattern with the design interval smaller than the set value are closer to the design shape and are not easy to contact with each other, the short circuit problem between the grids can be further improved, particularly the short circuit problem between the grids in the area with the design interval smaller than the set value between two adjacent grids is solved, and the electrical property of a semiconductor device is improved.
Furthermore, the grid pattern comprises a main body area corresponding to the position of the active area and an end cover area positioned at the end part of the main body area, the end cover area corresponds to the position of the isolation area positioned at the side edge of the active area, and when the pattern of the mask is corrected, the width of the end face, far away from the main body area, of the end cover area is larger than the width of the end face of the main body area, so that when the grid is manufactured by using the mask, the corner angle of the end part of the formed grid can be close to 90 degrees, namely the end part shape of the grid can be closer to the designed rectangular shape, the problem that the length of the end part of the grid extending out of the active area is shortened and the problem that the starting voltage of the grid deviates from a preset value are improved, and the electrical performance of a semiconductor device is improved.
Drawings
Fig. 1 is a design diagram of a gate pattern according to an embodiment of the invention.
FIG. 2 is a top view of a reticle according to an embodiment of the invention.
Fig. 3 is a design diagram of a gate pattern according to an embodiment of the invention.
FIG. 4 is a top view of a reticle according to an embodiment of the invention.
Fig. 5 is a design diagram of a gate pattern according to an embodiment of the invention.
FIG. 6 is a top view of a reticle according to an embodiment of the invention.
Fig. 7 is a schematic plan view of a gate pattern according to an embodiment of the invention.
Fig. 8 is a schematic plan view of a gate pattern according to an embodiment of the invention.
FIG. 9 is a cross-sectional SEM view of two gates in an embodiment of the invention.
Fig. 10 is a schematic plan view of a semiconductor device.
Description of reference numerals: 10-a gate pattern; 10 a-a body region; 10 b-end cap region; 11-a first gate pattern; 12-a second gate pattern; 13-a gate; 14-active region.
Detailed Description
When a grid is manufactured by using a mask through photoetching, etching process and the like, grid patterns are easy to deform in the copying process, so that the shape of the actually obtained grid is deviated from the designed shape, especially the deformation of two grid patterns which are opposite in position and small in design distance is obvious, the grids corresponding to the two grid patterns are easy to contact with each other to cause short circuit, and the electrical property of a semiconductor device is seriously influenced.
In order to improve the short circuit problem between gates, improve the electrical performance of the gates, and improve the electrical performance of semiconductor devices, this embodiment provides a method for correcting a mask, where the method for correcting a mask includes: providing a mask, wherein a plurality of gate patterns are formed in the mask, the plurality of gate patterns comprise a first gate pattern and a second gate pattern, the design interval of the first gate pattern and the design interval of the second gate pattern are smaller than a set value, the first gate pattern and the second gate pattern are opposite in position, and when the mask is subjected to pattern correction, the boundary of the part, close to the second gate pattern, of the first gate pattern is moved outwards in the direction away from the second gate pattern. When the mask is used for manufacturing the grid (also called as a grid structure), each grid pattern corresponds to a grid, and because the partial boundary of the first grid pattern close to the second grid pattern is moved outwards along the direction far away from the second grid pattern, the shapes of the grids corresponding to the first grid pattern and the second grid pattern with the designed interval smaller than the set value are closer to the designed shape and are not easy to contact with each other, so that the short circuit problem between the grids can be improved, particularly the short circuit problem between the grids in the area with the designed interval smaller than the set value between the two adjacent grids is improved, and the electrical property of a semiconductor device is improved.
In this embodiment, when the gate pattern in the mask is subjected to pattern correction, the middle part of the boundary of the first gate pattern, where the design pitch is smaller than the set value, close to the second gate pattern is moved outward in the direction away from the second gate pattern, so that the shape of the obtained gate (corresponding to the first gate pattern or/and the second gate pattern) is closer to the design shape, which is beneficial to improving the short circuit problem between gates, improving the electrical performance of the gate, and further improving the electrical performance of a semiconductor device including the gate.
The mask correction method proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As used herein, the singular forms "a", "an" and "the" may include the plural forms, the term "or" is used in a generic sense including "and/or" and, further, the terms "first", "second" and "the" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or at least two of the feature unless the content clearly dictates otherwise.
It should be noted that reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "one embodiment" or "the present embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Fig. 1 is a design diagram of a gate pattern according to an embodiment of the invention. FIG. 2 is a top view of a reticle according to an embodiment of the invention, the reticle of FIG. 2 having a pattern corresponding to the gate pattern of FIG. 1. As shown in fig. 1, the design interval d between the first gate pattern 11 and the second gate pattern 12 is less than a set value a, which may be 45nm or less. The first gate pattern 11 may have a U-shape, the second gate pattern 12 may have an I-shape, and one end of the second gate pattern 12 may be located in the opening of the first gate pattern 11, that is, the first gate pattern 11 may have a ring shape and surround one end of the second gate pattern 12, or one end of the second gate pattern 12 may extend into the opening of the first gate pattern 11.
In order to avoid the contact between the gates corresponding to the first gate pattern 11 and the second gate pattern 12, when the mask is subjected to pattern correction, as shown in fig. 2, the middle portion of the boundary between the long sides of the first gate pattern 11 and the second gate pattern 12 (i.e., the inner boundary between the two U-shaped side pillars) is moved outward in a direction away from the second gate pattern 12. When the width of the first gate pattern 11 is narrow, the entire intermediate region of the portion of the first gate pattern 11 close to the second gate pattern 12 may be moved outward in a direction away from the second gate pattern 12 as shown in fig. 2 when pattern correction is performed on the reticle.
In this embodiment, although the first gate pattern in the mask is different from the first gate pattern in the design drawing in shape, when the gate is manufactured by using the mask, the gate corresponding to the first gate pattern actually obtained is closer to the pattern in the design drawing (compared to the unmodified mask) due to the reflection action, the refraction action, and the like of the light.
As shown in fig. 2, in this embodiment, when the mask is subjected to pattern correction, the width of the portion of the second gate pattern 12 outside the first gate pattern 11 may be increased, which is helpful to make the gate corresponding to the second gate pattern 12 closer to the designed shape, and improve the pattern accuracy and electrical performance of the gate corresponding to the second gate pattern 12.
Fig. 3 is a design diagram of a gate pattern according to an embodiment of the invention. FIG. 4 is a top view of a reticle according to an embodiment of the invention, the reticle of FIG. 4 having a pattern corresponding to the gate pattern of FIG. 3. As shown in fig. 3, the first gate pattern 11 and the second gate pattern 12 are elongated in the same direction, for example, the first gate pattern 11 and the second gate pattern 12 are rectangular and have opposite long sides, and the distance between the first gate pattern 11 and the second gate pattern 12 may be smaller than a set value a. When the first gate pattern 11 and the second gate pattern 12 are subjected to pattern correction, as shown in fig. 4, the middle portion of the first gate pattern 11 near the long side of the second gate pattern 12 may be moved outward in a direction away from the second gate pattern 12.
As shown in fig. 3 and 4, when the width of the first gate pattern 11 is large, when the middle portion of the first gate pattern 11 moves outward in the direction away from the second gate pattern 12, only the middle portion of the first gate pattern 11 close to the long side of the second gate pattern 12 may move outward in the direction away from the second gate pattern 12, and the other boundaries of the first gate pattern may not be changed, so that the shape of the gate corresponding to the first gate pattern 11 may be closer to the designed shape, which is helpful for improving the electrical performance of the gate.
As shown in fig. 3 and 4, in an embodiment, the second gate pattern 12 is located between the two first gate patterns 11, and when performing pattern correction on the reticle, the middle portions of the two first gate patterns 11 close to the long sides of the second gate pattern 12 may be respectively moved outward in a direction away from the second gate pattern 12.
Fig. 5 is a design diagram of a gate pattern according to an embodiment of the invention. FIG. 6 is a top view of a reticle according to an embodiment of the invention, the reticle of FIG. 6 having a pattern corresponding to the gate pattern of FIG. 5. As shown in fig. 5, two second gate patterns 12 are disposed on the side of the first gate pattern 11, the two second gate patterns 12 extend along the extending direction of the first gate pattern 11 and are arranged along the extending direction, and the design distances between the two second gate patterns 12 and the first gate pattern 11 may be smaller than the set value a. When the mask is subjected to pattern correction, as shown in fig. 6, the middle portions of the boundaries of the first gate patterns 11 respectively opposite to the two second gate patterns 12 may be moved outwards in a direction away from the second gate patterns 12, so as to prevent the gates corresponding to the first gate patterns 11 and the second gate patterns 12 from contacting.
In this embodiment, when performing pattern correction on the reticle, the first gate pattern 11 and the second gate pattern 12 with a design pitch of less than 45nm may be corrected, that is, the set value may be equal to 45 nm. But not limited thereto, the set value a may be less than 45nm, or the set value may be set according to actual circumstances.
When the mask is subjected to pattern correction, the amount of movement for moving the boundary of the first gate pattern 11 close to the second gate pattern 12 outward in the direction away from the second gate pattern 12 may be 5nm to 10nm, and specifically, the amount of movement for moving the middle portion of the boundary of the first gate pattern 11 close to the second gate pattern 12 outward in the direction away from the second gate pattern 12 may be 5nm to 10 nm. Research shows that when the moving amount of the partial boundary of the first gate pattern 11 is within the range of 5nm to 10nm, the patterns of the gates corresponding to the first gate pattern 11 and the second gate pattern 12 are both close to the design pattern, which is helpful for improving the pattern precision of the gates, improving the turn-on voltage precision of the gates, and further improving the electrical performance of the semiconductor device. But not limited thereto, in other embodiments, the distance that the portion of the boundary of the first gate pattern 11 close to the second gate pattern 12 is moved outward in the direction away from the second gate pattern 12 may be adjusted as needed when patterning the reticle. In the case of pattern correction on the reticle, the amount of movement by which the boundary of the portion of the first gate pattern 11 close to the second gate pattern 12 is moved outward in the direction away from the second gate pattern 12 is based on the original position of the boundary of the first gate pattern 11 in the design drawing.
Fig. 10 is a schematic plan view of a semiconductor device. As shown in fig. 10, the semiconductor device includes a plurality of Active areas 14 (AA) and a plurality of gates 13, wherein an isolation region (e.g., a blank region between the Active areas 14) is located between adjacent Active areas 14, and the gates 13 are disposed across the Active areas 14. When the Gate 13 is manufactured by using the conventional mask (unmodified mask), as shown in fig. 10, the angle of the obtained end corner (for example, in the dashed line frame of fig. 10) of the Gate 13 is greatly different from 90 degrees with respect to the design shape of the Gate, and the end of the Gate 13 is easily shortened (Gate end cap shorting), so that the turn-on voltage of the Gate 13 is incorrect, and the electrical performance of the semiconductor device is seriously affected.
FIG. 7 is a schematic plan view of a gate pattern of a reticle according to an embodiment of the invention. As shown in fig. 7, the gate pattern 10 may include a body region 10a corresponding to the position of the active region 14 and an end cap region 10b located at an end of the body region 10 a. Note that the gate pattern 10 may include a first gate pattern 11 and a second gate pattern 12.
Specifically, in the extending direction of the gate pattern 10, taking fig. 7 as an example, the length of the body region 10a is greater than the width of the active region 14, i.e., the body region 10a may extend out of the active region 14. Without being limited thereto, in other embodiments, the length of the body region 10a may be equal to the width of the active region 14, i.e. the orthographic projections of the body regions 10a may all fall on the active region 14. The cap region 10b may correspond to an isolation region (e.g., a blank region at a side of the active region 14) at a side of the active region 14, that is, the cap region 10b extends out of the active region 14 and corresponds to the isolation region.
In one embodiment, in the extension direction of the gate pattern 10, the length of the body region 10a may be equal to the width of the corresponding active region 14, and the length of the cap region 10b may be 10nm to 24 nm. That is, the length of the gate pattern 10 extending from the active region 14 may be 10nm to 24nm, so that the coverage of the gate corresponding to the gate pattern 10 on the active region may be ensured, which is helpful for improving the performance of the semiconductor device. But not limited thereto, in other embodiments, the length of the gate pattern extending from the active region may be determined according to practical circumstances.
In an embodiment, the end face width of the cap region 10b far from the body region 10a is d2, and the end face width of the body region 10a is d1, when a mask is subjected to pattern correction, d2 can be made larger than d1, so that when the gate is manufactured by using the mask, the corner angle of the end part of the formed gate can be close to 90 degrees, namely the end part of the gate is made to be closer to a designed rectangular shape, which is beneficial to improving the problem that the length of the end part of the gate extending out of the active region is shortened, the problem that the starting voltage of the gate deviates from a preset value, and the electrical performance of a semiconductor device is improved.
The end face width d2 of the end cap region 10b of the gate pattern is larger than the end face width d1 of the body region 10a, so that the gate end face profile is obtained to be straight. FIG. 9 is a cross-sectional SEM view of two gates in an embodiment of the invention. As shown in fig. 9, when the profile of the end face of the obtained gate is relatively straight, the contact area when the end faces of two adjacent gates are connected on the isolation Structure (STI) is relatively large, which helps to improve the reliability of the gate connection. For example, one of the two gates with end faces connected is a gate of a PMOS, and the other is a gate of an NMOS, when the end faces of the gates of the PMOS and the NMOS are both relatively straight, the connection reliability of the gates of the PMOS and the NMOS is relatively high, which is beneficial to simultaneously improving the performance of the PMOS and the NMOS.
As an example, as shown in fig. 7, the top view shape of the end cap region 10b of the gate pattern 10 may be a trapezoid, in which a short side of the trapezoid meets the body region 10 a. FIG. 8 is a schematic plan view of a gate pattern of a reticle according to an embodiment of the invention. As shown in fig. 8, the end surface of the end cap region 10b far from the body region 10a may be connected with the end surface arc thereof near the body region 10 a. When the top view of the cap region 10b is trapezoidal or the end surface of the cap region 10b far from the body region 10a is connected to the end surface arc near the body region 10a, the corner angle of the end portion of the gate obtained is more likely to approach 90 degrees.
The correction method of the mask of the embodiment comprises the steps of providing a mask, wherein a plurality of gate patterns are formed in the mask, the gate patterns comprise a first gate pattern 11 and a second gate pattern 12, the design space of the first gate pattern 11 is smaller than the set value, the first gate pattern 11 and the second gate pattern 12 are opposite, when the mask is subjected to pattern correction, the partial boundary of the first gate pattern 11 close to the second gate pattern 12 is moved outwards in the direction far away from the second gate pattern, and therefore the shapes of gates corresponding to the first gate pattern 11 and the second gate pattern 12, the design space of which is smaller than the set value, are closer to the design shape and are not easy to contact with each other, the problem of short circuit between the gates can be improved, and the improvement of the electrical performance of a semiconductor device is facilitated.
Furthermore, the gate pattern 10 includes a body region 10a corresponding to the active region 14 and an end cap region 10b located at an end of the body region 10a, and when the mask is subjected to pattern correction, the end face width of the end cap region 10b far away from the body region 10a is greater than the end face width of the body region 10a, so that when the gate is manufactured by using the mask, a corner angle of an end of the formed gate may be close to 90 degrees, that is, the end shape of the gate may be closer to a designed rectangular shape, which is beneficial to improving the problem that the length of the end of the gate extending from the active region is shortened and the problem that the turn-on voltage of the gate deviates from a predetermined value, and is beneficial to improving the electrical performance of a semiconductor device.
The embodiment also provides a mask, wherein a plurality of gate patterns 10 are formed in the mask, and the gate patterns 10 are patterns corrected by the correction method of the mask.
It should be noted that, the present specification is described in a progressive manner, and the reticles described later are mainly described as different from the reticle correction method described earlier, and the same and similar places among the parts may be referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (9)
1. A method for correcting a mask, comprising:
providing a mask, wherein a plurality of gate patterns are formed in the mask, the plurality of gate patterns comprise a first gate pattern and a second gate pattern, the design interval of the first gate pattern and the design interval of the second gate pattern are smaller than a set value, the first gate pattern and the second gate pattern are opposite in position, and when the mask is subjected to pattern correction, the middle part of the boundary, close to the second gate pattern, of the first gate pattern is moved outwards in the direction away from the second gate pattern.
2. The correction method for the reticle according to claim 1, wherein the first gate pattern is U-shaped, the second gate pattern is I-shaped, and one end of the second gate pattern is located in an opening of the first gate pattern; when the mask is subjected to pattern correction, the middle part of the boundary of the first grid pattern and the second grid pattern, which is opposite to the long edge, is moved outwards in the direction away from the second grid pattern.
3. The reticle correction method according to claim 1, wherein the first gate pattern and the second gate pattern are both elongated in the same direction, and when the reticle is subjected to the pattern correction, a middle portion of the first gate pattern near a long side of the second gate pattern is moved outward in a direction away from the second gate pattern.
4. The correction method for the mask according to claim 1, wherein the gate pattern includes a body region corresponding to the position of the active region and an end cap region at the end of the body region, the end cap region corresponding to the position of the isolation region at the side of the active region; when the pattern of the mask is corrected, the end face width of the end cover area far away from the main body area is larger than the end face width of the main body area.
5. The reticle correction method according to claim 4, wherein the end cap region has a trapezoidal shape in plan view, or wherein an end face of the end cap region remote from the body region is connected to an end face thereof close to the body region by an arc.
6. The reticle correction method according to claim 4, wherein a length of the body region is equal to a width of the active region and a length of the cap region is 10nm to 24nm in an elongation direction of the gate pattern.
7. The reticle correction method according to claim 1, wherein the set value is 45nm or less.
8. The method for correcting the reticle according to claim 1, wherein when the reticle is subjected to the pattern correction, a moving amount by which a boundary of a portion of the first gate pattern which is close to the second gate pattern is moved outward in a direction away from the second gate pattern is 5nm to 10 nm.
9. A mask blank, wherein a plurality of gate patterns are formed in the mask blank, and the gate patterns are patterns corrected by the correction method for the mask blank according to any one of claims 1 to 8.
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| CN202210279764.3A CN114371596A (en) | 2022-03-22 | 2022-03-22 | Mask and correction method thereof |
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Citations (11)
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