CN109728069B

CN109728069B - High voltage metal oxide semiconductor element and manufacturing method thereof

Info

Publication number: CN109728069B
Application number: CN201711020470.4A
Authority: CN
Inventors: 黄宗义; 陈巨峰; 叶昱廷
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2017-10-27
Filing date: 2017-10-27
Publication date: 2022-03-01
Anticipated expiration: 2037-10-27
Also published as: CN109728069A

Abstract

A high voltage metal oxide semiconductor element and a manufacturing method thereof are provided, the high voltage metal oxide semiconductor element comprises: well region, body region, grid, source, a plurality of body connection regions and drain. A plurality of body contact regions are formed in the body region, wherein each body contact region is located in the longitudinal direction, below and in contact with the top surface, and laterally adjacent or not to the gate. The plurality of body connection regions are arranged in parallel in the width direction, and two adjacent body connection regions are not adjacent to each other in the width direction. The gate has a polysilicon layer as one and only electrical contact to the gate, and all portions of the polysilicon layer have the first conductivity type.

Description

High voltage metal oxide semiconductor element and manufacturing method thereof

Technical Field

The present invention relates to a Metal Oxide Semiconductor (MOS) device, and more particularly, to a MOS device having a plurality of body contact regions. The invention also relates to a manufacturing method of the high-voltage metal oxide semiconductor element.

Background

Fig. 1A and 1B respectively show a top view and a corresponding cross-sectional view of a high voltage MOS device (an N-type high voltage MOS device 1 and a high voltage MOS device 1') of the prior art. As shown in fig. 1A and 1B, the high voltage MOS device 1 and the high voltage MOS device 1 'are arranged in a mirror image with each other and formed on a semiconductor substrate 11, wherein the semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ opposite to each other in a longitudinal direction. Wherein, the high voltage MOS device 1 and the high voltage MOS device 1' respectively include: an N-well region 12, a gate 13, an N-source 14, a P-body region 16, an N-drain 17, and a P-body connecting region 18. The N-type source 14 is formed in the P-type body region 16, and the P-type body region 16 has a body connecting region 18 for electrical contact to the P-type body region 16. Generally, as shown, the N-type source 14 and the P-type body connecting region 18 are arranged in parallel in the lateral direction, wherein the N-type source 14 is laterally adjacent to the gate 13, and the P-type body connecting region 18 is not adjacent to the gate 13. The high-voltage MOS device 1 and the high-voltage MOS device 1' are arranged in a mirror manner in the transverse direction to share the body connection region 18, so that the use space of the whole circuit can be reduced, and the size of the whole circuit can be reduced. The unit pitch d1 is the length of the high-voltage MOS device 1 in the lateral direction, and the size of the high-voltage MOS devices 1 arranged in a mirror manner is calculated by the unit pitch d 1.

Fig. 2A and 2B respectively show a top view and a corresponding cross-sectional view of another prior art high voltage MOS device (i.e., an N-type high voltage MOS device 2 and a high voltage MOS device 2'). As shown in fig. 2A and 2B, the high voltage MOS device 2 and the high voltage MOS device 2 'are arranged in a mirror image with each other and formed on the semiconductor substrate 11, wherein the semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ opposite to each other in the longitudinal direction. Wherein, the high voltage MOS device 2 and the high voltage MOS device 2' respectively include: n-well region 12, gate 23, N-source 24, P-body 16, N-drain 17, and P-body connecting region 28. Wherein the N-type source 24 is formed in the P-type body region 16 and has a body tie region 28 in the P-type body region 16 for electrical contact to the P-type body region 16.

The high-voltage MOS device 2 and the high-voltage MOS device 2 'are different from the high-voltage MOS device 1 and the high-voltage MOS device 1' shown in fig. 1A and 1B in that: as shown in fig. 2A, the N-type sources 24 and the P-type body connecting regions 28 are arranged in parallel in the width direction; the gate 23 includes a plurality of N-type gate regions 23' and P-type gate regions 23 "; and the plurality of N-type gate regions 23' and the plurality of P-type gate regions 23 ″ are arranged in parallel and staggered in the width direction, and are laterally adjacent to the corresponding plurality of N-type sources 24 and the corresponding plurality of P-type body connecting regions 28, respectively. Compared with the high-voltage MOS device 1 and the high-voltage MOS device 1 'which are arranged in a mirror manner in the transverse direction and share the body connection region 18, the high-voltage MOS device 2 and the high-voltage MOS device 2' which are arranged in a mirror manner in the transverse direction and share the source 24 and the body connection region 18, the usage space of the whole circuit can be further reduced, and the size of the whole circuit can be further reduced.

Comparing the unit spacing d1 of the high-voltage MOS element 1 with the unit spacing d2 of the high-voltage MOS element 2, wherein the unit spacing d1 of the high-voltage MOS element 1 includes the spacing of the source 14 completely in the lateral direction and half of the body connection region 18 in the lateral direction, i.e., the spacing d 1'; the unit spacing d2 of the high-voltage MOS device 2 includes only half the spacing of the source in the lateral direction (and overlaps the body connection region 18 in the lateral direction), i.e., the spacing d 2'; in comparison, the distance d2 'is about one third of the distance d 1', so that the high voltage MOS device 2 and the high voltage MOS device 2 'shown in fig. 2A and 2B are significantly smaller in the lateral direction than the high voltage MOS device 1 and the high voltage MOS device 1' shown in fig. 1A and 1B, which further reduces the device size.

However, the prior art shown in fig. 2A and 2B has a disadvantage in that the region of the ion implantation step defined when the body connection region 28 is formed often includes the P-type gate region 23 ", because the prior art always regards the gate 23 as a self-aligned mask, which can be self-aligned to the area of the body connection region 28. However, in this way, the P-type impurity is implanted into the gate 23 to form the P-type gate region 23 ″. When the high-voltage MOS device is turned on, the channel region under the P-type gate region 23 ″ is not turned on (as shown in fig. 2E) when the N-type gate region 23 'is turned on (as shown in fig. 2D), which significantly increases the on-resistance between the high-voltage MOS device 2 and the high-voltage MOS device 2'.

In view of the above, the present invention provides a high voltage MOS device and a method for manufacturing the same, which can improve transient response and increase the application range of the high voltage MOS device.

Disclosure of Invention

The present invention is directed to overcome the disadvantages and drawbacks of the prior art, and provides a high voltage MOS device and a method for manufacturing the same, which can improve the transient response and increase the application range of the high voltage MOS device.

In order to achieve the above-mentioned objects, in one aspect, the present invention provides a high voltage Metal Oxide Semiconductor (MOS) device formed on a Semiconductor substrate, wherein the Semiconductor substrate has an upper surface and a lower surface opposite to each other in a longitudinal direction, comprising: a well region of a first conductivity type formed in the semiconductor substrate and located below and connected to the upper surface in the longitudinal direction; a body region of a second conductivity type formed in the well region and located below and connected to the upper surface in the longitudinal direction; a gate formed on the upper surface, wherein a portion of the gate is stacked and connected over a portion of the body region in the longitudinal direction; a source of the first conductivity type formed in the body region and in the longitudinal direction, the source being located below and contacting the upper surface and laterally adjacent to a first side of the gate; a plurality of body contact regions of the second conductivity type formed in the body region, wherein each body contact region is located below and in contact with the upper surface in the longitudinal direction and is adjacent to or not adjacent to the first side of the gate in the lateral direction, wherein the body contact regions are arranged substantially parallel to a width direction and each adjacent two of the body contact regions are not adjacent to each other in the width direction; and a drain of the first conductivity type formed in the well region, located below and in contact with the upper surface in the longitudinal direction, located outside a second side of the gate in the lateral direction, and separated from the source by the body region and the well region; wherein the gate has a polysilicon layer as one and only electrical contact to the gate, and all portions of the polysilicon layer have the first conductivity type.

In a preferred embodiment, the high voltage MOS device further includes a field oxide region formed on the upper surface and stacked and connected directly over a portion of the well region, wherein a portion of the gate in the lateral direction, which is close to the drain side, includes the second side of the gate, and is stacked and connected directly over at least a portion of the field oxide region.

In a preferred embodiment, the plurality of body connection regions respectively adjoin the first side of the gate in the lateral direction and separate the source into a plurality of source sub-regions, wherein the plurality of source sub-regions adjoin the first side of the gate in the lateral direction, wherein the plurality of source sub-regions are arranged substantially parallel to the width direction and each two adjacent source sub-regions do not adjoin each other in the width direction.

In a preferred embodiment, the body connecting regions are not adjacent to the first side of the gate in the lateral direction, and the body connecting regions are spaced apart from the first side of the gate by at least a predetermined distance in the lateral direction.

In a preferred embodiment, the predetermined pitch is not less than 0.05 μm.

From another perspective, the present invention also provides a method for manufacturing a Metal Oxide Semiconductor (MOS) device, including: providing a semiconductor substrate, which is provided with an upper surface and a lower surface opposite to each other in a longitudinal direction; forming a well region in the semiconductor substrate, the well region having a first conductivity type and being located below and connected to the upper surface in the longitudinal direction; forming a body region of a second conductivity type in the longitudinal direction under and connected to the upper surface in the first conductivity type well region; forming a gate on the upper surface, wherein a portion of the gate is stacked and connected over a portion of the body region in the longitudinal direction; forming a source electrode in the body region, the source electrode having the first conductivity type and being located below and contacting the upper surface in the longitudinal direction and being laterally adjacent to a first side of the gate electrode; forming a plurality of body connection regions in the body region, the body connection regions having the second conductivity type, wherein each of the body connection regions is located below and in contact with the upper surface in the longitudinal direction and adjacent to or not adjacent to the first side of the gate in the lateral direction, wherein the body connection regions are arranged substantially parallel to a width direction and each adjacent two of the body connection regions are not adjacent to each other in the width direction; and forming a drain of the first conductivity type in the well region, the drain being located below and contacting the upper surface in the longitudinal direction and outside a second side of the gate in the lateral direction, the drain being separated from the source by the body region and the well region; wherein the gate has a polysilicon layer as one and only electrical contact to the gate, and all portions of the polysilicon layer have the first conductivity type.

In a preferred embodiment, the method for manufacturing a MOS device further comprises the steps of: forming a field oxide region on the upper surface, and stacking and connecting the field oxide region right above the well region, wherein a portion of the gate electrode close to the drain electrode side in the transverse direction includes the second side of the gate electrode, and the field oxide region is stacked and connected right above at least a portion of the field oxide region.

In a preferred embodiment, the predetermined pitch is not less than 0.05 μm.

In a preferred embodiment, the step of forming the gate electrode comprises: implanting impurities of a first conductivity type into the polysilicon layer in the form of accelerated ion beams in the same first ion implantation process step as that for forming the source and/or the drain; and forming a photoresist layer to shield the gate, so as to prevent the second conductive type impurity from being implanted into the polysilicon layer in the form of accelerated ion beam in a second ion implantation process step for forming the plurality of body connection regions.

In a preferred embodiment, the step of forming the gate electrode comprises: implanting impurities of a first conductivity type into the polysilicon layer in the form of accelerated ion beams in the same first ion implantation process step as that for forming the source and/or the drain; and implanting impurities of the first conductivity type into the polysilicon layer in the form of accelerated ion beams in a second ion implantation process step to offset-invert the regions of the second conductivity type in the polysilicon layer to the first conductivity type, so that all portions of the polysilicon layer have the first conductivity type.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

FIGS. 1A and 1B illustrate a top view and a corresponding cross-sectional view, respectively, of a prior art high voltage Metal Oxide Semiconductor (MOS) device;

FIGS. 2A-2E illustrate a top view and a cross-sectional view of another prior art;

FIGS. 3A-3C illustrate a first embodiment of the present invention;

FIGS. 4A-4C illustrate a second embodiment of the present invention;

FIGS. 5A-5C illustrate a third embodiment of the present invention;

FIGS. 6A-6C illustrate a fourth embodiment of the present invention;

FIGS. 7A-7N illustrate a fifth embodiment of the present invention;

FIGS. 8A-8Q illustrate a sixth embodiment of the present invention;

FIGS. 9A-9F illustrate a seventh embodiment of the present invention;

FIGS. 10A-10N illustrate an eighth embodiment of the present invention;

11A-11Q illustrate a ninth embodiment of the invention;

fig. 12A-12F show a tenth embodiment of the invention.

Description of the symbols in the drawings

1, 1 ', 2, 2', 3, 4, 5, 6 high voltage MOS element

11 semiconductor substrate

11' upper surface

11' lower surface

12 well region

13, 23, 33, 53, 83 grid

14, 24, 34, 44 source

16 body region

17 drain electrode

18, 28, 38, 48 body attachment region

20, 20' field oxide region

16 ', 17 ', 34 ', 38 ', 44 ', 48 ', 83 ' photoresist layer

23' P type grid region

341 source sub-region

531, 831 gate compensation region

A-A' cutting line

B-B' cutting line

d1, d2 unit spacing

d1 ', d 2' spacing

dp preset pitch

S1 first side

S2 second side

Detailed Description

The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.

Referring to fig. 3A, 3B and 3C, a first embodiment of the present invention is shown, in which a top view, a first cross-sectional view (corresponding to the cross-sectional line a-a ') of an embodiment of a high voltage Metal Oxide Semiconductor (MOS) device (high voltage MOS device 3) and a second cross-sectional view (corresponding to the cross-sectional line B-B') of the top view are shown. As shown in fig. 3A, 3B and 3C, the high voltage MOS device 3 is formed on a semiconductor substrate 11, which has an upper surface 11' and a lower surface 11 ″ opposite to each other in a longitudinal direction (as shown by the dotted arrow in fig. 3B or 3C, the same applies below); the high voltage MOS device 3 includes: well region 12, body region 16, drain 17, gate 33, source 34, and body contact region 38.

Referring to fig. 3A, 3B and 3C, the well 12 of the first conductivity type is formed in the semiconductor substrate 11 and is located below the upper surface 11 'and connected to the upper surface 11' in the vertical direction. The body region 16 of the second conductivity type is formed in the well region 12 and is located below the upper surface 11 'and connected to the upper surface 11' in the longitudinal direction. The gate 13 is formed on the upper surface 11 ', and a part of the gate 33 is stacked and connected right above the body region 16 in the longitudinal direction, it should be noted that, where the gate 33 overlaps the body region 16 of the second conductivity type in the vertical projection in the longitudinal direction, it is a channel region of the high voltage MOS device 3 (as indicated by a dashed box in fig. 3B), and the gate 33 includes a polysilicon layer having conductivity, a dielectric layer connected to the upper surface 11', and a spacer layer having an electrical insulating property, which are well known to those skilled in the art and will not be described herein again.

With continued reference to fig. 3A, 3B and 3C, the source 34 of the first conductivity type is formed in the body region 16, and the source 34 is located below the upper surface 11 'and contacts the upper surface 11' in the vertical direction and is adjacent to the first side S1 of the gate 33 in the horizontal direction (as indicated by the solid arrow in fig. 3B or 3C, the same applies below). A plurality of body connection regions 38 of the second conductivity type formed in the body region 16, each body connection region 38 being located below the upper surface 11 'and contacting the upper surface 11' in the longitudinal direction, and in the present embodiment, each body connection region 38 being laterally adjacent to the first side S1 of the gate 13, the plurality of body connection regions 38 being arranged substantially parallel in a width direction (as shown by the arrow "width direction" in fig. 3A, the same applies hereinafter) and each two adjacent body connection regions 38 being at least partially not adjacent to each other in the width direction; as shown in FIG. 3A, in a preferred embodiment, each adjacent two of the body connecting regions 38 are not contiguous in the width direction. In the present embodiment, the body connection regions 38 laterally adjoin the first side S1 of the gate 33 and separate the source 34 into a plurality of source sub-regions 341, wherein the source sub-regions 341 laterally adjoin the first side S1 of the gate 13, and wherein the source sub-regions 341 are arranged substantially parallel to the width direction and each adjacent two of the source sub-regions 341 are not contiguous to the width direction. The drain 17 of the first conductivity type is formed in the well 12, and is located below the upper surface 11 'and in contact with the upper surface 11' in the longitudinal direction, and is located outside the second side S2 of the gate 13 in the lateral direction, and is separated from the source 34 by the body region 16 and the well 12.

The above-mentioned "first conductivity type" and "second conductivity type" refer to that in the high voltage MOS device, impurities with different conductivity types are doped in the semiconductor composition region (for example, but not limited to, the well region, the body connection region, the source, the drain, the gate, etc.) so that the semiconductor composition region becomes the first or the second conductivity type (for example, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa).

In addition, the high voltage MOS device means that the voltage applied to the drain is higher than a specific voltage, for example, 5V; in the present embodiment, the drain 17 and the channel region of the high voltage MOS device 3 are separated by the well region 12, and the lateral distance (drift region length) between the body region 16 and the drain 17 is adjusted according to the operating voltage applied during normal operation, so that the high voltage MOS device can be operated at the higher specific voltage. The channel region is a region that is controlled by the gate to be conductive or non-conductive, and the length of the drift region is used to adjust the operating voltage, which is well known to those skilled in the art and is not described herein.

It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 3A, 3B and 3C as an example, when the body connecting regions 38 are formed, the ion implantation step region defined therein does not include any portion of the gate 33, compared to the prior art, in which the gate 23 is regarded as a self-aligned mask, so that the P-type gate region 23 ″ is formed by implanting the P-type impurity into the gate 23, the polysilicon layer of the gate 33 of the present embodiment serves as one and only electrical contact of the gate 33, and all portions of the polysilicon layer according to the present invention have the first conductivity type and do not include any portion of the second conductivity type. When the high voltage MOS device is turned on, the on resistance of the high voltage MOS device 3 according to the present invention is significantly lower than that of the high voltage MOS device 2 of the prior art. In addition, the field oxide region 20' is not limited to a local oxidation of silicon (LOCOS) structure as shown in the figure, but also a Shallow Trench Isolation (STI) structure.

Referring to fig. 4A to 4C, a second embodiment of the invention is shown, in which a top view (fig. 4A) and a first cross-sectional view (fig. 4B, corresponding to the cross-section a-a 'of the top view fig. 4A) and a second cross-sectional view (fig. 4C, corresponding to the cross-section B-B' of the top view fig. 4A) of an embodiment of a high voltage MOS device (high voltage MOS device 4) according to the invention are respectively shown. High-voltage MOS device 4 is similar to high-voltage MOS device 3 described above, in this embodiment, the plurality of body connection regions 48 of high-voltage MOS device 4 are laterally not adjacent to first side S1 of gate 33, and body connection regions 48 are laterally spaced apart from first side S1 of gate 33 by at least a predetermined pitch dp. In the present embodiment, the source 44 is not divided into a plurality of source sub-regions by the body connecting regions 48, but is a fully connected region.

It should be noted that, in the second embodiment, the predetermined pitch dp is not less than 0.05 μm, which is considered to be a margin of error of the design rule (design rule), and in a preferred embodiment, the predetermined pitch dp is 0.1 μm.

Fig. 5A-5C illustrate a third embodiment of the present invention, which shows a top view (fig. 5A) and a first cross-sectional view (fig. 5B, corresponding to the cross-sectional line a-a 'of the top view fig. 5A) and a second cross-sectional view (fig. 5C, corresponding to the cross-sectional line B-B' of the top view fig. 5A), respectively, of an embodiment of a high voltage MOS device (high voltage MOS device 5) according to the present invention. High-voltage MOS device 5 is similar to high-voltage MOS device 3, but in the present embodiment, high-voltage MOS device 5 further includes a field oxide region 20 ' formed on upper surface 11 ' and stacked and connected directly over a portion of well region 12, wherein a portion of gate 53 laterally adjacent to the drain 17 side includes a second side S2 of gate 53, and stacked and connected directly over at least a portion of field oxide region 20 '.

Referring to fig. 6A to 6C, a fourth embodiment of the invention is shown, in which a top view (fig. 6A) and a first cross-sectional view (fig. 6B, corresponding to the cross-section a-a 'of the top view fig. 6A) and a second cross-sectional view (fig. 6C, corresponding to the cross-section B-B' of the top view fig. 6A) of an embodiment of a high voltage MOS device (high voltage MOS device 6) according to the invention are respectively shown. The high voltage MOS device 6 is similar to the high voltage MOS device 5, in the embodiment, the body connection regions 48 of the high voltage MOS device 6 are laterally not adjacent to the first side S1 of the gate 53, and the body connection regions 48 are laterally spaced apart from the first side S1 of the gate 53 by at least a predetermined pitch dp. In the present embodiment, the source 44 is not divided into a plurality of source sub-regions by the body connecting regions 48, but is a fully connected region.

Fig. 7A-7N show a fifth embodiment of the present invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Taking the high voltage MOS device 3 of the first embodiment as an example, first, as shown in the top view schematic diagram of fig. 7A and the cross-sectional schematic diagram (corresponding to the cross-sectional line a-a' of fig. 7A) of fig. 7B, a semiconductor substrate 11 is provided, wherein the semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, but may be other semiconductor substrates. The semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ facing each other in a longitudinal direction (e.g., the direction of the dotted arrow in fig. 7B). Next, as shown in fig. 7A and 7B, a first conductive type well region 12 is formed in the semiconductor substrate 11, and is located below the upper surface 11 'and connected to the upper surface 11' in the longitudinal direction; the method for forming the first conductive type well 12 is, for example, but not limited to, photolithography, ion implantation, and thermal process, which are well known in the art and will not be described herein.

Next, as shown in the top view of fig. 7C and the cross-sectional view of fig. 7D (corresponding to the cross-sectional line a-a' of fig. 7C), field oxide regions 20 are formed to define the active regions of the high voltage MOS devices 3. Next, as shown in the top view diagram of fig. 7E and the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 7E) of fig. 7F, a photoresist layer 16 ' is used as a mask to define an ion implantation region of the second conductive type body region 16, and second conductive type impurities are implanted into the defined region in the form of accelerated ions by an ion implantation process step to form the second conductive type body region 16 in the first conductive type well region 12, and is located below and connected to the upper surface 11 ' in the longitudinal direction.

Next, as shown in the top view of fig. 7G and the cross-sectional view of fig. 7H (corresponding to the cross-sectional line a-a 'of fig. 7G), as shown, an undoped gate 33 is formed on the upper surface 11', and a portion of the gate 33 is stacked and connected directly above a portion of the body region 16 of the second conductivity type in the vertical direction.

Next, as shown in the schematic top view of FIG. 7I, the schematic cross-sectional view of FIG. 7J (corresponding to the cross-sectional line A-A 'of FIG. 7I in the top view) and the schematic cross-sectional view of FIG. 7K (corresponding to the cross-sectional line B-B' of FIG. 7I in the top view), the field oxide region 20, the photoresist layer 34 'and the photoresist layer 17' are used as a mask to define the ion implantation regions of the gate 33, the plurality of first conductive type source sub-regions 341 and the drain 17, and the first conductive type impurities are implanted, a polysilicon layer of the first conductivity type implanted into the defined region to form the gate 33, a source 34 of the first conductivity type (including a plurality of source sub-regions 341 of the first conductivity type) in the body region 16 of the second conductivity type, and a drain 17 in the well region 12, respectively, and in the vertical direction, the source electrode 34 and the drain electrode 17 of the first conductive type are both located below the upper surface 11 'and contact with the upper surface 11'. In the same ion implantation step as that for forming the source 34 and the drain 17, as shown by the downward dotted arrows in fig. 7J, the first conductivity type impurity is implanted into the polysilicon layer in the form of an accelerated ion beam. The first conductive type drain 17 is located below the upper surface 11 'in the vertical direction and in contact with the upper surface 11', and is separated from the first conductive type source region 34 in the horizontal direction by the second conductive type body region 16 and the first conductive type well region 12.

Next, as shown in the top view diagram of fig. 7L, the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 7L in the top view), shown in fig. 7M, and the cross-sectional diagram (corresponding to the cross-sectional line B-B ' of fig. 7L in the top view) shown in fig. 7N, the photoresist layer 38 ' is used as a mask to define a plurality of ion implantation regions of the second conductive type body connecting regions 38, and second conductive type impurities are implanted into the defined regions in the form of accelerated ions to form a plurality of second conductive type body connecting regions 38 in the second conductive type body regions 16, each body connecting region 38 is located below the upper surface 11 ' in the longitudinal direction and is in contact with the upper surface 11 ', and in the present embodiment, each body connecting region 38 is adjacent to the first side S1 of the gate 33 in the transverse direction, the plurality of body connecting regions 38 are arranged substantially in parallel in the width direction, and each adjacent two body connecting regions 38 are arranged at least partially in the width direction The partitions are not contiguous. In the present embodiment, each two adjacent body connecting regions 38 are not adjacent to each other in the width direction. In the present embodiment, the body connection regions 38 laterally adjoin the first side S1 of the gate 33 and separate the source 34 into a plurality of source sub-regions 341, wherein the source sub-regions 341 laterally adjoin the first side S1 of the gate 33, and the source sub-regions 341 are arranged substantially parallel to the width direction and each adjacent two of the source sub-regions 341 are not contiguous to the width direction. In this embodiment, a photoresist layer 38' is formed to shield the gate electrode 33, so as to prevent impurities of the second conductivity type from being implanted into the polysilicon layer of the gate electrode 33 in the form of an accelerated ion beam in the ion implantation process step for forming the plurality of body connection regions 38.

It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 7A-7N as an example, when the body connecting regions 38 are formed, the defined ion implantation step region does not include any portion of the gate 33, i.e., when the body connecting regions 38 are formed, the gate 33 is completely shielded by the photoresist layer 38' to prevent the second conductivity type ion from being implanted into the gate 33. In contrast to the prior art shown in fig. 2A-2E, which forms P-type gate region 23 "by treating gate 23 as a self-aligned mask or by implanting P-type impurities into gate 23 for a less precise lithographic step selected for the process accuracy of the body contact regions 28, the polysilicon layer of gate 33 of this embodiment serves as one and the only electrical contact for gate 33, and all portions of the polysilicon layer according to the present invention have the first conductivity type and do not include any portion of the second conductivity type. When the high voltage MOS device is turned on, the on resistance of the high voltage MOS device 3 according to the present invention is significantly lower than that of the high voltage MOS device 2 of the prior art.

Fig. 8A-8Q show a sixth embodiment of the present invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Taking the high voltage MOS device 3 of the first embodiment as an example, first, as shown in the top view schematic diagram of fig. 8A and the cross-sectional schematic diagram (corresponding to the cross-sectional line a-a' of fig. 8A) of fig. 8B, a semiconductor substrate 11 is provided, wherein the semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, but may be other semiconductor substrates. The semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ facing each other in a longitudinal direction (e.g., the direction of the dotted arrow in fig. 8B). Next, as shown in fig. 8A and 8B, a first conductive type well region 12 is formed in the semiconductor substrate 11, and is located below the upper surface 11 'and connected to the upper surface 11' in the longitudinal direction; the method for forming the first conductive type well 12 is, for example, but not limited to, photolithography, ion implantation, and thermal process, which are well known in the art and will not be described herein.

Next, as shown in the top view of fig. 8C and the cross-sectional view (corresponding to the cross-sectional line a-a' of fig. 8C) of fig. 8D, field oxide regions 20 are formed to define the active regions of the high voltage MOS devices 3. Next, as shown in the top view diagram of fig. 8E and the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 8E) of fig. 8F, a photoresist layer 16 ' is used as a mask to define an ion implantation region of the second conductive type body region 16, and second conductive type impurities are implanted into the defined region in the form of accelerated ions by an ion implantation process step to form the second conductive type body region 16 in the first conductive type well region 12, and is located below and connected to the upper surface 11 ' in the longitudinal direction.

Next, as shown in the top view diagram of fig. 8G and the cross-sectional diagram (corresponding to the cross-sectional line a-a 'of fig. 8G) of fig. 8H, as shown, a gate 83 not yet doped is formed on the upper surface 11', and in the vertical direction, a portion of the gate 83 is stacked and connected to a portion of the body region 16 of the second conductivity type.

Next, as shown in the top view of fig. 8I, the cross-sectional view of fig. 8J (corresponding to the cross-sectional line a-a 'of the top view of fig. 8I) and the cross-sectional view of fig. 8K (corresponding to the cross-sectional line B-B' of the top view of fig. 8I), as shown, the field oxide region 20, the photoresist layer 34 'and the photoresist layer 17' are used as a mask to define the ion implantation region of the first conductive type polysilicon layer among the plurality of first conductive type source sub-regions 341, the drain 17 and the gate 83, and the first conductive type impurity is implanted in the form of accelerated ions into the defined region to form the first conductive type polysilicon layer of the gate 83, the first conductive type source 34 (including the plurality of first conductive type source sub-regions 341) in the second conductive type body region 16 and the drain 17 in the well region 12, respectively, and in the vertical direction, the source 34 and the drain 17 of the first conductivity type are both located under the upper surface 11 'and contact the upper surface 11'. Wherein impurities of the first conductivity type are implanted into the polysilicon layer in the form of accelerated ion beams in the same ion implantation process step as the source 34 and drain 17 are formed, as indicated by the downward dashed arrows in fig. 7J. The first-conductivity-type drain 17 is located below the upper surface 11 'in the longitudinal direction and in contact with the upper surface 11', and is separated from the first-conductivity-type source region 34 in the lateral direction by the second-conductivity-type body region 16 and the first-conductivity-type well region 12.

Next, as shown in the top view diagram of fig. 8L, the cross-sectional diagram of fig. 8M (corresponding to the cross-sectional line a-a ' of fig. 8L in the top view), and the cross-sectional diagram of fig. 8N (corresponding to the cross-sectional line B-B ' of fig. 8L in the top view), using the photoresist layer 38 ' as a mask to define a plurality of second-conductivity-type body connection regions 38 and an ion implantation region of the second-conductivity-type polysilicon layer in the gate 83, and implanting second-conductivity-type impurities in the form of accelerated ions into the defined region in an ion implantation process step to form the second-conductivity-type polysilicon layer in the gate 83 and a plurality of second-conductivity-type body connection regions 38 in the second-conductivity-type body region 16, each body connection region 38 is located below the upper surface 11 ' in the longitudinal direction and in contact with the upper surface 11 ', and in this embodiment, each body connection region 38 is laterally adjacent to the first side S1 of the gate 83, the plurality of body connecting regions 38 are arranged substantially in parallel in the width direction, and each adjacent two body connecting regions 38 are at least partially not adjacent to each other in the width direction. In the present embodiment, each two adjacent body connecting regions 38 are not adjacent to each other in the width direction. In the present embodiment, the body connection regions 38 laterally adjoin the first side S1 of the gate 83 and separate the source 34 into a plurality of source sub-regions 341, wherein the source sub-regions 341 laterally adjoin the first side S1 of the gate 83, and wherein the source sub-regions 341 are arranged substantially parallel to the width direction and each adjacent two of the source sub-regions 341 are not contiguous to the width direction. In the present embodiment, when the second conductive type impurity is implanted into the defined region in the form of accelerated ions (as indicated by the downward dotted arrows in the figure) to form a plurality of second conductive type body connecting regions 38, the second conductive type impurity is also implanted into a portion of the gate 83 in the form of accelerated ions, as illustrated in fig. 8M and 8N.

Next, as shown in the top view diagram of fig. 8O, the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of the top view fig. 8O) of fig. 8P and the cross-sectional diagram (corresponding to the cross-sectional line B-B ' of the top view fig. 8O) of fig. 8Q, the photoresist layer 83 ' is used as a mask to define the ion implantation region of the gate compensation region 831, and the first conductive type impurity is implanted in the form of accelerated ions into the region defined in the polysilicon layer to offset the region of the polysilicon layer of the gate 83 having the second conductive type into the first conductive type, so that all parts of the polysilicon layer have the first conductive type.

Fig. 9A-9F show a seventh embodiment of the invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Take the high voltage MOS device 4 as an example in the second embodiment of the present invention shown in fig. 4A-4C. The foregoing steps of the manufacturing method are the same as those of the fifth embodiment of the present invention shown in FIGS. 7A to 7H, please refer to FIGS. 7A to 7H.

Next, as shown in the schematic top view of fig. 9A, the schematic cross-sectional view of fig. 9B (corresponding to the cross-sectional line a-a 'of fig. 9A in the top view) and the schematic cross-sectional view of fig. 9C (corresponding to the cross-sectional line B-B' of fig. 9A in the top view), the field oxide region 20, the photoresist layer 44 'and the photoresist layer 17' are used as a mask to define the ion implantation regions of the gate 33, the first conductive type source 44 and the drain 17, and the first conductive type impurity is implanted by an ion implantation process, implanting a polysilicon layer of the first conductivity type in the defined region to form the gate 33, a source 44 of the first conductivity type in the body region 16 of the second conductivity type, and a drain 17 in the well region 12, respectively, in the form of accelerated ions, and in the vertical direction, the first conductive type source 44 and the drain 17 are both located under the upper surface 11 'and contact with the upper surface 11'. In the same ion implantation step as that for forming the source 44 and the drain 17, as shown by the downward dashed arrows in fig. 9B and 9C, the first conductivity type impurity is implanted into the polysilicon layer in the form of an accelerated ion beam. The first-conductivity-type drain 17 is located below the upper surface 11 'in the longitudinal direction and in contact with the upper surface 11', and is separated from the first-conductivity-type source 44 in the lateral direction by the second-conductivity-type body region 16 and the first-conductivity-type well region 12.

Next, as shown in the schematic top view shown in fig. 9D, the schematic cross-sectional view shown in fig. 9E (corresponding to the cross-sectional line a-a ' of fig. 9D in the top view), and the schematic cross-sectional view shown in fig. 9F (corresponding to the cross-sectional line B-B ' of fig. 9D in the top view), with the photoresist layer 48 ' as a mask, to define a plurality of ion implantation regions of the second conductive type body connection regions 48, and with an ion implantation process step, implanting second conductive type impurities in the form of accelerated ions into the defined regions to form a plurality of second conductive type body connection regions 48 in the second conductive type body regions 16, each body connection region 48 being located below the upper surface 11 ' in the longitudinal direction and contacting the upper surface 11 ', and in the present embodiment, each body connection region 48 being laterally not adjacent to the first side S1 of the gate 33, the plurality of body connection regions 48 being arranged substantially parallel in the width direction, and each adjacent two body connection regions 48 being at least substantially parallel in the width direction The sections are not contiguous. In the present embodiment, each two adjacent body connecting regions 48 are not adjacent to each other in the width direction. In the present embodiment, the plurality of body connection regions 48 are not adjacent to the first side S1 of the gate 33 in the lateral direction, and the source 44 is adjacent to the first side S1 of the gate 33 in the lateral direction, respectively. In the present embodiment, a photoresist layer 48' is formed to shield the gate electrode 33, so as to prevent impurities of the second conductivity type from being implanted into the polysilicon layer of the gate electrode 33 in the form of an accelerated ion beam in the ion implantation process step for forming the plurality of body connection regions 48.

It should be noted that the present embodiment is different from the fifth embodiment shown in fig. 7A to 7N in that: in the present embodiment, the plurality of body connection regions 48 of the high voltage MOS device 4 are laterally not adjacent to the first side S1 of the gate 33, and the body connection regions 48 are laterally spaced apart from the first side S1 of the gate 33 by at least a predetermined pitch dp. In the present embodiment, the source 44 is not divided into a plurality of source sub-regions by the body connecting regions 48, but is a fully connected region.

Fig. 10A to 10N show an eighth embodiment of the present invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Taking the high voltage MOS device 5 according to the third embodiment of the present invention shown in fig. 5A-5C as an example, first, as shown in the schematic plan view shown in fig. 10A and the schematic cross-sectional view shown in fig. 10B (corresponding to the cross-sectional line a-a' of fig. 10A), a semiconductor substrate 11 is provided, wherein the semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, but may be other semiconductor substrates. The semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ facing each other in a longitudinal direction (e.g., the direction of the dotted arrow in fig. 10B). Next, as shown in fig. 10A and 10B, a first conductive type well region 12 is formed in the semiconductor substrate 11, and is located below the upper surface 11 'and connected to the upper surface 11' in the longitudinal direction; the method for forming the first conductive type well 12 is, for example, but not limited to, photolithography, ion implantation, and thermal process, which are well known in the art and will not be described herein.

Next, as shown in the top view diagram of fig. 10C and the cross-sectional diagram (corresponding to the cross-sectional line a-a' of the top view diagram 10C) of fig. 10D, field oxide regions 20 are formed to define the active regions of the high voltage MOS devices 5; at the same time, a field oxide region 20 'is formed on the upper surface of the well region 11' and is stacked and connected directly above the well region 12. Next, as shown in the top view diagram of fig. 10E and the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 10E) of fig. 10F, a photoresist layer 16 ' is used as a mask to define an ion implantation region of the second conductive type body region 16, and second conductive type impurities are implanted into the defined region in the form of accelerated ions by an ion implantation process step to form the second conductive type body region 16 in the first conductive type well region 12, and is located below and connected to the upper surface 11 ' in the longitudinal direction.

Next, as shown in the top view of fig. 10G and the cross-sectional view of fig. 10H (corresponding to the cross-sectional line a-a 'of the top view of fig. 10G), as shown, a gate 53 not yet doped is formed on the upper surface 11', wherein the field oxide region 20 'is located laterally, a portion of the gate 53 near the drain 17 (see fig. 5A-5C), including the second side S2 of the gate 53, is stacked and connected directly above at least a portion of the field oxide region 20', and a portion of the gate 53 is stacked and connected directly above a portion of the body region 16 of the second conductivity type in the longitudinal direction.

Next, as shown in the schematic top view of fig. 10I, the schematic cross-sectional view of fig. 10J (corresponding to the cross-sectional line a-a 'of fig. 10I in the top view) and the schematic cross-sectional view of fig. 10K (corresponding to the cross-sectional line B-B' of fig. 10I in the top view), the field oxide region 20 and the photoresist layer 34' are used as a mask to define the ion implantation regions of the gate 53, the plurality of first conductive type source sub-regions 341 and the drain 17, and the ion implantation process step is used to implant the first conductive type impurities, a polysilicon layer of the first conductivity type implanted in the defined region to form the gate 53, a source 34 of the first conductivity type (including a plurality of source sub-regions 341 of the first conductivity type) in the body region 16 of the second conductivity type, and a drain 17 in the well region 12, respectively, and in the vertical direction, the source electrode 34 and the drain electrode 17 of the first conductive type are both located below the upper surface 11 'and contact with the upper surface 11'. In the same ion implantation step as that for forming the source 34 and the drain 17, as shown by the downward dotted arrows in fig. 10J and 10K, the first conductivity type impurity is implanted into the polysilicon layer in the form of an accelerated ion beam. The first conductive type drain 17 is located below the upper surface 11 'in the vertical direction and in contact with the upper surface 11', and is separated from the first conductive type source region 34 in the horizontal direction by the second conductive type body region 16 and the first conductive type well region 12.

Next, as shown in the top view diagram of fig. 10L, the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of the top view fig. 10L) of fig. 10M and the cross-sectional diagram (corresponding to the cross-sectional line B-B ' of the top view fig. 10L) of fig. 10N, the photoresist layer 38 ' is used as a mask to define a plurality of ion implantation regions of the second conductive type body connecting regions 38, and the second conductive type impurities are implanted into the defined regions in the form of accelerated ions to form a plurality of second conductive type body connecting regions 38 in the second conductive type body regions 16, each body connecting region 38 is located below the upper surface 11 ' in the longitudinal direction and contacts the upper surface 11 ', and in this embodiment, each body connecting region 38 is adjacent to the first side S1 of the gate 33 in the transverse direction, the plurality of body connecting regions 38 are arranged substantially parallel in the width direction, and each adjacent two body connecting regions 38 are arranged substantially parallel to each other in the width direction with at least a portion between the two adjacent body connecting regions 38 in the width direction The partitions are not contiguous. In the present embodiment, each two adjacent body connecting regions 38 are not adjacent to each other in the width direction. In the present embodiment, the body connection regions 38 laterally adjoin the first side S1 of the gate 33 and separate the source 34 into a plurality of source sub-regions 341, wherein the source sub-regions 341 laterally adjoin the first side S1 of the gate 33, and the source sub-regions 341 are arranged substantially parallel to the width direction and each adjacent two of the source sub-regions 341 are not contiguous to the width direction. In this embodiment, a photoresist layer 38' is formed to shield the gate electrode 33, so as to prevent impurities of the second conductivity type from being implanted into the polysilicon layer of the gate electrode 33 in the form of an accelerated ion beam in the ion implantation process step for forming the plurality of body connection regions 38.

It is noted that one of the technical features of the present invention over the prior art is that: in accordance with the present invention, taking the embodiment shown in fig. 10A-10N as an example, when the body connecting regions 38 are formed, the defined ion implantation step region does not include any portion of the gate 53, i.e., when the body connecting regions 38 are formed, the gate 53 is completely shielded by the photoresist layer 38' to prevent the second conductivity type ions from being implanted into the gate 53. In contrast to the prior art shown in fig. 2A-2E, which forms P-type gate region 23 "by treating gate 23 as a self-aligned mask or by implanting P-type impurities into gate 23 for a less precise lithographic step selected for the process accuracy of the body contact regions 28, the polysilicon layer of gate 53 of the present embodiment serves as one and the only electrical contact for gate 53, and all portions of the polysilicon layer according to the present invention have the first conductivity type and do not include any portion of the second conductivity type. When the high voltage MOS device is turned on, the on resistance of the high voltage MOS device 5 according to the present invention is significantly lower than that of the high voltage MOS device 2 of the prior art.

Fig. 11A-11Q show a ninth embodiment of the invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Taking the high voltage MOS device 5 of the third embodiment as an example, first, as shown in the top view schematic diagram of fig. 11A and the cross-sectional schematic diagram (corresponding to the cross-sectional line a-a' of fig. 11A) of fig. 11B, a semiconductor substrate 11 is provided, wherein the semiconductor substrate 11 is, for example, but not limited to, a P-type silicon substrate, but may be other semiconductor substrates. The semiconductor substrate 11 has an upper surface 11' and a lower surface 11 ″ facing each other in a longitudinal direction (e.g., the direction of the dotted arrow in fig. 11B). Next, as shown in fig. 11A and 11B, a first conductive type well region 12 is formed in the semiconductor substrate 11, and is located below the upper surface 11 'and connected to the upper surface 11' in the longitudinal direction; the method for forming the first conductive type well 12 is, for example, but not limited to, photolithography, ion implantation, and thermal process, which are well known in the art and will not be described herein.

Next, as shown in the top view diagram of fig. 11C and the cross-sectional diagram (corresponding to the cross-sectional line a-a' of fig. 11C) of fig. 11D, a field oxide region 20 is formed to define the active region of the high voltage MOS device 5; at the same time, a field oxide region 20 'is formed on the upper surface of the well region 11' and is stacked and connected directly above the well region 12. Next, as shown in the top view diagram of fig. 11E and the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 11E) of fig. 11F, a photoresist layer 16 ' is used as a mask to define an ion implantation region of the second conductive type body region 16, and second conductive type impurities are implanted into the defined region in the form of accelerated ions by an ion implantation process step to form the second conductive type body region 16 in the first conductive type well region 12, and is located below and connected to the upper surface 11 ' in the longitudinal direction.

Next, as shown in the top view of fig. 11G and the cross-sectional view of fig. 11H (corresponding to the cross-sectional line a-a 'of fig. 11G), a gate 53 not yet doped is formed on the upper surface 11', and a portion of the gate 53 is stacked and connected directly above a portion of the body region 16 of the second conductivity type in the vertical direction.

Next, as shown in the schematic top view of FIG. 11I, the schematic cross-sectional view of FIG. 11J (corresponding to the cross-sectional line A-A 'of FIG. 11I in the top view) and the schematic cross-sectional view of FIG. 11K (corresponding to the cross-sectional line B-B' of FIG. 11I in the top view), the field oxide region 20 and the photoresist layer 34' are used as a mask to define the ion implantation region of the first conductive type polysilicon layer in the plurality of first conductive type source sub-regions 341, the drain 17 and the gate 53, and the ion implantation process step is used to implant the first conductive type impurity, a polysilicon layer of the first conductivity type implanted in the defined region to form the gate 53, a source 34 of the first conductivity type (including a plurality of source sub-regions 341 of the first conductivity type) in the body region 16 of the second conductivity type, and a drain 17 in the well region 12, respectively, and in the vertical direction, the source electrode 34 and the drain electrode 17 of the first conductive type are both located below the upper surface 11 'and contact with the upper surface 11'. Wherein impurities of the first conductivity type are implanted into the polysilicon layer in the form of accelerated ion beams in the same ion implantation process step as the source 34 and drain 17 are formed, as indicated by the downward dashed arrows in fig. 11J. The first-conductivity-type drain 17 is located below the upper surface 11 'in the longitudinal direction and in contact with the upper surface 11', and is separated from the first-conductivity-type source region 34 in the lateral direction by the second-conductivity-type body region 16 and the first-conductivity-type well region 12.

Next, as shown in the top view diagram of fig. 11L, the cross-sectional diagram of fig. 11M (corresponding to the cross-sectional line a-a ' of fig. 11L in the top view), and the cross-sectional diagram of fig. 11N (corresponding to the cross-sectional line B-B ' of fig. 11L in the top view), using the photoresist layer 38 ' as a mask to define a plurality of second-conductivity-type body connection regions 38 and an ion implantation region of the second-conductivity-type polysilicon layer in the gate 53, and implanting second-conductivity-type impurities in the form of accelerated ions into the defined region in an ion implantation process step to form the second-conductivity-type polysilicon layer in the gate 53 and a plurality of second-conductivity-type body connection regions 38 in the second-conductivity-type body region 16, each body connection region 38 is located below the upper surface 11 ' in the longitudinal direction and in contact with the upper surface 11 ', and in this embodiment, each body connection region 38 is laterally adjacent to the first side S1 of the gate 53, the plurality of body connecting regions 38 are arranged substantially in parallel in the width direction, and each adjacent two body connecting regions 38 are at least partially not adjacent to each other in the width direction. In the present embodiment, each two adjacent body connecting regions 38 are not adjacent to each other in the width direction. In the present embodiment, the body connection regions 38 laterally adjoin the first side S1 of the gate 53 and separate the source 34 into a plurality of source sub-regions 341, wherein the source sub-regions 341 laterally adjoin the first side S1 of the gate 53, and wherein the source sub-regions 341 are arranged substantially parallel to the width direction and each adjacent two of the source sub-regions 341 are not contiguous to the width direction. In the present embodiment, when the second conductive type impurity is implanted into the defined region in the form of accelerated ions (as indicated by the downward dotted arrows in the figure) to form a plurality of second conductive type body connecting regions 38, the second conductive type impurity is also implanted into a portion of the gate electrode 53 in the form of accelerated ions, as illustrated in fig. 11M and 11N.

Next, as shown in the schematic top view of fig. 11O, the schematic cross-sectional view of fig. 11P (corresponding to the cross-sectional line a-a ' of fig. 11O in the top view), and the schematic cross-sectional view of fig. 11Q (corresponding to the cross-sectional line B-B ' of fig. 11O in the top view), the photoresist layer 53 ' is used as a mask to define an ion implantation region of the gate compensation region 531, and first conductive type impurities are implanted in the form of accelerated ions into the region defined in the polysilicon layer to offset and invert a portion of the polysilicon layer of the gate 53 having the second conductive type into the first conductive type, so that all portions of the polysilicon layer have the first conductive type.

Fig. 12A-12F show a tenth embodiment of the invention. This embodiment shows a method for manufacturing a high voltage MOS device according to the present invention. Take the high voltage MOS device 6 in the fourth embodiment of the present invention shown in fig. 6A to 6C as an example. The steps of the foregoing manufacturing method are the same as those of the eighth embodiment of the present invention shown in FIGS. 10A-10H, please refer to FIGS. 10A-10H.

Next, as shown in the top view diagram of fig. 12A, the cross-sectional diagram (corresponding to the cross-sectional line a-a ' of fig. 12A in the top view), shown in fig. 12B, and the cross-sectional diagram (corresponding to the cross-sectional line B-B ' of fig. 12A in the top view) of fig. 12C, as shown, the field oxide region 20 and the photoresist layer 44 ' are used as a mask to define the ion implantation regions of the gate 53 and the first conductive source 44 and the drain 17, and the first conductive impurity is implanted into the defined regions in the form of accelerated ions by the ion implantation process step to form the first conductive polysilicon layer of the gate 53, the first conductive source 44 in the second conductive body region 16, and the drain 17 in the well region 12, respectively, and in the vertical direction, the first conductive source 44 and the drain 17 are both located below the upper surface 11 ' and in contact with the upper surface 11 '. In the same ion implantation step as that for forming the source 44 and the drain 17, as shown by the downward dashed arrows in fig. 12B and 12C, the first conductivity type impurity is implanted into the polysilicon layer in the form of an accelerated ion beam. The first-conductivity-type drain 17 is located below the upper surface 11 'in the longitudinal direction and in contact with the upper surface 11', and is separated from the first-conductivity-type source 44 in the lateral direction by the second-conductivity-type body region 16 and the first-conductivity-type well region 12.

Next, as shown in the schematic top view shown in fig. 12D, the schematic cross-sectional view shown in fig. 12E (corresponding to the cross-sectional line a-a ' of the top view fig. 12D) and the schematic cross-sectional view shown in fig. 12F (corresponding to the cross-sectional line B-B ' of the top view fig. 12D), the photoresist layer 48 ' is used as a mask to define a plurality of ion implantation regions of the second conductive type body connection regions 48, and second conductive type impurities are implanted into the defined regions in the form of accelerated ions to form a plurality of second conductive type body connection regions 48 in the second conductive type body regions 16, each body connection region 48 is located below the upper surface 11 ' in the longitudinal direction and is in contact with the upper surface 11 ', and in the present embodiment, each body connection region 48 is not adjacent to the first side S1 of the gate 33 in the transverse direction, the plurality of body connection regions 48 are arranged substantially parallel in the width direction, and each adjacent two body connection regions 48 are at least in the width direction The sections are not contiguous. In the present embodiment, each two adjacent body connecting regions 48 are not adjacent to each other in the width direction. In the present embodiment, the plurality of body connection regions 48 are not adjacent to the first side S1 of the gate 53 in the lateral direction, and the source 44 is adjacent to the first side S1 of the gate 53 in the lateral direction, respectively. In the present embodiment, the photoresist layer 48' is formed to shield the gate electrode 53, so as to prevent impurities of the second conductivity type from being implanted into the polysilicon layer of the gate electrode 53 in the form of an accelerated ion beam in the ion implantation process step for forming the plurality of body connection regions 48.

It should be noted that the present embodiment is different from the eighth embodiment shown in fig. 10A to 10N in that: in the present embodiment, the plurality of body connection regions 48 of the high voltage MOS device 6 are laterally not adjacent to the first side S1 of the gate 53, and the body connection regions 48 are laterally spaced apart from the first side S1 of the gate 53 by at least a predetermined pitch dp. In the present embodiment, the source 44 is not divided into a plurality of source sub-regions by the body connecting regions 48, but is a fully connected region.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as threshold voltage adjustment regions, may be added without affecting the primary characteristics of the device; for another example, the lithography technique is not limited to the mask technique, but may include electron beam lithography; for another example, the conductive type P and N can be interchanged, and only other regions are required to be correspondingly interchanged. The scope of the invention should be determined to encompass all such equivalent variations. Furthermore, equivalent variations and combinations will occur to those skilled in the art, within the same spirit of the invention, for example, the invention may be applied to other types of high voltage components. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A high voltage metal oxide semiconductor device formed on a semiconductor substrate, wherein the semiconductor substrate has an upper surface and a lower surface opposite to each other in a longitudinal direction, the high voltage metal oxide semiconductor device comprising:

a well region of a first conductivity type formed in the semiconductor substrate and located below and connected to the upper surface in the longitudinal direction;

a body region of a second conductivity type formed in the well region and located below and connected to the upper surface in the longitudinal direction;

a gate formed on the upper surface, wherein a portion of the gate is stacked and connected over a portion of the body region in the longitudinal direction;

a source of the first conductivity type formed in the body region and in the longitudinal direction, the source being located below and contacting the upper surface and laterally adjacent to a first side of the gate;

a plurality of body contact regions of the second conductivity type formed in the body region, wherein each body contact region is located below and in contact with the upper surface in the longitudinal direction and is adjacent to the first side of the gate in the lateral direction, wherein the body contact regions are arranged substantially parallel to a width direction and adjacent to each other in the width direction; and

a drain of the first conductivity type formed in the well region, the drain being located below and contacting the upper surface in the longitudinal direction, and being located outside a second side of the gate in the lateral direction, and being separated from the source by the body region and the well region;

wherein the gate has a polysilicon layer as one and only electrical contact to the gate, and all portions of the polysilicon layer have the first conductivity type;

the source electrode is separated into a plurality of source electrode sub-regions by the plurality of body connecting regions, wherein the plurality of source electrode sub-regions are adjacent to the first side of the gate electrode in the transverse direction, and the plurality of source electrode sub-regions are arranged in parallel in the width direction, and each two adjacent source electrode sub-regions are not adjacent to each other in the width direction.

2. The HV-MOS device of claim 1, further comprising a field oxide region formed on said top surface and stacked over a portion of said well region, wherein a portion of said gate in said lateral direction near said drain side, including said second side of said gate, is stacked over and connected over at least a portion of said field oxide region.

3. A method for fabricating a high voltage MOS device, comprising:

providing a semiconductor substrate, which is provided with an upper surface and a lower surface opposite to each other in a longitudinal direction;

forming a well region in the semiconductor substrate, the well region having a first conductivity type and being located below and connected to the upper surface in the longitudinal direction;

forming a body region of a second conductivity type in the longitudinal direction under and connected to the upper surface in the first conductivity type well region;

forming a gate on the upper surface, wherein a portion of the gate is stacked and connected over a portion of the body region in the longitudinal direction;

forming a source electrode in the body region, the source electrode having the first conductivity type and being located below and contacting the upper surface in the longitudinal direction and being laterally adjacent to a first side of the gate electrode;

forming a plurality of body-tie regions in the body region, the body-tie regions having the second conductivity type, wherein each of the body-tie regions is disposed below and in contact with the upper surface in the longitudinal direction and is adjacent to the first side of the gate in the lateral direction, wherein the body-tie regions are arranged substantially parallel to a width direction and each adjacent two of the body-tie regions are not adjacent to each other in the width direction; and

forming a drain of the first conductivity type in the well region, the drain being located below and contacting the upper surface in the longitudinal direction and outside a second side of the gate in the lateral direction, the drain being separated from the source by the body region and the well region;

4. The method of claim 3, further comprising: forming a field oxide region on the upper surface, and stacking and connecting the field oxide region right above the well region, wherein a portion of the gate electrode close to the drain electrode side in the transverse direction includes the second side of the gate electrode, and the field oxide region is stacked and connected right above at least a portion of the field oxide region.

5. The method of claim 3, wherein the step of forming the gate comprises:

implanting impurities of a first conductivity type into the polysilicon layer in the form of accelerated ion beams in the same first ion implantation process step as that for forming the source and/or the drain; and

a photoresist layer is formed to shield the gate electrode, so that second conductivity type impurities are prevented from being implanted into the polysilicon layer in the form of accelerated ion beams in a second ion implantation process step for forming the plurality of body connection regions.

6. The method of claim 3, wherein the step of forming the gate comprises:

implanting impurities of the first conductivity type into the polysilicon layer in the form of accelerated ion beams in a second ion implantation process step to offset-invert the regions of the second conductivity type in the polysilicon layer to the first conductivity type so that all portions of the polysilicon layer have the first conductivity type.