CN114362752B

CN114362752B - Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Info

Publication number: CN114362752B
Application number: CN202011087957.6A
Authority: CN
Inventors: 杨培; 殷秀梅
Original assignee: Beijing Tebang Microelectronic Technology Co ltd
Current assignee: Beijing Tebang Microelectronic Technology Co ltd
Priority date: 2020-10-13
Filing date: 2020-10-13
Publication date: 2024-06-14
Anticipated expiration: 2040-10-13
Also published as: CN114362752A

Abstract

The present disclosure relates to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter, the circuit being a stage of the pipeline analog-to-digital converter, comprising: SADC module, comparison module, MDAC module and control module, SADC module is used to convert the input analog signal into digital signal; the MDAC module is used for outputting a residual difference signal of the analog signal and the digital signal; the control module is used for performing correction control. When the residual signal exceeds a preset first voltage interval, the control module judges that the circuit meets the adjustment condition, and adjusts the clock deviation amount of the SADC module or the comparison module by the first control signal and the second control signal so as to adjust the residual signal to be in the first voltage interval. According to the embodiment of the disclosure, the real-time correction of the sampling time deviation of the MDAC module and the SADC module in the pipelined analog-to-digital converter can be realized at a lower circuit cost, and the accuracy of the analog-to-digital conversion circuit is improved.

Description

Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter.

Background

The pipelined Analog-to-Digital Converter (ADC) is composed of several stages of Analog-to-digital conversion modules with similar functions, each including a sub-Analog-to-digital conversion (SADC) module and a digital-to-Analog conversion and amplification (MDAC) module, etc.

The accuracy of the pipelined ADC is closely related to the signal processing accuracy of the MDAC module, and the quantization result of the SADC module affects the signal processing accuracy of the MDAC module. For example, the sampling time deviation of the comparator in the SADC module has a great influence on the accuracy of the MDAC module, and under normal conditions, the MDAC and the SADC sample the dynamic input signal of the ADC at the same time, the sampled signal voltages are consistent, and the absolute value of the output amplitude of the MDAC residual voltage should be half of the full amplitude voltage of the ADC. When the sampling time deviation of the comparator exists, the signal voltages obtained by sampling the MDAC and SADC are inconsistent, which is equivalent to the change of the threshold value of the comparator, and the output amplitude of the residual voltage of the MDAC is increased, so that the performance of the MDAC module is deteriorated, and under the more serious condition, the absolute value of the amplitude of the residual voltage exceeds the full-amplitude voltage of the ADC, and the ADC loses codes. Therefore, to ensure the accuracy of the pipelined ADC, the comparator sample time offset index needs to be controlled within a certain range.

Disclosure of Invention

In view of this, the disclosure provides an analog-to-digital conversion circuit, which can correct the sampling time offset of the comparator in real time and improve the accuracy of the analog-to-digital conversion circuit with a smaller circuit cost when the pipeline analog-to-digital converter works.

According to an aspect of the present disclosure, there is provided an analog-to-digital conversion circuit, the circuit being a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-module-digital conversion SADC module, a digital-to-analog conversion and amplification MDAC module, a comparison module and a control module,

The first input end of the SADC module inputs a clock signal, the second input end inputs a first control signal, the third input end inputs a first analog signal, and the output end outputs a first digital signal;

The first input end of the comparison module inputs the clock signal, the second input end inputs the second control signal, the third input end inputs the first analog signal, and the output end outputs the second digital signal;

the first input end of the MDAC module inputs the clock signal, the second input end inputs the first analog signal, the third input end inputs the first digital signal, and the output end outputs a residual difference signal;

the first input end of the control module inputs the first digital signal, the second input end inputs the second digital signal, the third input end inputs the residual difference signal, the output end outputs the first control signal and the second control signal,

Wherein, the control module is used for:

Judging whether the analog-to-digital conversion circuit meets an adjusting condition or not, wherein the adjusting condition comprises that the residual difference signal exceeds a preset first voltage interval;

Under the condition that the analog-to-digital conversion circuit meets the regulation condition, determining a reference residual signal of the comparison module according to the first digital signal, the residual signal and the second digital signal;

And adjusting the first control signal or the second control signal according to the relation between the residual signal and the reference residual signal so that the residual signal is adjusted to be within the first voltage interval, wherein the first control signal is used for adjusting the clock offset of the SADC module, and the second control signal is used for adjusting the clock offset of the comparison module.

In one possible implementation, the SADC module includes a first conditioning unit and N comparators, the first digital signal includes an N-bit digital signal, N is an integer greater than 1,

The first adjusting unit is connected to the N comparators and is used for adjusting the deviation amount of the clock signals and outputting first deviation clock signals with first clock deviation amounts;

The N comparators input the first analog signal and the first offset clock signal, the ith comparator of the N comparators is used for comparing the sampling voltage of the first analog signal with the reference voltage of the ith comparator, outputting the compared ith digital signal, i is an integer and is more than or equal to 1 and less than or equal to N,

Wherein the first adjusting unit is further configured to: and adjusting the first clock offset according to the first control signal.

In one possible implementation, the comparison module comprises a second adjustment unit and a replica comparator,

The second adjusting unit is connected to the replica comparator and is used for adjusting the deviation amount of the clock signal and outputting a second deviation clock signal with a second clock deviation amount;

The replica comparator inputs the first analog signal and the second offset clock signal, the reference voltage of the replica comparator is the same as the j-th comparator in the N comparators, the replica comparator is used for comparing the sampling voltage of the first analog signal with the reference voltage of the replica comparator, the compared digital signal is output, j is an integer and 1< j < N,

Wherein the second adjusting unit is further configured to: and adjusting the second clock offset according to the second control signal.

In one possible implementation, the adjusting conditions further include: the second digital signal is different from the j-th bit of the first digital signal.

In one possible implementation, the determining, by the control module, the reference residual signal of the comparison module according to the first digital signal, the residual signal, and the second digital signal includes:

converting the analog form of the residual signal into a digital form of the residual signal;

determining an equivalent input voltage of the analog-to-digital conversion circuit according to the digital form residual difference signal and the first digital signal;

and determining the reference residual signal according to the equivalent input voltage, the second digital signal and the first digital signal.

In one possible implementation, the control module adjusts the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal, including:

And adjusting the first control signal to control the first adjusting unit of the SADC module to adjust the first clock offset toward a direction approaching to a second clock offset in case that the absolute value of the voltage of the residual signal is greater than the absolute value of the voltage of the reference residual signal.

In one possible implementation manner, the control module adjusts the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal, and further includes:

And adjusting the second control signal to control the second adjusting unit of the comparison module to adjust the second clock offset toward a direction approaching the first clock offset when the absolute value of the voltage of the residual signal is smaller than the absolute value of the voltage of the reference residual signal.

In one possible implementation, after the residual signal is adjusted to be within the first voltage interval, the method further includes:

And adjusting the second control signal to control the second adjusting unit of the comparison module to adjust the second clock offset in a direction away from the first clock offset when the absolute voltage value of the residual signal is smaller than or equal to the absolute voltage value of the reference residual signal.

In one possible implementation, [ N/2] -1<j +.1 +.N/2 ].

According to another aspect of the present disclosure, there is provided a pipelined analog-to-digital converter comprising a plurality of stages of analog-to-digital conversion circuits, each stage of analog-to-digital conversion circuit comprising an analog-to-digital conversion circuit as described above.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are added in the circuit, the control module is used for acquiring the signal output by the circuit, and under the condition that the output signal meets the regulation condition, the control signal is output to regulate the clock deviation of the SADC module or the comparison module, so that the real-time correction of the analog-to-digital conversion circuit is realized at a lower circuit cost, and the correction precision of the analog-to-digital conversion circuit is improved.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a one-stage analog-to-digital conversion circuit of a pipelined analog-to-digital converter according to the related art.

Fig. 2a and 2b are schematic diagrams showing a circuit configuration of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing thereof, respectively.

Fig. 3 is a schematic diagram showing a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 4 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure.

Fig. 5 shows a block diagram of SADC modules according to one embodiment of the present disclosure.

Fig. 6 shows a block diagram of a comparator according to an embodiment of the present disclosure.

Fig. 7 shows a block diagram of a comparison module according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Fig. 1 is a schematic diagram of a primary analog-to-digital conversion circuit of a pipelined analog-to-digital converter according to the related art. For example, a pipelined ADC may include several stages of analog-to-digital conversion circuits that are functionally similar, as shown in fig. 1, an analog-to-digital conversion circuit 10 according to the related art may include:

The sub-analog-to-digital conversion (SADC) module 101, wherein a clock signal CLK ₀ is input to a first input end of the sadc module 101, an analog signal V _in0 is input to a second input end, and an analog-to-digital converted digital signal D ₀₁ is output to an output end; if the analog signal is not the first-stage analog-to-digital conversion circuit, V _in0 is the analog signal provided by the previous-stage analog-to-digital conversion circuit;

in one possible implementation, as shown in fig. 1, SADC module 101 may include a plurality of comparators (e.g., 8 comparators), the sampling paths of the plurality of comparators include a sample holder (S/H), a first input terminal of the sample holder inputs clock signal CLK ₀, a second input terminal inputs analog signal V _in0, and an output terminal outputs a voltage value of the sample-held analog signal V _in0 to each of the comparators; the f-th comparator of the plurality of comparators may have a reference voltage V _c0f, (1. Ltoreq.f. Ltoreq.the number of comparators), and the value of V _c0f may be different according to the value of f (for example, the reference voltage of the 1 st comparator may be V _c01). Each comparator compares the voltage value of the analog signal V _in0 with the respective reference voltage and outputs a one-bit digital signal; until all comparators complete the comparison of the voltage value of the analog signal V _in0 with the reference voltage, the digital signal D ₀₁ is formed in the order of the number of comparators.

The digital-to-analog conversion and amplification (MDAC) module 102, the MDAC module 102 is connected to the SADC module 101, the first input terminal inputs the clock signal CLK ₀, the second input terminal inputs the analog signal V _in0, the third input terminal inputs the digital signal D ₀₁, and the output terminal outputs the residual signal V _res0.

In one possible implementation, as shown in FIG. 1, the MDAC module 102 may include a sample holder (S/H), a digital-to-analog converter (DAC), an adder, and a gain unit including an operational amplifier (OPA). The first input end of the sampling holder inputs the clock signal CLK ₀, the second input end inputs the analog signal V _in0, and the output end outputs the voltage value of the analog signal V _in0 after sampling and holding to the adder; the input end of the DAC inputs a digital signal D ₀₁, and the output end of the DAC is connected with one input end of the adder; the other input end of the adder inputs the voltage value of the analog signal V _in0 after sampling and holding, and the output end is connected with the input end of the gain unit; the output end of the gain unit outputs a residual signal V _res0.

For example, the clock signal CLK ₀ and the analog signal V _in0 enter both the SADC module 101 and the MDAC module 102, and coarse quantization (i.e., preliminary analog-to-digital conversion) is performed in the SADC module 101, for example, 1-4 bits are quantized, and the quantized result (digital signal D ₀₁) is sent to the MDAC module 102. The MDAC module 102 converts the output of the SADC module 101 into different reference voltages, subtracts the analog signal V _in0 from the reference voltage, amplifies the subtracted signal by several times by the gain unit to obtain a residual signal V _res0, and sends the residual signal V _res0 to the next stage for processing.

Fig. 2a and 2b are schematic diagrams of a circuit structure of an MDAC module of an analog-to-digital conversion circuit and a circuit timing thereof according to the related art, respectively. Fig. 3 is a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 2a illustrates an exemplary circuit configuration of the MDAC module 102, and fig. 2b illustrates clock signals of the MDAC module illustrated in fig. 2 a. The clock signal may include two inverted clocks Φ ₁ and Φ ₂, where T _clk represents the period of the system clock, C _S,1-C_S,m represents the sampling capacitance, m represents the number of sampling capacitances, C _stg2 represents the sampling capacitance of the second stage, C _F represents the feedback capacitance, and V _rp and V _rn represent the positive and negative reference voltages, respectively.

In one possible implementation, as shown in fig. 2a, after the Φ ₁ phase (e.g., Φ ₁ is high and 1/2 clock period T _clk),V_in0 is sampled into each sampling capacitor C _S,1-C_S,m. After the sampling is finished (e.g., Φ ₁ is low), each switch of Φ ₁ phase is opened, the switch of Φ ₂ phase (e.g., Φ ₂ is high and 1/2 clock period T _clk) is closed, at this time, the voltage of the lower plate of each capacitor C _S,1-C_S,m is controlled by the output signal of the SADC module 101, and according to the output signal (quantized result) of the SADC module 101, the connection V _rp or V _rn is selected to implement digital-analog conversion in the MDAC, so as to form a transmission curve as shown in fig. 3. OPA works in a closed-loop negative feedback state, according to the principle of charge conservation and ideal OPA, it can be obtained:

In the formula (1), V _res0 represents a residual signal output by the MDAC module 102, V _in0 represents an input analog signal, D _0f represents an f-th bit of a digital signal D ₀₁ of the SADC module 101, D _0f has a value range of [0,1], C _S,f represents a capacitance value of an f-th sampling capacitor, f is an integer between 1 and m, C _F represents a capacitance value of a feedback capacitor, V _ref0 represents a full-width voltage of the pipeline ADC, and the input signal range of the pipeline ADC is within a range of [ -V _ref0,V_ref0 ].

As shown in the transmission curve of fig. 3, the ideal transmission characteristic curve is shown in solid line, the MDAC modules 102 and SADC module 101 sample the analog signal V _in0 simultaneously, the sampled signal voltages are consistent, and the MDAC residual voltage output amplitude is about ±0.5v _ref0. When the sampling time of the comparator deviates, the signal voltages sampled by the MDAC module 102 and the SADC module 101 are inconsistent, which is equivalent to the change of the threshold value of the comparator. The transmission characteristic curve is shifted as shown by the dotted line, the output amplitude of the residual signal V _res0 is increased, so that the performance of the MDAC module 102 is deteriorated, and in a more serious case, the amplitude of the residual signal V _res0 exceeds ±v _ref0, and the ADC is out of code. To ensure ADC accuracy, the comparator sample offset index needs to be controlled within a certain range.

In the related art, a sample-and-hold circuit is generally added to the front end of the ADC, or the comparator sampling time deviation error is corrected when the ADC is not in operation. However, the method of adding a sample-and-hold circuit to the front end of the ADC can significantly increase the cost of the analog circuit, increase power consumption, noise, and the like. When the ADC is not in operation, the method for correcting the sampling time deviation error of the comparator cannot track the change of the sampling time deviation error of the comparator along with different environment temperatures and operating voltages because the method is not in real-time correction, and the correction accuracy is limited.

Fig. 4 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the disclosure. The circuit 40 is any stage of a pipelined ADC. As shown in fig. 4, the circuit 40 includes: a sub analog-to-digital conversion SADC module 401, a comparison module 402, a digital-to-analog conversion and amplification MDAC module 403 and a control module 404,

The sub-adc SADC module 401 has a first input terminal receiving the clock signal CLK, a second input terminal receiving the first control signal D _{ctrl_1}, a third input terminal receiving the first analog signal V _in, and an output terminal outputting the first digital signal D ₁;

The first input terminal of the comparison module 402 inputs the clock signal CLK, the second input terminal inputs the second control signal D _{ctrl_2}, the third input terminal inputs the first analog signal V _in, and the output terminal outputs the second digital signal D ₂;

The digital-to-analog conversion and amplification MDAC module 403 has a first input terminal receiving the clock signal CLK, a second input terminal receiving the first analog signal V _in, a third input terminal receiving the first digital signal D ₁, and an output terminal outputting the residual signal V _res;

The control module 404 has a first input for the first digital signal D ₁, a second input for the second digital signal D ₂, a third input for the residual signal V _res, and an output for the first control signal D _{ctrl_1} and the second control signal D _{ctrl_2},

Wherein the control module 404 is configured to:

judging whether the analog-to-digital conversion circuit 40 meets the regulation conditions, wherein the regulation conditions comprise that the residual difference signal exceeds a preset first voltage interval;

Under the condition that the analog-to-digital conversion circuit meets the regulation condition, determining a reference residual signal D _{res_r} of the comparison module according to the first digital signal D ₁, the residual signal V _res and the second digital signal D ₂;

According to the relation between the residual signal and the reference residual signal, the first control signal D _{ctrl_1} or the second control signal D _{ctrl_2} is adjusted so that the residual signal is adjusted to be within the first voltage interval, the first control signal D _{ctrl_1} is used for adjusting SADC the clock offset of the module 401, and the second control signal D _{ctrl_2} is used for adjusting the clock offset of the comparison module.

For example, the MDAC module 403 may employ a related-art circuit structure. SADC module 401 may include a plurality of comparators for quantizing the input first analog signal and outputting a quantized multi-bit digital signal (i.e., a first digital signal). Each comparator of SADC modules has a reference voltage, for example the reference voltage of the 1 st comparator can be denoted by V _c1. The comparison module 402 may include at least one comparator having a structure identical to that of the comparator of the SADC module 401, and the comparison module 402 inputs the first analog signal and outputs the quantized at least one digital signal (i.e., the second digital signal). At least one comparator of the comparison module 402 has a reference voltage, e.g., the reference voltage of the 1 st comparator may be denoted by V _{c_1}. SADC module 401 and comparison module 402 each include a sample-and-hold (S/H) that samples first analog signal V _in according to clock signal CLK, outputting the voltage value of the sample-and-hold first analog signal V _in to each comparator.

In one possible implementation, an adjustment unit may be added before the sample holders of SADC module 401 and comparison module 402, and different clock offsets may be set for SADC module 401 and comparison module 402, respectively, to correct the analog-to-digital conversion circuit by adjusting the clock offsets when the analog-to-digital conversion circuit accuracy decreases. Wherein the regulating unit may, for example, comprise a plurality of inverters connected in series, the specific structure of the regulating unit is not limited by the present disclosure.

In one possible implementation, the clock signal CLK enters SADC module 401, the comparison module 402, and the MDAC module 403 simultaneously with the first analog signal V _in when the analog-to-digital conversion circuit is operating. SADC module 401 and comparison module 402 perform analog-to-digital signal conversion to obtain a first digital signal D ₁ and a second digital signal D ₂, respectively. The first digital signal D ₁ output by the SADC module 401 is input to the MDAC module 403, processed by the MDAC module 403, and output the residual signal V _res, and sent to the next stage of analog-to-digital conversion circuit for processing.

In a possible implementation, the analog-to-digital conversion circuit 40 may further be provided with a control module 404 for implementing a correction control of the analog-to-digital conversion circuit. During operation of the analog-to-digital conversion circuit 40, the control module 404 may obtain a plurality of signals output by the circuit, including the first digital signal D ₁, the second digital signal D ₂, and the residual signal V _res, and determine whether the analog-to-digital conversion circuit 40 meets the adjustment condition according to at least one of the signals.

In one possible implementation, the adjustment condition may include the residual signal exceeding a preset first voltage interval. That is, if the residual signal exceeds the preset first voltage interval, the sampling time deviation error of the comparator is considered to be large, and the MDAC performance is deteriorated and needs to be adjusted. The first voltage interval may be set according to the reference voltage V _ref and the circuit structure of the analog-to-digital conversion circuit, for example, the first voltage interval may be set to [ - (1/2) V _ref,(1/2)V_ref ], which is not limited by the specific value of the first voltage interval in the disclosure.

In one possible implementation, the adjustment condition may also be other conditions, for example, when the corresponding signal bits of the second digital signal D ₂ and the first digital signal D ₁ are different, it is determined that the adjustment condition is satisfied; the adjustment condition may also be at least one of a plurality of conditions being satisfied. It should be understood that the adjusting conditions of the analog-to-digital conversion circuit can be set by those skilled in the art according to the actual situation, and the present disclosure is not limited thereto.

In one possible implementation, the control module 404 may output an initial first control signal and an initial second control signal such that SADC module 401 and comparison module 402 have different clock offsets if the analog-to-digital conversion circuit satisfies the adjustment condition. The control module can calculate a reference residual signal D _{res_r} of the comparison module according to the first digital signal D ₁, the second digital signal D ₂ and the residual signal; the relationship between the residual signal and the calculated reference residual signal D _{res_r} is determined, and the first control signal D _{ctrl_1} is selectively adjusted to adjust SADC the clock offset of the module 401, or the second control signal D _{ctrl_2} is selectively adjusted to adjust the clock offset of the comparison module 402.

In one possible implementation, if the absolute voltage value of the residual signal is greater than the absolute voltage value of the reference residual signal, then the clock skew error of SADC module 401 may be considered to be greater, and the control module may adjust the output of the first control signal D _{ctrl_1} to adjust the clock skew of SADC module 401; conversely, if the absolute voltage value of the reference residual signal is greater than the absolute voltage value of the residual signal, the clock skew error of the comparison module 402 may be considered to be greater, and the control module may adjust the output of the second control signal D _{ctrl_2} to adjust the clock skew of the comparison module 402.

In one possible implementation, the first control signal D _{ctrl_1} and the second control signal D _{ctrl_2} are adjustable control signals including information indicating the manner of adjustment of the clock skew, and upon receipt of the control signals, the SADC module 401 or the comparison module 402 may implement the adjustment of the clock skew, for example, by changing the number of inverters through which the clock signal CLK passes in the adjustment unit. The present disclosure is not limited to a particular manner of adjustment.

In one possible implementation, through multiple adjustments, if the residual signal is adjusted to be within the first voltage interval, the comparator sampling time deviation error can be considered to be within a range allowed by the precision, the MDAC module can meet the performance requirement, and the control module can end the adjustment process.

In one possible implementation, after the control module controls SADC the clock offset of the module 401 to make one or more adjustments, the residual signal may be adjusted to a preset first voltage interval, in which case, if the absolute voltage value of the residual signal is less than or equal to the absolute voltage value of the reference residual signal, for the purpose of further compressing the residual signal swing, the control module may adjust the second control signal D _{ctrl_2} to search for a more suitable clock offset in a direction in which the second clock offset increases or decreases to try to determine whether the effect of compressing the signal swing of the residual signal can be achieved. If the swing of the residual signal obtained after the adjustment D _{ctrl_2} is found to be reduced during the probing process, the control module may adjust the first control signal D _{ctrl_1} to approach the second control signal D _{ctrl_2} to reduce the output swing of the MDAC module 403.

In one possible implementation, noise may be present in the circuit, which has an effect on the magnitude of the residual signal as well as the reference residual signal. After the relation between the residual signal and the reference residual signal can be judged for multiple times, how to adjust the first control signal or the second control signal to adjust SADC the clock offset of the module 401 or the comparison module 402 is determined, so that the influence of noise on the circuit is reduced, and the correction precision is ensured.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are added in the circuit, the control module is used for acquiring the signals output by the circuit, and under the condition that the output signals meet the regulation conditions, the control signal is output to regulate the clock deviation of the SADC module or the comparison module, so that the real-time correction of the sampling time deviation of the MDAC module and the SADC module in the analog-to-digital conversion circuit is realized at a lower circuit cost, and the precision of the analog-to-digital conversion circuit is improved.

Fig. 5 shows a schematic structural diagram of SADC module according to one embodiment of the present disclosure. As shown in fig. 5, in one possible implementation, SADC module 401 may include a first conditioning unit 4011 and N comparators (e.g., 8 comparators), the first digital signal including an N-bit digital signal, N being an integer greater than 1,

The first adjustment unit 4011 is connected to the N comparators for adjusting the offset amount of the clock signal, and outputs a first offset clock signal having a first clock offset amount;

The N comparators input a first analog signal V _in and a first offset clock signal, the ith comparator of the N comparators can be used for comparing the sampling voltage of the first analog signal V _in with the reference voltage V _ci of the ith comparator, outputting a compared ith digital signal, i is an integer and is more than or equal to 1 and less than or equal to N,

Wherein, the first adjusting unit 4011 can be further used for: the first clock offset is adjusted according to the first control signal D _{ctrl_1}.

For example, the first adjustment unit 4011 may be disposed in the sampling path of the SADC module 401, and the clock signal CLK is input to the first adjustment unit 4011 before the sample holders (S/H) of the N comparators, and outputs the first offset clock signal having the first clock offset. The first adjustment unit 4011 may include a plurality of inverters connected in series, for example.

In one possible implementation, the initial first control signal may be preset when the analog-to-digital conversion circuit starts to operate, the first clock offset may be adjusted according to the preset initial first control signal, and the clock signal CLK may be passed through a preset number of inverters, for example, to obtain the first offset clock signal having the first clock offset.

In one possible implementation, the sample-and-hold devices of the N comparators may sample the first analog signal V _in according to the input first offset clock signal, and output the voltage value of the sampled and held first analog signal to each comparator.

Fig. 6 shows a schematic diagram of a structure of a comparator according to an embodiment of the present disclosure. Fig. 6 shows any one of the comparators, as shown in fig. 6, in which the input first analog signal V _in is sampled/held, compared with the reference voltage V _c of the comparator, and when V _in≥V_c, the comparator outputs D ₀ =1; when V _in<V_c, the comparator output D ₀ =0. Thus, after comparison by the N comparators, SADC module 401 outputs an N-bit digital signal, i.e., first digital signal D ₁, so as to implement quantization of the analog signal.

In one possible implementation, the ith comparator of the SADC module 401 has a reference voltage V _ci (e.g., the 1 st comparator has a reference voltage V _c1), and may be divided by the reference voltage V _ref of the analog-to-digital conversion circuit, for example, when the number of comparators of the SADC module 401 is 8, the reference voltages of the 1 st comparator to the 8 th comparator may be ：-7/8V_ref,-5/8V_ref,-3/8V_ref,-1/8V_ref,1/8V_ref,3/8V_ref,5/8V_ref,7/8V_ref.N comparators respectively compare the voltage value of the first analog signal with the respective reference voltages, and output an N-bit digital signal (e.g., the N takes 8,i to take 3, the 3 rd comparator may output the 3 rd digital signal, and the 8 comparators may output the 8-bit digital signal altogether), and the N-bit digital signal may be sequenced according to the number of bits, so as to obtain the first digital signal D ₁.

In one possible implementation, the comparison results output by the N comparators may be n+1, for example, the comparison results output by the 8 comparators may be 9, as shown in table 1:

TABLE 1

In Table 1, D _i represents the ith bit of the digital signal D ₁ of SADC module 401, D _i has a range of [0,1], and D _1,k represents the possible kth output result, 1.ltoreq.i.ltoreq.N, 1.ltoreq.k.ltoreq.N+1.

In one possible implementation, the SADC module may ultimately quantize g bits of data, where g is related to the number of possible outputs of the comparators in the SADC module 401, and g may take a minimum value that satisfies n+1.ltoreq.2 ^g. For example, if there are 9 possible outputs from 8 comparators, g may take 4 and the sadc module quantizes 4 bits. That is, a digital signal of four bits is finally output to an external circuit.

In one possible implementation, the first adjustment unit 4011 is further input with a first control signal D _{ctrl_1}. The first control signal D _{ctrl_1} may include information indicating a degree of adjustment of the first clock skew, and the first adjustment unit 4011 may adjust SADC the first clock skew of the module 401 according to the first control signal D _{ctrl_1}, for example, increase or decrease the number of inverters through which the clock signal CLK passes, thereby reducing the comparator sampling time skew error of the module SADC and improving the performance of the MDAC module.

In one possible implementation manner, when the analog-to-digital conversion circuit starts to operate, an initial second control signal may be preset, and a second clock offset may be adjusted according to the preset initial second control signal, where the second clock offset may be different from the first clock offset of the SADC module 401. For example, the first clock offset may be set to 0, and the second clock offset may be set to a positive offset or a negative offset. Whether the first control signal is adjusted to adjust the first clock offset can be determined according to the output result of the SADC module and the residual error signal, and when the first clock offset needs to be adjusted, the adjusting direction of the first clock offset can be determined according to the output result of the comparison module, so that the first control signal D _{ctrl_1} is adjusted to reduce the offset error between the sampling time of the comparator and the sampling time of the MDAC. The specific settings of the initial first control signal and the initial second control signal are not limited by the present disclosure.

In this way, a SADC module with an adjustable clock offset is realized, so that real-time correction of sampling time offset of the MDAC module and the SADC module of the analog-to-digital conversion circuit can be realized at a low circuit cost.

Fig. 7 shows a block diagram of a comparison module according to an embodiment of the present disclosure. In one possible implementation, the comparison module 402 may include a second adjustment unit 4021 and a replica comparator,

The second adjustment unit 4021 is connected to the replica comparator, and is operable to adjust the offset of the clock signal, and output a second offset clock signal having a second clock offset;

The replica comparator inputs the first analog signal V _in and the second offset clock signal, the reference voltage of the replica comparator is the same as the j-th comparator in the N comparators, the replica comparator is used for comparing the sampling voltage of the first analog signal V _in with the reference voltage of the replica comparator, the compared digital signals are output, j is an integer and 1< j < N,

Wherein the second adjustment unit 4021 is further configured to: the second clock offset is adjusted according to the second control signal D _{ctrl_2}.

For example, the second adjustment unit 4021 may be disposed in the sampling path of the comparison module 402, placed before the sample holder (S/H) of the replica comparator, and the clock signal CLK is input into the second adjustment unit 4021 to output a second offset clock signal having a second clock offset. The second adjusting unit 4021 may include, for example, a plurality of inverters connected in series.

In one possible implementation, when the analog-to-digital conversion circuit starts to operate, an initial second control signal may be preset, a second clock offset may be adjusted according to the preset initial second control signal, and the clock signal CLK may be passed through a preset number of inverters, for example, to obtain a second offset clock signal having the second clock offset.

In one possible implementation, the sample-and-hold of the replica comparators may sample the first analog signal V _in according to the input second off-clock signal, outputting the voltage value of the sample-and-hold first analog signal V _in to the respective comparator.

In one possible implementation, the replica comparator of the comparison module 402 has a reference voltage V _{c_r}, and the input first analog signal V _in is sampled/held, compared to the comparator's reference voltage V _{c_r}. When V _in≥V_{c_r}, the comparator output d _r =1; when V _in<V_{c_r}, the comparator output d _r =0. The replica comparator may compare the voltage value of the first analog signal with the reference voltage and output a 1-bit digital signal, i.e., the second digital signal D ₂.

In one possible implementation, the reference voltage of the replica comparator of the comparison module 402 may be the same as the j-th comparator of the N comparators of the SADC module 401, e.g., j is 4, and the reference voltage V _{c_r} of the replica comparator may be the same as the reference voltage V _c4 of the 4-th comparator of the SADC module 401.

In one possible implementation, the second adjusting unit 4021 is further input with a second control signal D _{ctrl_2}. The second control signal D _{ctrl_2} may include information indicating a degree of adjustment of the second clock skew, and the second adjustment unit 4021 may adjust the second clock skew of the comparison module 402, for example, by increasing or decreasing the number of inverters through which the clock signal CLK passes, based on the second control signal D _{ctrl_2}, so as to attempt to skew the comparator sampling time of the comparison module 402 in a direction more advantageous for compressing the MDAC output swing.

In one possible implementation, when the analog-to-digital conversion circuit starts to operate, an initial first control signal may be preset, and a first clock offset may be adjusted according to the preset initial first control signal, where the first clock offset may be different from the second clock offset of the comparison module 402. For example, the first clock offset may be set to 0, and the second clock offset may be set to a positive offset or a negative offset. Whether the second control signal is adjusted to adjust the second clock offset can be determined according to the output result of the comparison module 402 and the residual signal, and when the second clock offset needs to be adjusted, the adjusting direction of the second clock offset can be determined according to the adjusting result of the SADC module, so as to adjust and output the second control signal to determine whether the clock offset more beneficial to compressing the MDAC output swing is detected. The specific settings of the initial first control signal and the initial second control signal are not limited by the present disclosure.

In one possible implementation, the adjustment conditions of the control module 404 may further include: the j-th bit of the second digital signal D ₂ output by the comparison module 402 is different from the j-th bit of the first digital signal D ₁ output by the SADC module 401 (e.g., j may be taken as 4 when N is taken as 8).

In one possible implementation, the replica comparator of the comparison module 402 has the same reference voltage as the j-th stage comparator of the SADC module 401, and the first analog signal V _in input to the comparison modules 402 and SADC module 401 is also the same, so that, under the condition that all other conditions are the same, the j-th bit of the first digital signal D ₁ output by the j-th stage comparator of the replica comparator and the second digital signal D ₂ and SADC module is determined by the respective clock offsets of the comparison modules and SADC module. It will be appreciated by those skilled in the art that if the second digital signal D ₂ is different from the j-th bit of the first digital signal D ₁, the sample time offset of the comparing module and the SADC module may be considered to be large, and the control module 404 may be required to adjust the second clock offset of the comparing module 402 or the first clock offset of the SADC module 401 to correct the sample time offset of the analog-to-digital conversion circuit.

In this way, the residual signal can exceed a preset first voltage interval; and the second digital signal D ₂ is different from the j-th bit of the first digital signal D ₁, so as to ensure that the analog-to-digital conversion circuit is in a state of performance degradation caused by sampling time deviation, and reduce the probability of judgment errors.

In one possible implementation, the comparison module may further include a plurality of comparators, each comparator having a reference voltage that is the same as the reference voltage of any one of the SADC modules, the different comparator reference voltages of the comparison module being different. The input first analog signal is sampled/held, and compared with the reference voltage of each comparator, one bit of digital signal is output, and all the digital signals obtained by comparison, namely, the second digital signal D ₂ is output.

In one possible implementation, where the comparison module includes a plurality of comparators, the adjustment conditions of the control module 404 may further include: the second digital signal D ₂ output by the comparison module 402 is different from the corresponding signal bit of the first digital signal D ₁ output by the SADC module 401. For example, when the reference voltages of the 1 st comparator and the 2 nd comparator of the comparison module are the same as the 4 th comparator and the 5 th comparator of the SADC module, respectively, the 1 st and the 2 nd bits of the second digital signal D ₂ are considered to be corresponding signal bits respectively with the 4 th and the 5 th bits of the first digital signal D ₁, and when the corresponding signal bits are different, the sampling time offset difference between the comparison module and the SADC module is considered to be larger, and the control module is required to adjust the second clock offset of the comparison module or the first clock offset of the SADC module to correct the sampling time offset of the analog-digital conversion circuit.

By using a plurality of comparators for comparison in the comparison module, more information of the working parameters of the circuit can be obtained, and the correction precision is ensured.

In one possible implementation, the adjustment conditions of the analog-to-digital conversion circuit may include: the residual difference signal exceeds a preset first voltage interval; or the second digital signal D ₂ is different from the j-th bit of the first digital signal D ₁. That is, in the case where one of the above two conditions is satisfied, the adjustment can be started when the analog-to-digital conversion circuit may be deteriorated in performance, thereby improving the sensitivity of the circuit correction.

In one possible implementation, [ N/2] -1<j +.1 (e.g., N may be 8, then 3<j +. 5,j may take on at least one of 4, 5).

In one possible implementation, N is the total number of comparators included in SADC module 401, j is the number of jth comparators in SADC module 401, and the reference voltage of the duplicate comparator of comparison module 402 may be the same as the jth comparator in SADC module 401. By limiting the value range of j, the output result of the duplicate comparator is used as the comparison of the output result of the j-th comparator, so that the comparison can be more accurate.

In one possible implementation, the control module 404 determines the reference residual signal D _{res_r} of the comparison module 402 according to the first digital signal D ₁, the residual signal V _res, and the second digital signal D ₂, including:

The residual signal V _res in analog form is converted into the residual signal D _res in digital form. An equivalent input voltage D _in of the analog-to-digital conversion circuit is determined from the digital form of the residual signal D _res and the first digital signal D ₁.

The reference residual signal D _{res_r} is determined according to the equivalent input voltage D _in, the second digital signal D ₂, and the first digital signal D ₁.

For example, if the analog-to-digital conversion circuit satisfies the adjustment condition, the control module 404 may determine the reference residual signal D _{res_r} of the comparison module 402 according to the first digital signal D ₁ output by the SADC module 401, the residual signal V _res output by the MDAC module 403, and the second digital signal D ₂ output by the comparison module 402.

In one possible implementation, the residual signal V _res is an analog signal, and the first digital signal D ₁ and the second digital signal D ₂ are digital signals, so that the analog residual signal V _res may be converted into digital form and then calculated, for example, the analog-to-digital conversion of the residual signal V _res may be completed by the analog-to-digital conversion ADC unit in the control module 404 to obtain the digital result D _res of the residual signal V _res, and the specific manner adopted in the present disclosure for completing the digitization of the residual signal V _res is not limited.

In one possible implementation, the control module may calculate the equivalent input voltage D _in of the analog-to-digital conversion circuit based on the digital form of the residual signal D _res and the first digital signal D ₁. For example, as shown in equation 2, where G represents the present stage MDAC gain,

In one possible implementation, the control module may further obtain the reference digital signal D _{1_r} according to the second digital signal D ₂ and the first digital signal D ₁. The second digital signal may be output by a replica comparator of the comparison module, and the j-th bit of the first digital signal D ₁ may be replaced by the second digital signal D ₂, so as to obtain a reference digital signal D _{1_r} with the same number of bits as the first digital signal after replacement. The reference voltage of the replica comparator of the comparison module is the same as the reference voltage of the j-th comparator in the N comparators of the SADC modules.

In one possible implementation, in the case that the comparison module includes a plurality of comparators, each digital signal in the second digital signal D ₂ may be used to replace a digital signal of a corresponding signal bit in the first digital signal D ₁, so as to obtain a reference digital signal D _{1_r} having the same number of bits as the first digital signal D ₁ after being replaced.

In one possible implementation, the control module may calculate the reference residual voltage D _{res_r} based on the calculated equivalent input voltage D _in and the digital signal D _{1_r}, as shown in equation 3, where G represents the current stage MDAC gain,

D_{res_r}＝G·(D_in-D_{1_r}) (3)

In this way, the control module can determine the reference residual voltage of the analog-to-digital conversion circuit.

In one possible implementation, the control module 404 adjusts the first control signal D _{ctrl_1} or the second control signal D _{ctrl_2} according to a relationship between a residual signal and a reference residual signal, including:

In the case that the absolute value of the voltage of the residual signal is greater than the absolute value of the voltage of the reference residual signal, the first control signal D _{ctrl_1} is adjusted to control the first adjusting unit of the SADC module to adjust the first clock offset toward a direction approaching the second clock offset.

In one possible implementation, the control module may compare the absolute magnitudes of voltages of the digital form of the residual signal D _res and the reference residual signal D _{res_r} and output different control signals according to different comparison results.

In one possible implementation, the absolute voltage value of the residual signal and the absolute voltage value of the reference residual signal are related to the sample time offsets of SADC module 401 and comparison module 402, respectively, and if the absolute voltage value of the residual signal is greater, the sample time offset of SADC module 401 may be considered to be greater, and the first clock offset of SADC module 401 may be adjusted to approximate the second clock offset, which is less the sample time offset.

In one possible implementation, the control module may compare the absolute values of D _res and D _{res_r}, as shown in equation (4), and in the condition that the absolute value of the residual signal D _res is greater, the control module 404 may adjust the first control signal D _{ctrl_1} to control SADC the first adjusting unit 4011 to adjust the first clock offset toward the second clock offset.

|D_res__r|＜|D_res|(4)

In one possible implementation, the control module adjusts the first control signal D _{ctrl_1} or the second control signal D _{ctrl_2} according to a relationship between a residual signal and a reference residual signal, and further includes:

In the case where the absolute value of the voltage of the residual signal is smaller than the absolute value of the voltage of the reference residual signal, the second control signal D _{ctrl_2} is adjusted to control the comparison module second adjustment unit 4021 to adjust the second clock offset toward a direction approaching the first clock offset.

As one possible implementation, the control module may compare the absolute magnitudes of the voltages of the digital form of the residual signal D _res and the reference residual signal D _{res_r}, and if the absolute magnitude of the voltage of the reference residual signal is greater, the sample time offset of the comparison module 402 may be considered to be greater, and the second clock offset of the comparison module 402 may be adjusted to approximate the first clock offset having the smaller sample time offset.

In one possible implementation, as shown in equation (5), in the case where the absolute value of the reference residual signal D _{res_r} is greater, the control module 404 may adjust the second control signal D _{ctrl_2} to control the comparison module second adjustment unit 4021 to adjust the second clock offset toward a direction approaching the first clock offset.

|D_res__r|＞|D_res|(5)

In this way, the control module may output a control signal to adjust SADC the sampling time offset of the module or the comparison module, thereby completing the real-time correction process of the sampling time offset of the analog-to-digital conversion circuit.

In one possible implementation, after a comparison of D _res and D _{res_r}, the control module may control the SADC module or the comparison module to make a single adjustment in the amount of clock offset, and the comparison and adjustment may be performed multiple times when the adjustment condition is met until the residual signal is adjusted to within the preset first voltage interval. In this case, the control module may actively adjust the second control signal D _{ctrl_2} to search in a direction that increases or decreases the second clock offset to find a better clock offset, and if there is a better clock offset, may adjust the clock offset of the SADC module to the best clock offset that is probed, and compress the swing of the residual signal.

By the method, on the premise of correcting the sampling time deviation of the comparator, the signal swing of the residual difference signal output by the MDAC module can be further reduced, so that the linearity performance of the MDAC module is improved, and the performances of the whole assembly line analog-to-digital conversion circuit and the assembly line analog-to-digital converter are further improved.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are added in the circuit, signals output by the circuit are obtained through the control module, and under the condition that the output signals meet the regulation conditions, control signals are output to regulate the clock deviation of the SADC module or the comparison module. Compared with the scheme of the related technology, the method has the advantages that only the comparison module and the control module are added, noise is not added, the influence on power consumption is small, and the cost of an analog circuit is low; the time deviation error of the comparator can be tracked to change along with different environment temperatures and working voltages, so that the real-time correction of the analog-to-digital conversion circuit is realized, and the correction precision of the analog-to-digital conversion circuit is improved. The analog-to-digital conversion circuit according to the embodiment of the disclosure can be applied to MDAC modules of all stages of analog-to-digital conversion circuits of a pipeline ADC, and real-time correction is performed on all stages of analog-to-digital conversion circuits respectively.

There is also provided, in accordance with an embodiment of the present disclosure, a pipelined analog-to-digital converter including a multi-stage analog-to-digital conversion circuit, each stage of the analog-to-digital conversion circuit including an analog-to-digital conversion circuit as described above.

The specific manner in which the various blocks perform operations in relation to the pipelined analog-to-digital converter has been described in detail in relation to embodiments of the analog-to-digital conversion circuit and will not be described in detail herein.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog to digital conversion circuit, the circuit being a stage of a pipelined analog to digital converter, the circuit comprising: a sub-module-digital conversion SADC module, a digital-to-analog conversion and amplification MDAC module, a comparison module and a control module,

Wherein, the control module is used for:

2. The circuit of claim 1, wherein the SADC module includes a first conditioning unit and N comparators, the first digital signal including an N-bit digital signal, N being an integer greater than 1,

3. The circuit of claim 2, wherein the comparison module comprises a second adjustment unit and a replica comparator,

the replica comparator inputs the first analog signal and the second off-clock signal,

The reference voltage of the replica comparator is the same as the j-th comparator in the N comparators, the replica comparator is used for comparing the sampling voltage of the first analog signal with the reference voltage of the replica comparator, outputting a compared digital signal, j is an integer and 1< j < N,

4. The circuit of claim 3, wherein the conditioning conditions further comprise: the second digital signal is different from the j-th bit of the first digital signal.

5. The circuit of any of claims 1-4, wherein the control module determining the reference residual signal of the comparison module based on the first digital signal, the residual signal, and the second digital signal comprises:

6. The circuit of any of claims 2-4, wherein the control module adjusting the first control signal or the second control signal based on a relationship between the residual signal and the reference residual signal comprises:

7. The circuit of claim 3 or 4, wherein the control module adjusts the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal, further comprising:

8. The circuit of claim 3 or 4, wherein after the margin signal is adjusted to be within the first voltage interval, the control module is further configured to:

9. A circuit according to claim 3, wherein [ N/2] -1<j + [ N/2] +1.

10. A pipelined analog-to-digital converter comprising a plurality of stages of analog-to-digital conversion circuits, each stage of analog-to-digital conversion circuit comprising an analog-to-digital conversion circuit according to any one of claims 1 to 9.