CN114362752A

CN114362752A - Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Info

Publication number: CN114362752A
Application number: CN202011087957.6A
Authority: CN
Inventors: 杨培; 殷秀梅
Original assignee: Beijing Tebang Microelectronic Technology Co ltd
Current assignee: Beijing Tebang Microelectronic Technology Co ltd
Priority date: 2020-10-13
Filing date: 2020-10-13
Publication date: 2022-04-15
Anticipated expiration: 2040-10-13
Also published as: CN114362752B

Abstract

The present disclosure relates to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter, the circuit is a first stage of the pipeline analog-to-digital converter, and comprises: the system comprises an SADC module, a comparison module, an MDAC module and a control module, wherein the SADC module is used for converting an input analog signal into a digital signal; the MDAC module is used for outputting a residual signal of the analog signal and the digital signal; the control module is used for carrying out correction control. When the residual difference signal exceeds a preset first voltage interval, the control module judges that the circuit meets the regulation condition, and adjusts the first control signal and the second control signal to regulate the clock deviation of the SADC module or the comparison module so as to regulate the residual difference signal to be in the first voltage interval. According to the embodiment of the disclosure, the real-time correction of the sampling time deviation of the MDAC module and the SADC module in the pipeline analog-to-digital converter can be realized with less circuit cost, and the precision of the analog-to-digital conversion circuit is improved.

Description

Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter.

Background

The pipeline Analog-to-Digital Converter (ADC) is composed of several Analog-to-Digital conversion modules with similar functions, and each Analog-to-Digital conversion module includes a sub-Analog-to-Digital conversion (SADC) module, a Digital-to-Analog conversion and amplification (MDAC) module, and the like.

The precision of the pipeline ADC is closely related to the signal processing precision of the MDAC module, and the quantization result of the SADC module influences the signal processing precision of the MDAC module. For example, the sampling time offset of the comparator in the SADC module has a large influence on the accuracy of the MDAC module, and under normal conditions, the MDAC and the SADC sample the dynamic input signal of the ADC at the same time, the sampled signal voltages are consistent, and the absolute value of the MDAC residual voltage output amplitude should be half of the full-scale voltage of the ADC. Under the condition that sampling time deviation of the comparator exists, signal voltages obtained by MDAC and SADC sampling are inconsistent, namely the threshold value of the comparator changes, the output amplitude of MDAC residual difference voltage is increased, so that the performance of an MDAC module is deteriorated, and under the more serious condition, the absolute value of the residual difference voltage amplitude exceeds the full-amplitude voltage of the ADC, and the ADC loses codes. Therefore, in order to ensure the precision of the pipeline ADC, the sampling time deviation index of the comparator needs to be controlled within a certain range.

Disclosure of Invention

In view of this, the present disclosure provides an analog-to-digital conversion circuit, which can correct the sampling time deviation of a comparator in real time and improve the accuracy of the analog-to-digital conversion circuit at a low circuit cost when a pipeline analog-to-digital converter works.

According to an aspect of the present disclosure, there is provided an analog-to-digital conversion circuit, the circuit being a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-analog-to-digital conversion SADC module, an analog-to-digital conversion and amplification MDAC module, a comparison module and a control module,

a first input end of the SADC module inputs a clock signal, a second input end of the SADC module inputs a first control signal, a third input end of the SADC module inputs a first analog signal, and an output end of the SADC module outputs a first digital signal;

the first input end of the comparison module inputs the clock signal, the second input end of the comparison module inputs a second control signal, the third input end of the comparison module inputs the first analog signal, and the output end of the comparison module outputs a second digital signal;

the first input end of the MDAC module inputs the clock signal, the second input end of the MDAC module inputs the first analog signal, the third input end of the MDAC module inputs the first digital signal, and the output end of the MDAC module outputs a residual error signal;

the first input end of the control module inputs the first digital signal, the second input end of the control module inputs the second digital signal, the third input end of the control module inputs the residual error signal, and the output end of the control module outputs the first control signal and the second control signal,

wherein the control module is configured to:

judging whether the analog-to-digital conversion circuit meets an adjusting condition, wherein the adjusting condition comprises that the residual difference signal exceeds a preset first voltage interval;

determining a reference residual signal of the comparison module according to the first digital signal, the residual signal and the second digital signal under the condition that the analog-to-digital conversion circuit meets the regulation condition;

and adjusting the first control signal or the second control signal according to the relation between the residual difference signal and the reference residual difference signal, so that the residual difference signal is adjusted to be within the first voltage interval, wherein the first control signal is used for adjusting the clock deviation of the SADC module, and the second control signal is used for adjusting the clock deviation of the comparison module.

In one possible implementation, the SADC module includes a first adjusting unit and N comparators, the first digital signal includes an N-bit digital signal, N is an integer greater than 1,

the first adjusting unit is connected to the N comparators and used for adjusting the deviation amount of the clock signal and outputting a first deviation clock signal with a first clock deviation amount;

the N comparators input the first analog signal and the first deviation clock signal, an ith comparator of the N comparators is used for comparing a sampling voltage of the first analog signal with a reference voltage of the ith comparator and outputting an ith digital signal after comparison, i is an integer and is more than or equal to 1 and less than or equal to N,

wherein the first adjusting unit is further configured to: and adjusting the first clock offset according to the first control signal.

In one possible implementation, the comparison module comprises a second adjustment unit and a replica comparator,

the second adjusting unit is connected to the replica comparator, and is used for adjusting the deviation amount of the clock signal and outputting a second deviated clock signal with a second clock deviation amount;

the replica comparator inputs the first analog signal and the second off-clock signal, a reference voltage of the replica comparator is the same as a jth comparator of the N comparators, the replica comparator is configured to compare a sampling voltage of the first analog signal with the reference voltage of the replica comparator and output a compared digital signal, j is an integer and 1< j < N,

wherein the second adjustment unit is further configured to: and adjusting the second clock deviation amount according to the second control signal.

In one possible implementation, the adjusting condition further includes: the second digital signal is different from a jth bit of the first digital signal.

In a possible implementation manner, the determining, by the control module, the reference residual signal of the comparison module according to the first digital signal, the residual signal and the second digital signal includes:

converting the analog form of the residual signal into a digital form of the residual signal;

determining an equivalent input voltage of the analog-to-digital conversion circuit according to the digital residual signal and the first digital signal;

and determining the reference residual signal according to the equivalent input voltage, the second digital signal and the first digital signal.

In one possible implementation manner, the adjusting, by the control module, the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal includes:

and adjusting the first control signal to control a first adjusting unit of the SADC module to adjust the first clock deviation amount toward a direction approaching a second clock deviation amount, if the voltage absolute value of the residual signal is greater than the voltage absolute value of the reference residual signal.

In a possible implementation manner, the adjusting, by the control module, the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal further includes:

and under the condition that the voltage absolute value of the residual difference signal is smaller than the voltage absolute value of the reference residual difference signal, adjusting the second control signal to control a second adjusting unit of the comparison module to adjust the second clock deviation amount towards the direction close to the first clock deviation amount.

In one possible implementation, after the residual signal is adjusted to be within the first voltage interval, the method further includes:

and under the condition that the voltage absolute value of the residual difference signal is less than or equal to the voltage absolute value of the reference residual difference signal, adjusting the second control signal to control a second adjusting unit of the comparison module to adjust the second clock deviation amount towards the direction far away from the first clock deviation amount.

In one possible implementation, [ N/2] -1< j ≦ [ N/2] + 1.

According to another aspect of the present disclosure, a pipeline analog-to-digital converter is provided, which includes a plurality of stages of analog-to-digital conversion circuits, each stage of analog-to-digital conversion circuit including the above analog-to-digital conversion circuit.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are additionally arranged in the circuit, the control module is used for acquiring the signal output by the circuit, and outputting the control signal to adjust the clock deviation of the SADC module or the comparison module under the condition that the output signal meets the adjustment condition, so that the real-time correction of the analog-to-digital conversion circuit is realized with less circuit cost, and the correction precision of the analog-to-digital conversion circuit is improved.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a one-stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art.

Fig. 2a and 2b illustrate a circuit configuration diagram of an MDAC module of an analog-to-digital conversion circuit according to the related art and a schematic diagram of a circuit timing thereof, respectively.

Fig. 3 illustrates a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 4 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

Fig. 5 illustrates a block diagram of an SADC module according to an embodiment of the present disclosure.

Fig. 6 shows a block diagram of a comparator according to an embodiment of the present disclosure.

FIG. 7 shows a block diagram of a comparison module according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 is a schematic diagram of a one-stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art. For example, the pipelined ADC may include several stages of analog-to-digital conversion circuits with similar functions, as shown in fig. 1, an analog-to-digital conversion circuit 10 according to the related art may include:

a sub-analog-to-digital conversion (SADC) module 101, a clock signal CLK being input to a first input terminal of the SADC module 101₀The second input end inputs an analog signal V_in0The output end outputs a digital signal D after analog-to-digital conversion₀₁(ii) a Wherein if the first stage analog-to-digital conversion circuit is not adopted, V_in0Is an analog signal provided by a former-stage analog-to-digital conversion circuit;

in one possible implementation, as shown in fig. 1, the SADC module 101 may include a plurality of comparators (e.g., 8 comparators), a sampling path of the plurality of comparators includes a sample-and-hold (S/H), and a first input terminal of the sample-and-hold inputs the clock signal CLK₀The second input end inputs an analog signal V_in0The output end outputs the analog signal V after sampling and holding_in0To the respective comparators; the f-th comparator of the plurality of comparators may have a reference voltage V_c0f(f is not less than 1 and not more than the number of comparators), V_c0fThe value of (c) may be different depending on the value of f (e.g., the reference voltage of the 1 st comparator may be V_c01). Each comparator converts the analog signal V_in0Comparing the voltage value with respective reference voltage to output a one-bit digital signal; until all comparators have finished the analog signal V_in0The voltage value of the digital signal D is compared with the reference voltage to form a digital signal D according to the number sequence of the comparators₀₁。

A digital-to-analog conversion and amplification (MDAC) module 102, the MDAC module 102 being connected to the SADC module 101, a first input terminal of which is inputted with a clock signal CLK₀The second input end inputs an analog signal V_in0A third input terminal for inputting a digital signal D₀₁And the output end outputs a residual difference signal V_res0。

In one possible implementation, as shown in fig. 1, the MDAC module 102 may include a sample-and-hold (S/H), a digital-to-analog converter (DAC), an adder, and a gain unit including an operational amplifier (OPA). The first input terminal of the sample-and-hold unit is inputted with a clock signal CLK₀The second input end inputs an analog signal V_in0The output end outputs the analog signal V after sampling and holding_in0To the adder; digital signal D is input to the input end of DAC₀₁The output end of the adder is connected with one input end of the adder; the other input end of the adder inputs the analog signal V after sampling and holding_in0The output end of the voltage value is connected with the input end of the gain unit; the output end of the gain unit outputs a residual signal V_res0。

For example, the clock signal CLK₀And an analog signal V_in0Simultaneously entering the SADC module 101 and the MDAC module 102, a coarse quantization (i.e., a preliminary analog-to-digital conversion) is performed in the SADC module 101, for example, 1-4 bits are quantized, and a quantization result (digital signal D) is obtained₀₁) Into the MDAC module 102. MDAC module 102 converts the output of SADC module 101 into different reference voltages, analog signals V_in0After subtracting, the signal is amplified by a gain unit to obtain a residual signal V_res0And sending to the next stage for treatment.

Fig. 2a and 2b are schematic diagrams of a circuit structure of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing thereof, respectively. Fig. 3 is a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 2a shows an exemplary circuit structure of the MDAC module 102, and fig. 2b shows a clock signal of the MDAC module shown in fig. 2 a. The clock signal may comprise two inverted clocks Φ₁And phi₂Wherein T is_clkIndicating the period of the system clock, C_S,1-C_S,mRepresenting the sampling capacitance, m representing the number of sampling capacitances, C_stg2Representing the sampling capacitance of the second stage, C_FRepresenting the feedback capacitance, V_rpAnd V_rnRespectively representing a positive reference voltage and a negative reference voltage.

In one possible implementation, as shown in FIG. 2a, at Φ₁Phase (e.g. phi)₁1/2 clock period T being high_clk)，V_in0Is sampled into each sampling capacitor C_S,1-C_S,mIn (1). End of sample (e.g., #)₁Low) is phi₁The respective switches are turned off. Phi₂Phase (e.g. phi)₂1/2 clock period T being high_clk) The switch is closed, at which time each capacitor C_S,1-C_S,mThe voltage of the lower plate is controlled by the output signal of the SADC module 101, and V connection is selected according to the output signal (quantization result) of the SADC module 101_rpOr V_rnThe digital-to-analog conversion in MDAC is thus achieved, resulting in the transmission curve shown in fig. 3. The OPA works in a closed loop negative feedback state, and according to the charge conservation and the working principle of the ideal OPA, the following can be obtained:

in the formula (1), V_res0Representing the residual signal, V, output by the MDAC module 102_in0Representing an input analogue signal, d_0fDigital signal D representing SADC module 101₀₁F position of (d)_0fIs in the value range of [0, 1 ]]，C_S,fRepresents the capacitance value of the f-th sampling capacitor, f is an integer between 1 and m, C_FRepresenting the capacitance value, V, of the feedback capacitor_ref0Representing the full-scale voltage of the pipeline ADC, the input signal range of the pipeline ADC should be [ -V ]_ref0，V_ref0]Within the range of (1).

The MDAC module 102 and the SADC module 101 pair the analog signal V, as shown in FIG. 3, with the transmission curve of FIG. 3, the ideal transmission curve being shown as the solid line_in0Simultaneously, sampling is carried out, the sampled signal voltages are consistent, and the MDAC residual voltage output amplitude is +/-0.5V_ref0Nearby. When there is a deviation of the sampling time of the comparator, the signal voltages sampled by the MDAC module 102 and the SADC module 101 are not consistent, which corresponds to a change in the threshold of the comparator. The transmission characteristic curve is shifted as shown by the dotted line, and a residual signal V is generated_res0The output amplitude increases, which degrades the performance of the MDAC module 102 and, in more severe cases, the residual signal V_res0Amplitude exceeding + -V_ref0The ADC is missing code. In order to ensure the ADC precision, the sampling deviation index of the comparator needs to be controlled within a certain range.

In the related art, a sample hold circuit is usually added to the front end of the ADC, or the error of the sampling time deviation of the comparator is corrected when the ADC is not operating. However, the method of adding the sample-and-hold circuit to the front end of the ADC significantly increases the cost of the analog circuit, increases power consumption, noise, and the like. When the ADC does not work, the sampling time deviation error of the comparator is corrected, because the correction is not real-time, the change of the time deviation error of the comparator along with different environmental temperatures and working voltages cannot be tracked, and the correction precision is limited.

Fig. 4 shows a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure. This circuit 40 is any stage of a pipelined ADC. As shown in fig. 4, the circuit 40 includes: a sub analog to digital conversion SADC module 401, a comparison module 402, a digital to analog conversion and amplification MDAC module 403 and a control module 404,

the sub-ADC module 401 has a first input terminal for inputting the clock signal CLK and a second input terminal for inputting the first control signal D_{ctrl_1}The third input end inputs the first analog signal V_inThe output end outputs a first digital signal D₁；

The comparing module 402 has a first input terminal for inputting the clock signal CLK and a second input terminal for inputting the second control signal D_{ctrl_2}The third input end inputs the first analog signal V_inThe output end outputs a second digital signal D₂；

The first input terminal of the DAC and MDAC module 403 inputs the clock signal CLK, and the second input terminal inputs the first analog signal V_inThe third input end inputs the first digital signal D₁And the output end outputs a residual difference signal V_res；

The first digital signal D is input to the first input terminal of the control module 404₁A second digital signal D is input to the second input terminal₂The third input end inputs residual difference signal V_resThe output end outputs a first control signal D_{ctrl_1}And a second control signal D_{ctrl_2}，

Wherein the control module 404 is configured to:

judging whether the analog-to-digital conversion circuit 40 meets the regulation condition, wherein the regulation condition comprises that the residual difference signal exceeds a preset first voltage interval;

according to the first digital signal D in the case that the analog-to-digital conversion circuit satisfies the regulation condition₁Residual signal V_resAnd a second digital signal D₂Determining a reference residual signal D of the comparison module_{res_r}；

Adjusting the first control signal D according to the relation between the residual signal and the reference residual signal_{ctrl_1}Or the second control signal D_{ctrl_2}So that the residual signal is adjusted to be within a first voltage interval, a first control signal D_{ctrl_1}For adjusting the clock offset of the SADC module 401, a second control signal D_{ctrl_2}For adjusting the clock skew amount of the comparing module.

For example, the MDAC module 403 may adopt a related art circuit structure. The SADC module 401 may include a plurality of comparators for quantizing an input first analog signal and outputting a quantized multi-bit digital signal (i.e., a first digital signal). Each comparator of the SADC module has a reference voltage, for example, the reference voltage of the 1 st comparator can be V_c1And (4) showing. The comparing module 402 may include at least one comparator having a structure identical to that of the comparator of the SADC module 401, and the comparing module 402 inputs the first analog signal and outputs the quantized at least one-bit digital signal (i.e., the second digital signal). At least one comparator of the comparison module 402 has a reference voltage, e.g. the reference voltage of the 1 st comparator may be V_{c_1}And (4) showing. The SADC module 401 and the comparison module 402 each comprise a sample-and-hold (S/H) for a first analog signal V according to a clock signal CLK_inSampling and outputting a first analog signal V subjected to sampling and holding_inTo the respective comparators.

In one possible implementation, an adjusting unit may be added before the sample holders of the SADC module 401 and the comparison module 402, and different clock offset amounts are set for the SADC module 401 and the comparison module 402, respectively, so as to correct the analog-to-digital conversion circuit by adjusting the clock offset amounts when the accuracy of the analog-to-digital conversion circuit is degraded. Wherein, the adjusting unit may for example comprise a plurality of inverters connected in series, and the present disclosure does not limit the specific structure of the adjusting unit.

In one possible implementation, the clock signal CLK and the first analog signal V are used during the operation of the analog-to-digital conversion circuit_inSimultaneously into the SADC module 401, the comparison module 402, and the MDAC module 403. The SADC module 401 and the comparison module 402 complete the conversion of the analog-digital signal to obtain the first digital signal D respectively₁And a second digital signal D₂. First digital signal D output by SADC module 401₁Input into MDAC module 403, processed by MDAC module 403, and output residual signal V_resAnd sending the data to the next-stage analog-to-digital conversion circuit for processing.

In a possible implementation manner, the analog-to-digital conversion circuit 40 may further be provided with a control module 404 for implementing a correction control of the analog-to-digital conversion circuit. During operation of the analog-to-digital conversion circuit 40, the control module 404 may obtain a plurality of signals output by the circuit, including the first digital signal D₁A second digital signal D₂Sum and residual signal V_resAnd determines whether the analog-to-digital conversion circuit 40 satisfies the adjustment condition based on at least one of these signals.

In one possible implementation, the adjustment condition may include that the residual signal exceeds a preset first voltage interval. That is, if the residual difference signal exceeds the preset first voltage interval, the sampling time deviation error of the comparator is considered to be large, the MDAC performance is deteriorated, and adjustment is required. Wherein the first voltage interval can be based on the reference voltage V of the analog-to-digital conversion circuit_refAnd circuit arrangements, e.g. the first voltage interval can be set to [ - (1/2) V_ref，(1/2)V_ref]The specific value of the first voltage interval is not limited in this disclosure.

In a possible implementation, the adjustment condition may also adopt other conditions, for example, in the second digital signal D₂And a first digital signal D₁Judging that the adjusting condition is met when the corresponding signal positions are different; the adjustment condition may also be that at least one of a plurality of conditions is satisfied. It should be understood that the adjusting conditions of the analog-to-digital conversion circuit can be set by those skilled in the art according to actual conditions, and the present disclosure is directed toThis is not limiting.

In one possible implementation, in a case where the analog-to-digital conversion circuit satisfies the adjustment condition, the control module 404 may output an initial first control signal and an initial second control signal, so that the SADC module 401 and the comparison module 402 have different clock skew amounts. The control module can be used for controlling the output according to the first digital signal D₁A second digital signal D₂And reference residual signal D of residual signal calculation and comparison module_{res_r}(ii) a Judging residual difference signal and reference residual difference signal D obtained by calculation_{res_r}The relation between the first control signal D and the second control signal D is selected and adjusted to output the first control signal D_{ctrl_1}To adjust the clock offset of the SADC module 401 or to selectively adjust the output of the second control signal D_{ctrl_2}To adjust the amount of clock skew of the comparison module 402.

In one possible implementation, if the voltage absolute value of the residual signal is greater than the voltage absolute value of the reference residual signal, the clock bias error of the SADC module 401 may be considered to be large, and the control module may adjust to output the first control signal D_{ctrl_1}To adjust the clock offset of the SADC module 401; on the contrary, if the voltage absolute value of the reference residual signal is greater than the voltage absolute value of the residual signal, the clock deviation error of the comparing module 402 is considered to be larger, and the control module can adjust and output the second control signal D_{ctrl_2}To adjust the amount of clock skew of the comparison module 402.

In a possible implementation, the first control signal D_{ctrl_1}And a second control signal D_{ctrl_2}For an adjustable control signal, comprising information indicating the way of adjustment of the clock skew, upon receiving the control signal, the SADC module 401 or the comparison module 402 may implement the adjustment of the clock skew, for example by changing the number of inverters through which the clock signal CLK passes in the adjustment unit. The present disclosure is not limited to a particular manner of adjustment.

In a possible implementation manner, through multiple times of adjustment, if the residual difference signal is adjusted to be within the first voltage interval, it can be considered that the sampling time deviation error of the comparator is within the range allowed by the precision, the MDAC module can meet the performance requirement, and the control module can end the adjustment process this time.

In a possible implementation manner, after the control module controls the clock offset of the SADC module 401 to perform one or more times of adjustment, the residual signal may be adjusted to a preset first voltage interval, in this case, if the voltage absolute value of the residual signal is less than or equal to the voltage absolute value of the reference residual signal, the control module may adjust the second control signal D for the purpose of further compressing the amplitude of the residual signal_{ctrl_2}And searching for a more appropriate clock deviation amount in the direction of increasing or decreasing the second clock deviation amount to find out whether the effect of compressing the signal swing of the residual signal can be achieved. If an adjustment D is found during the trial_{ctrl_2}The swing amplitude of the residual signal is reduced, and the control module can control the first control signal D_{ctrl_1}Towards the second control signal D_{ctrl_2}To reduce the output swing of the MDAC module 403.

In one possible implementation, noise may be present in the circuit, having some effect on the magnitude of the residual signal and the reference residual signal. After the relationship between the residual signal and the reference residual signal is determined for multiple times, how to adjust the first control signal or the second control signal to adjust the clock offset of the SADC module 401 or the comparison module 402 is determined, so that the influence of noise on the circuit is reduced, and the correction accuracy is ensured.

According to the analog-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are additionally arranged in the circuit, the control module is used for acquiring the signal output by the circuit, and outputting the control signal to adjust the clock deviation of the SADC module or the comparison module under the condition that the output signal meets the adjustment condition, so that the real-time correction of the sampling time deviation of the MDAC module and the SADC module in the analog-digital conversion circuit is realized with less circuit cost, and the precision of the analog-digital conversion circuit is improved.

Fig. 5 illustrates a schematic structural diagram of an SADC module according to an embodiment of the present disclosure. As shown in fig. 5, in one possible implementation, the SADC module 401 may include a first adjusting unit 4011 and N comparators (e.g., 8 comparators), where the first digital signal includes an N-bit digital signal, N is an integer greater than 1,

the first adjusting unit 4011 is connected to the N comparators, and is configured to adjust an offset amount of the clock signal and output a first offset clock signal having a first clock offset amount;

n comparators input a first analog signal V_inAnd a first off-clock signal, an ith comparator of the N comparators being operable to provide the first analog signal V_inAnd the reference voltage V of the ith comparator_ciComparing and outputting the ith digital signal after comparison, wherein i is an integer and is more than or equal to 1 and less than or equal to N,

wherein, the first adjusting unit 4011 is further configured to: according to the first control signal D_{ctrl_1}The first clock offset is adjusted.

For example, the first adjusting unit 4011 may be disposed in a sampling path of the SADC module 401, placed before a sample holder (S/H) of N comparators, and the clock signal CLK is input to the first adjusting unit 4011, and outputs a first deviated clock signal having a first clock deviation amount. Here, the first adjusting unit 4011 may include a plurality of inverters connected in series, for example.

In a possible implementation manner, when the analog-to-digital conversion circuit starts to operate, an initial first control signal may be preset, a first clock offset amount may be obtained by adjusting according to the preset initial first control signal, and the clock signal CLK may pass through a preset number of inverters, for example, to obtain a first offset clock signal having the first clock offset amount.

In one possible implementation, the sample-and-hold unit of the N comparators can compare the first analog signal V with the first off-clock signal_inSampling is performed, and the voltage value of the sampled and held first analog signal is output to each comparator.

Fig. 6 shows a schematic structural diagram of a comparator according to an embodiment of the present disclosure. FIG. 6 shows an input of a first analog signal V to any one of the comparators, as shown in FIG. 6_inSampled/held with reference voltage V of the comparator_cBy comparison, when V_in≥V_cComparatorOutput D₀1 is ═ 1; when V is_in<V_c

Comparator output D

₀0. Thus, after the comparison by the N comparators, the SADC module 401 outputs an N-bit digital signal, i.e., the first digital signal D₁Thereby realizing the quantization of the analog signal.

In one possible implementation, the ith comparator of the SADC module 401 has a reference voltage V_ci(for example, the 1 st comparator has a reference voltage V_c1) Can be derived from the reference voltage V of the analog-to-digital conversion circuit_refFor example, when the number of comparators of the SADC module 401 is 8, the reference voltages of the 1 st comparator to the 8 th comparator may be: -7/8V_ref，-5/8V_ref，-3/8V_ref，-1/8V_ref，1/8V_ref，3/8V_ref，5/8V_ref，7/8V_ref. The N comparators may compare the voltage value of the first analog signal with respective reference voltages, output an N-bit digital signal (e.g., if N is 8, i is 3, then the 3 rd comparator may output a 3 rd-bit digital signal, and the 8 comparators may output 8-bit digital signals in total), sort the N-bit digital signals by bit, and obtain a first digital signal D₁。

In one possible implementation, N +1 comparison results output by N comparators are possible, for example, 9 comparison results output by 8 comparators are possible, as shown in table 1:

TABLE 1

In Table 1, d_iDigital signal D representing SADC module 401₁I th position of (d)_iIs in the value range of [0, 1 ]]，D_1，kRepresenting the possible kth output result, 1 ≦ i ≦ N, 1 ≦ k ≦ N + 1.

In one possible implementation, the SADC module can quantize g bits of data, where g is related to the number of possible output results of the comparator in the SADC module 401, and g can satisfy N +1 ≦ 2^gIs measured. For exampleAnd the possible output results of 8 comparators are 9, g can be 4, and the SADC module quantizes 4 bits. That is, the four-bit digital signal is finally output to an external circuit.

In a possible implementation manner, the first adjusting unit 4011 further inputs a first control signal D_{ctrl_1}. First control signal D_{ctrl_1}May include information indicating an adjustment degree of the first clock deviation amount, and the first adjustment unit 4011 may adjust the first clock deviation amount according to the first control signal D_{ctrl_1}The first clock offset of the SADC module 401 is adjusted, for example, the number of inverters through which the clock signal CLK passes is increased or decreased, so that the comparator sampling time offset error of the SADC module 401 is reduced, and the performance of the MDAC module is improved.

In a possible implementation manner, when the analog-to-digital conversion circuit starts to operate, an initial second control signal may be preset, and a second clock offset may be obtained by adjusting according to the preset initial second control signal, where the second clock offset may be different from the first clock offset of the SADC module 401. For example, the first clock offset amount may be made 0, and the second clock offset amount may be made a positive offset amount or a negative offset amount. Whether the first control signal is adjusted to adjust the first clock deviation can be judged according to the output result of the SADC module and the residual signal, when the first clock deviation needs to be adjusted, the adjusting direction of the first clock deviation can be judged according to the output result of the comparison module, and therefore the first control signal D is adjusted and output_{ctrl_1}To reduce the error in the deviation of the comparator sample time from the MDAC sample time. The present disclosure is not limited to a specific setting of the initial first control signal and the initial second control signal.

In this way, the SADC module with adjustable clock deviation is realized, so that the real-time correction of the sampling time deviation of the MDAC module and the SADC module of the analog-digital conversion circuit can be realized with less circuit cost.

FIG. 7 shows a block diagram of a comparison module according to an embodiment of the present disclosure. In one possible implementation, the comparing module 402 may include a second adjusting unit 4021 and a replica comparator,

the second adjusting unit 4021 is connected to the replica comparator, and is operable to adjust an offset amount of the clock signal and output a second offset clock signal having a second clock offset amount;

the first analog signal V is input by a replica comparator_inAnd a second off-clock signal, the reference voltage of the replica comparator being the same as the jth comparator of the N comparators, the replica comparator being for the first analog signal V_inComparing the sampled voltage with a reference voltage of a replica comparator, and outputting a compared digital signal, j being an integer and 1<j<N，

Wherein, the second adjusting unit 4021 is further configured to: according to a second control signal D_{ctrl_2}And adjusting the second clock offset.

For example, the second adjusting unit 4021 may be disposed in a sampling path of the comparing module 402, placed before a sample holder (S/H) of the replica comparator, and the clock signal CLK is input into the second adjusting unit 4021 and outputs a second deviated clock signal having a second clock deviation amount. The second adjusting unit 4021 may include a plurality of inverters connected in series, for example.

In a possible implementation manner, when the analog-to-digital conversion circuit starts to operate, an initial second control signal may be preset, a second clock offset may be obtained by adjusting according to the preset initial second control signal, and the clock signal CLK may be passed through a preset number of inverters, for example, to obtain a second offset clock signal with the second clock offset.

In a possible implementation, the sample holder of the replica comparator can be used to compare the first analog signal V with the second off-clock signal_inSampling and outputting a first analog signal V subjected to sampling and holding_inTo the respective comparators.

In one possible implementation, the replica comparator of the comparison module 402 has a reference voltage V_{c_r}Input first analog signal V_inSampled/held and compared with reference voltage V of comparator_{c_r}And (6) comparing. When V is_in≥V_{c_r}Output d of comparator _r1 is ═ 1; when V is_in<V_{c_r}Output d of comparator _r0. The replica comparator can compare the voltage value of the first analog signal with a reference voltage and output a 1-bit digital signal, i.e., a second digital signal D₂。

In one possible implementation, the reference voltage of the replica comparator of the comparison module 402 may be the same as the jth comparator of the N comparators of the SADC module 401, for example, if j takes 4, then the reference voltage V of the replica comparator is obtained_{c_r}Can be compared with the reference voltage V of the 4 th comparator of the SADC module 401_c4The same is true.

In a possible implementation manner, the second adjusting unit 4021 further inputs a second control signal D_{ctrl_2}. Second control signal D_{ctrl_2}May include information indicating the degree of adjustment of the second clock skew amount, and the second adjustment unit 4021 may adjust the second clock skew amount according to the second control signal D_{ctrl_2}Adjusting the second clock offset of the comparison module 402, for example, increasing or decreasing the number of inverters through which the clock signal CLK passes, attempts to offset the comparator sample time of the comparison module 402 in a direction that is more favorable for compressing the MDAC output swing.

In a possible implementation manner, when the analog-to-digital conversion circuit starts to operate, an initial first control signal may be preset, and a first clock offset may be obtained by adjusting according to the preset initial first control signal, where the first clock offset may be different from a second clock offset of the comparison module 402. For example, the first clock offset amount may be made 0, and the second clock offset amount may be made a positive offset amount or a negative offset amount. Whether the second control signal is adjusted to adjust the second clock skew can be judged according to the output result of the comparison module 402 and the residual difference signal, and when the second clock skew needs to be adjusted, the adjustment direction of the second clock skew can be judged according to the adjustment result of the SADC module, so that whether the clock skew which is more beneficial to compressing MDAC output swing exists or not is determined by adjusting the output second control signal. The present disclosure is not limited to a specific setting of the initial first control signal and the initial second control signal.

In a possible implementationThe adjustment conditions of the control module 404 may further include: the second digital signal D output by the comparing module 402₂And the first digital signal D output by the SADC module 401₁Is different (e.g., j may take 4 when N takes 8).

In one possible implementation, the replica comparator of the comparison module 402 and the jth comparator of the SADC module 401 have the same reference voltage, and the first analog signal V input to the comparison module 402 and the SADC module 401_inThe same applies, and therefore, the second digital signal D output by the comparator is duplicated under otherwise identical conditions₂And a first digital signal D output by a j stage comparator of the SADC module₁Is determined by the respective clock offsets of the comparison module and the SADC module. It will be appreciated by those skilled in the art that if the second digital signal D is a digital signal₂And a first digital signal D₁The j-th bit of the analog-to-digital conversion circuit is different from the j-th bit of the analog-to-digital conversion circuit, it can be considered that the difference between the sampling time offsets of the comparison module and the SADC module is large, and the control module 404 is required to adjust the second clock offset of the comparison module 402 or the first clock offset of the SADC module 401 to correct the sampling time offset of the analog-to-digital conversion circuit.

In this way, when the residual difference signal exceeds a preset first voltage interval; and a second digital signal D₂And a first digital signal D₁The j-th bit of the analog-to-digital conversion circuit is different, so that the analog-to-digital conversion circuit is ensured to be in a state of performance deterioration caused by sampling time deviation, and the probability of judgment error can be reduced.

In a possible implementation manner, the comparison module may further include a plurality of comparators, each comparator has a reference voltage which is the same as that of any one comparator in the SADC module, and reference voltages of different comparators of the comparison module are different. The input first analog signal is sampled/held, compared with the reference voltage of each comparator, and then one-bit digital signal is output, and all the digital signals obtained by comparison, namely the second digital signal D, are output₂。

In a possible implementation, in the case where the comparison module comprises a plurality of comparators, the control moduleThe adjustment conditions of 404 may further include: the second digital signal D output by the comparing module 402₂And the first digital signal D output by the SADC module 401₁The corresponding signal bits of (a) are different. For example, when the reference voltages of the 1 st comparator and the 2 nd comparator of the comparison module are the same as the 4 th comparator and the 5 th comparator of the SADC module, respectively, the second digital signal D is considered to be₂Respectively with the first digital signal D₁The 4 th and 5 th bits of the analog-to-digital conversion circuit are corresponding signal bits, and when the corresponding signal bits are different, the difference between the sampling time offsets of the comparison module and the SADC module is considered to be large, and the control module is required to adjust the second clock offset of the comparison module or the first clock offset of the SADC module to correct the sampling time offset of the analog-to-digital conversion circuit.

By using a plurality of comparators for comparison in the comparison module, more information of the working parameters of the circuit can be obtained, and the correction precision is ensured.

In one possible implementation, the adjustment condition of the analog-to-digital conversion circuit may include: the residual difference signal exceeds a preset first voltage interval; or the second digital signal D₂And a first digital signal D₁Is different from the j-th bit. That is, it is possible to start the adjustment when the analog-to-digital conversion circuit may suffer performance deterioration in the case where one of the above-described two conditions is satisfied, thereby improving the sensitivity of the circuit correction.

In one possible implementation, [ N/2] -1< j ≦ [ N/2] +1 (e.g., N may be 8, then 3< j ≦ 5, and j may take on at least one of the values 4, 5).

In one possible implementation, N is the total number of comparators included in the SADC module 401, j is the number of jth comparators in the SADC module 401, and the reference voltage of the replica comparator of the comparison module 402 may be the same as the jth comparator in the SADC module 401. By limiting the value range of j, the output result of the duplicate comparator is used as the comparison of the output result of the jth comparator, and the comparison can be more accurate.

In one possible implementation, the control module 404 is configured to control the first digital signal D according to the first digital signal D₁Residual signal V_resAnd a second digital signal D₂Determining a reference residual signal D of the comparison module 402_{res_r}The method comprises the following steps:

the residual signal V in analog form_resResidual signal D converted into digital form_res. From a digital form of the residual signal D_resAnd the first digital signal D₁Determining an equivalent input voltage D of the analog-to-digital conversion circuit_in。

According to the equivalent input voltage D_inThe second digital signal D₂And the first digital signal D₁Determining the reference residual signal D_{res_r}。

For example, the control module 404 may output the first digital signal D according to the SADC module 401 in case the analog-to-digital conversion circuit satisfies the regulation condition₁And residual difference signal V output by MDAC module 403_resAnd the second digital signal D output by the comparing module 402₂Determining a reference residual signal D of the comparison module 402_{res_r}。

In a possible implementation, the residual signal V_resIs a signal in analog form, a first digital signal D₁A second digital signal D₂Are all signals in digital form, so that the residual signal V in analog form can be used_resConverted to digital form and then calculated, e.g., residual signal V may be accomplished by an analog-to-digital converter (ADC) unit in control block 404_resTo obtain a residual signal V_resDigitized result D of_resThe present disclosure is directed to a completion residual signal V_resThe particular manner in which the digitization of (a) is performed is not limiting.

In a possible implementation, the control module may be based on the residual signal D in digital form_resAnd a first digital signal D₁Calculating an equivalent input voltage D of the analog-to-digital conversion circuit_in. For example, as shown in equation 2, where G represents the present stage MDAC gain,

in a possible implementation manner, the control module may also be based on the second digital signal D₂And a first digital signal D₁Obtaining a reference digital signal D_{1_r}. The second digital signal can be output by a replica comparator of the comparison module, and can be used as the second digital signal D₂Replacing the first digital signal D₁The j-th bit of the first digital signal, and obtaining the replaced reference digital signal D with the same number of bits as the first digital signal_{1_r}. And the reference voltage of the duplicate comparator of the comparison module is the same as the reference voltage of the jth comparator in the N comparators of the SADC module.

In a possible implementation, in the case where the comparison module comprises a plurality of comparators, the second digital signal D may be used₂Respectively replacing the first digital signal D with the digital signal of each bit₁To obtain the replaced and first digital signal D₁Reference digital signal D with the same number of bits_{1_r}。

In one possible implementation, the control module may calculate the equivalent input voltage D_inAnd a digital signal D_{1_r}Calculating a reference residual voltage D_{res_r}As shown in equation 3, where G represents the MDAC gain of this stage,

D_{res_r}＝G·(D_in-D_{1_r}) (3)

in this way, the control module can determine a reference residual voltage of the analog-to-digital conversion circuit.

In one possible implementation manner, the control module 404 adjusts the first control signal D according to a relationship between a residual signal and a reference residual signal_{ctrl_1}Or the second control signal D_{ctrl_2}The method comprises the following steps:

adjusting the first control signal D when the voltage absolute value of the residual signal is greater than the voltage absolute value of a reference residual signal_{ctrl_1}To control a first adjusting unit of the SADC module to adjust the first clock offset amount toward a direction approaching a second clock offset amount.

In a possible implementation, the control module may compare the residual signal D in digital form_resAnd a reference residual signal D_{res_r}And outputs different control signals according to different comparison results.

In one possible implementation, the voltage absolute value of the residual signal and the voltage absolute value of the reference residual signal are related to the sampling time offsets of the SADC module 401 and the comparison module 402, respectively, if the voltage absolute value of the residual signal is larger, the sampling time offset of the SADC module 401 can be considered to be larger, and the first clock offset of the SADC module 401 can be adjusted to approach the second clock offset with the smaller sampling time offset.

In one possible implementation, the control module may control D_resAnd D_{res_r}Is compared with the absolute value of (D), as shown in equation (4), in the residual signal D_resThe control module 404 may adjust the first control signal D under the condition that the absolute value of the first control signal D is larger_{ctrl_1}The SADC module first adjustment unit 4011 is controlled to adjust the first clock offset amount in a direction approaching the second clock offset amount.

|D_res__r|＜|D_res|(4)

In one possible implementation, the control module adjusts the first control signal D according to a relationship between a residual signal and a reference residual signal_{ctrl_1}Or the second control signal D_{ctrl_2}The method also comprises the following steps:

adjusting the second control signal D when the voltage absolute value of the residual signal is less than the voltage absolute value of the reference residual signal_{ctrl_2}To control the comparing module second adjusting unit 4021 to adjust the second clock offset amount in a direction approaching the first clock offset amount.

As in one possible implementation, the control module may compare the residual signal D in digital form_resAnd a reference residual signal D_{res_r}If the absolute value of the voltage of the reference residual signal is larger, the sampling time of the comparison module 402 may be considered to be deviated fromThe amount is also greater and the second clock offset of the comparison module 402 may be adjusted to approximate the first clock offset, which is less in offset of the sample time.

In one possible implementation, as shown in equation (5), the residual signal D is referred to_{res_r}In the case of larger absolute value, the control module 404 may adjust the second control signal D_{ctrl_2}The comparison module second adjustment unit 4021 is controlled to adjust the second clock deviation amount in a direction approaching the first clock deviation amount.

|D_res__r|＞|D_res|(5)

In this way, the control module can output a control signal to adjust the sampling time deviation of the SADC module or the comparison module, so as to complete the real-time correction process of the sampling time deviation of the analog-digital conversion circuit.

In one possible implementation, D_resAnd D_{res_r}After the first comparison, the control module can control the clock deviation amount of the SADC module or the comparison module to make a first adjustment, and when the adjustment condition is met, the comparison and the adjustment can be carried out for multiple times until the residual error signal is adjusted to be within a preset first voltage interval. In this case, the control module can actively adjust the second control signal D_{ctrl_2}Searching in the direction of increasing or decreasing the second clock deviation amount to find a better clock deviation amount, and if the better clock deviation amount exists, adjusting the clock deviation amount of the SADC module to the tested optimal clock deviation amount and compressing the swing of the residual error signal.

By the method, on the premise of correcting the sampling time deviation of the comparator, the signal swing of the residual error signal output by the MDAC module is further reduced, so that the linearity performance of the MDAC module is improved, and the performances of the whole assembly line analog-to-digital conversion circuit and the assembly line analog-to-digital converter are improved.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the comparison module and the control module are added in the circuit, the control module is used for acquiring the signal output by the circuit, and outputting the control signal to adjust the clock deviation of the SADC module or the comparison module under the condition that the output signal meets the adjustment condition. Compared with the scheme of the related technology, the method only adds the comparison module and the control module, does not increase noise, has little influence on power consumption and has low cost of an analog circuit; and the time deviation error of the comparator can be tracked along with the change of different environmental temperatures and working voltages, so that the real-time correction of the analog-digital conversion circuit is realized, and the correction precision of the analog-digital conversion circuit is improved. The analog-to-digital conversion circuit according to the embodiment of the disclosure can be applied to MDAC modules of analog-to-digital conversion circuits of various levels of a pipeline ADC, and can respectively carry out real-time correction on the analog-to-digital conversion circuits of various levels.

According to an embodiment of the present disclosure, there is also provided a pipeline analog-to-digital converter, which includes a plurality of stages of analog-to-digital conversion circuits, each stage of analog-to-digital conversion circuit including the analog-to-digital conversion circuit described above.

The specific manner in which the various blocks perform operations with respect to the pipelined analog-to-digital converter has been described in detail in relation to embodiments of the analog-to-digital conversion circuit and will not be elaborated upon here.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit, the circuit being a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-analog-to-digital conversion SADC module, an analog-to-digital conversion and amplification MDAC module, a comparison module and a control module,

wherein the control module is configured to:

2. The circuit of claim 1, wherein the SADC module comprises a first regulation unit and N comparators, the first digital signal comprising an N-bit digital signal, N being an integer greater than 1,

3. The circuit of claim 2, wherein the comparison module comprises a second adjustment unit and a replica comparator,

the replica comparator inputs the first analog signal and the second off-clock signal,

the reference voltage of the replica comparator is the same as the jth comparator of the N comparators, the replica comparator is configured to compare the sampling voltage of the first analog signal with the reference voltage of the replica comparator and output a compared digital signal, j is an integer and 1< j < N,

4. The circuit of claim 3, wherein the adjustment condition further comprises: the second digital signal is different from a jth bit of the first digital signal.

5. The circuit of any one of claims 1-4, wherein the control module determines the reference residual signal of the comparison module according to the first digital signal, the residual signal, and the second digital signal, and comprises:

6. The circuit of any of claims 2-4, wherein the control module adjusts the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal, comprising:

7. The circuit of claim 3 or 4, wherein the control module adjusts the first control signal or the second control signal according to a relationship between the residual signal and the reference residual signal, further comprising:

8. The circuit of claim 3 or 4, wherein after the residual signal is adjusted to be within the first voltage interval, the method further comprises:

9. A circuit as claimed in claim 3, characterized in that [ N/2] -1< j ≦ [ N/2] + 1.

10. A pipeline analog-to-digital converter, characterized in that the pipeline analog-to-digital converter comprises a plurality of stages of analog-to-digital conversion circuits, each stage of analog-to-digital conversion circuit comprising an analog-to-digital conversion circuit according to any one of claims 1 to 9.