CN114362742A - High-speed receiving circuit and operation method thereof - Google Patents

High-speed receiving circuit and operation method thereof Download PDF

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CN114362742A
CN114362742A CN202011096185.2A CN202011096185A CN114362742A CN 114362742 A CN114362742 A CN 114362742A CN 202011096185 A CN202011096185 A CN 202011096185A CN 114362742 A CN114362742 A CN 114362742A
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source
nmosfet
drain
pmosfet
output
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许振隆
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Beijing Pingxin Technology Co ltd
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Nyanox Sox Ltd Private Trading Co
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Abstract

The invention relates to a high-speed receiving circuit, comprising: a first nMOSFET (MN1), a second nMOSFET (MN2), a first pMOSFET (MP1), and a second pMOSFET (MP 2). The high-speed receiving circuit further includes a third nMOSFET (MN3) and a fourth nMOSFET (MN 4). The invention also relates to a method for operating such a circuit. By the high-speed receiving circuit and/or the method, the delay of the high-speed receiver can be remarkably reduced, and the input voltage range of the high-speed stable operation of the high-speed receiver can be expanded.

Description

High-speed receiving circuit and operation method thereof
Technical Field
The present invention relates generally to the field of integrated circuits, and more particularly to a high speed receive circuit. The invention further relates to a method for operating such a circuit.
Background
As a data receiving and level converting apparatus, a high-speed receiver is widely used in hardware devices such as a memory. However, the current high-speed receiver has the problems of high time delay and unbalanced duty ratio of output signals. Therefore, there is a need for a high speed receiver with lower latency and higher stability.
Disclosure of Invention
Starting from the prior art, the object of the present invention is to provide a high-speed receiver circuit and a method for operating the same, by means of which the delay of a high-speed receiver can be significantly reduced and at the same time the input voltage range for its high-speed and stable operation can be extended.
In a first aspect of the invention, the aforementioned task is solved by a high speed receiving circuit comprising:
a first n-type metal oxide semiconductor field effect transistor nMOSFET (MN1) having a gate connected to the input terminal (IN) and to the gate of the fourth nMOSFET (NM4), a first one of its drain and source connected to ground, and a second one of its drain and source connected to a first one of the drain and source of the third nMOSFET (MN 3);
a second nMOSFET (MN2) having gate and inverting input terminal
Figure BDA0002723831660000011
Is connected and is connected to the gate of the third nMOSFET (NM3), a first one of its drain and source is grounded, and a second one of its drain and source is connected to a first one of the drain and source of the fourth nMOSFET (MN 4);
a third nMOSFET (MN3) having a first one of its drain and source and an inverted output terminal
Figure BDA0002723831660000012
Is connected to and connected to a first one of the drain and source of a first p-type metal oxide semiconductor field effect transistor pMOSFET (MP1) and to the gate of a second pMOSFET (MP2), and a second one of the drain and source thereof is connected to a supply voltage (V)dd) Connecting;
a fourth nMOSFET (MN4) having a first one of its drain and source connected to the output terminal (OUT) and to a first one of the drain and source of the second pMOSFET (MP2) and to the gate of the first pMOSFET (MP1), and a second one of its drain and source connected to the supply voltage (V)dd) Connecting;
a first pMOSFET (MP1) having a second one of its drain and source connected to a supply voltage (V)dd) Connecting; and
a second pMOSFET (MP2) having a second one of its drain and source connected to a supply voltage (V)dd) And (4) connecting.
In the present invention, the terms "a first one of the drain and the source" and "a second one of the drain and the source" refer to one and the other of the drain and the source, respectively, i.e. if the first is the drain, the second is the source, and vice versa. The drain and source can be interchanged according to application requirements.
In one embodiment of the invention, it is provided that the first to fourth nmosfets (MN1, MN2, MN3, MN4) and the first to second pmosfets (MP1, MP2) comprise one or more of the following: enhancement mode field effect transistors, and depletion mode field effect transistors. Other types of MOSFETs may also be selected according to different scenarios.
In a preferred embodiment of the present invention, it is provided that the first one of the drain and the source of the first to second nmosfets (MN1, MN2) is the source, and the second one is the drain; and/or
A first one of the drain and the source of the third to fourth nmosfets (MN3, MN4) is a drain, and a second one is a source; and/or
The first one of the drain and the source of the first to second pMOSFETs (MP1, MP2) is the drain, and the second one is the source.
The drain and source connections of the MOSFET may be different depending on the transistor and circuit arrangement.
IN one embodiment of the invention, it is provided that the high-level value of the input signal input at the Input (IN) is less than, equal to, or greater than the high-level value of the output signal output at the Output (OUT).
In a preferred embodiment of the invention, it is provided that the high-level value of the input signal is at least V greater than the high-level value of the output signalthIn which V isthIs the gate-source turn-on threshold voltage of the third and/or fourth nmosfets (MN3, MN 4). When the voltage of the input signal reaches a level that enables the third and/or fourth nmosfets (MN3, MN4) to be turned on, a lower delay can be achieved and thereby extend the input voltage range of the high speed receiver. It should be noted, however, that the high speed receive circuit of the present invention can also operate below VddVoltage range of (c).
In a preferred embodiment of the invention, it is provided that 0.1 V.ltoreq.VthLess than or equal to 1.4V. It should be noted here that the term "conducting" as used in the present invention does not only mean "fully conducting", but also covers "starting conducting" and "partially conducting". Similarly, the term "gate-source turn-on threshold voltage" also does not merely refer to the voltage difference between the gate-source of an nMOSFET when fully turned on, but also covers the onset of conductionThe voltage difference between the gate and the source when on or partially on. For example, when VthLower, i.e. input voltage vs. supply voltage VddSlightly larger, the third and fourth nmosfets start to conduct, and the output signal is already available, so that the effect of reducing the output delay is still achieved. For example, VthValues of 0.1, 0.2, 0.3, 0.4, 0.7, 1, 1.2, 1.3, 1.4V may be selected.
In a second aspect of the present invention, the foregoing task is solved by a high-speed receiving circuit having a level shift function, comprising:
a first n-type metal oxide semiconductor field effect transistor nMOSFET (MN1) having a gate connected to the input terminal (IN) and to a gate of a fourth nMOSFET (NM4), a first one of a drain and a source thereof grounded, and a second one of the drain and the source thereof connected to a first one of a drain and a source of a third nMOSFET (MN3), wherein an input signal input at the input terminal (IN) has a first high level value;
a second nMOSFET (MN2) having gate and inverting input terminal
Figure BDA0002723831660000031
Is connected and is connected to the gate of the third nMOSFET (NM3), a first one of its drain and source is grounded, and a second one of its drain and source is connected to a first one of the drain and source of the fourth nMOSFET (MN 4);
a third nMOSFET (MN3) having a first one of its drain and source and an inverted output terminal
Figure BDA0002723831660000032
Is connected to and connected to a first one of the drain and source of a first p-type metal oxide semiconductor field effect transistor pMOSFET (MP1) and to the gate of a second pMOSFET (MP2), and a second one of the drain and source thereof is connected to a supply voltage (V)dd) Connecting;
a fourth nMOSFET (MN4) having a first one of its drain and source connected to the output terminal (OUT) and to a first one of the drain and source of the second pMOSFET (MP2) and to the gate of the first PMOSFET (MP1)And the second of its drain and source is connected to the supply voltage (V)dd) -connecting, wherein the output signal output at the output terminal (OUT) has a second high value, the second high value not being equal to the first high value;
a first pMOSFET (MP1) having a second one of its drain and source connected to a supply voltage (V)dd) Connecting; and
a second pMOSFET (MP2) having a second one of its drain and source connected to a supply voltage (V)dd) And (4) connecting.
In a preferred embodiment of the invention, it is provided that the first high value is at least V greater than the second high valuethIn which V isthIs the gate-source turn-on threshold voltage of the third and/or fourth nmosfets (MN3, MN 4).
In a third aspect of the invention, the aforementioned task is solved by a method for operating a high-speed receiving circuit according to the invention, comprising the steps of:
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure BDA0002723831660000041
Applying a first high level VHIn which V isH–Vdd<VthIn which V isthIs the gate-source turn-on threshold voltage of the third and fourth nMOSFETs (MN3, MN4), so that the second nMOSFET (MN2) and the first pMOSFET (MP1) are turned on, and the first nMOSFET (MN1), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned off, and are turned off at the inverting output terminal
Figure BDA0002723831660000042
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT); and
applying a high level V to the Input (IN)HAnd to the inverting input terminal
Figure BDA0002723831660000043
Applying a low level VLSo that the first nMOSFET (MN1) and the second pMOSFET (MP2) are turned on, and the second pMOSFET is turned offThe nMOSFET (MN2), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the first pMOSFET (MP1) are turned off, and a power supply voltage (V) is output at an output terminal (OUT)dd) And at the inverting output
Figure BDA0002723831660000044
And outputs a low level.
In a preferred embodiment of the invention, it is provided that the method further comprises the following steps:
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure BDA0002723831660000045
Applying a second high level VH', wherein VH’–Vdd≥VthSo that the second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are turned on, and the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned off, and at the inverting output terminal
Figure BDA0002723831660000046
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT); and
applying a second high level V to the input terminal (IN)H' and to the inverting input terminal
Figure BDA0002723831660000047
Applying a low level VLSo that the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned on, and the second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are turned off, and the power supply voltage (V) is output at the output terminal (OUT)dd) And at the inverting output
Figure BDA0002723831660000048
And outputs a low level.
In a fourth aspect of the present invention, the aforementioned task is solved by a method for level conversion using a high-speed receiving circuit according to the present invention, the method comprising the steps of:
determining the supply voltage (V)dd) And a high level voltage V of the input signalH', make VH’–Vdd≥VthIn which V isthGate-source turn-on threshold voltages for the third and fourth nmosfets (MN3, MN 4);
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure BDA0002723831660000051
Applying a high level voltage VH', such that at the inverting output
Figure BDA0002723831660000052
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT); and
applying a high level V to the Input (IN)H' and to the inverting input terminal
Figure BDA0002723831660000053
Applying a low level VLSo that the supply voltage (V) is output at the output terminal (OUT)dd) And at the inverting output
Figure BDA0002723831660000054
And outputs a low level.
Furthermore, the invention relates to a high-speed receiver comprising a high-speed receiving circuit according to the invention.
The invention has at least the following beneficial effects: after research, the inventor finds that the following unexpected effects can be achieved after two n-type MOSFETs are added to a high-speed receiving circuit: first, the present invention has been found uniquely that in some applications, the input voltage may be greater than the power supply voltage Vdd, and at this time, the output signal of the conventional receiver will have a problem of duty distortion or imbalance due to a large delay difference of the output signals of the p-type MOSFET and the n-type MOSFET at the high input voltage (i.e., at the high input voltage, the n-type MOSFET will be rapidly turned on and the p-type MOSFET will be turned on with a delay, which results in a large delay time difference and causes distortion of the output waveform), in the present invention, by adding two n-type MOSFETs, i.e., a third nMOSFET (MN3) and a fourth nMOSFET (MN4), one of the added two n-type MOSFETs can be rapidly turned on at a higher voltage to provide an output signal, thereby eliminating the delay time difference and further outputting an output signal with a normal waveform; (2) the n-type MOSFET is faster to conduct, so that lower output delay can be realized at high input voltage, and the response speed of the receiver is improved; meanwhile, the voltage range of high-speed signal receiving of the high-speed receiving circuit is expanded, namely, the high-speed signal receiving and the level conversion can be realized in the whole voltage range.
Drawings
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
FIG. 1 shows a circuit diagram of a high speed receive circuit according to the present invention; and
fig. 2 shows a graph of an output voltage waveform of a high-speed receiving circuit according to the present invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, "disposed on …", "disposed over …" and "disposed over …" do not exclude the presence of an intermediate therebetween, unless otherwise specified. Further, "disposed on or above …" merely indicates the relative positional relationship between two components, and may also be converted to "disposed below or below …" and vice versa in certain cases, such as after reversing the product direction.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario. Furthermore, features from different embodiments of the invention may be combined with each other, unless otherwise indicated. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal". By analogy, in the present invention, the terms "perpendicular", "parallel" and the like in the directions of the tables also cover the meanings of "substantially perpendicular", "substantially parallel".
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
First, the principle on which the present invention is based is explained.
The inventor finds that in some application occasions, the input voltage is possibly larger than the power supply voltage VddAt this time, the output signal of the conventional receiver has a problem of duty distortion or imbalance due to an increase in delay difference of the output signals of the p-type MOSFET and the n-type MOSFET at a high input voltage (i.e., at a high input voltage, the n-type MOSFET is rapidly turned on, and the p-type MOSFET is turned on with a delay, which causes a large delay time difference and causes distortion of an output waveform), in the present invention, by adding two n-type MOSFETs, i.e., a third nMOSFET (MN3) and a fourth nMOSFET (MN4), one of the two additional n-type MOSFETs can be rapidly turned on at a higher voltage to provide an output signal, thereby eliminating the delay time difference and outputting an output signal with a normal waveform; second, n-type MOSFETs turn on faster than p-type MOSFETs,therefore, at high input voltage, lower output delay can be realized, thereby improving the response speed of the receiver; thirdly, the voltage range of high-speed signal receiving of the high-speed receiving circuit is expanded through the invention, namely, the high-speed signal receiving and the level conversion can be realized in the whole voltage range.
It should be noted here that the term "conducting" as used in the present invention does not only mean "fully conducting", but also covers "starting conducting" and "partially conducting". Similarly, the term "gate-source turn-on threshold voltage" also does not merely refer to the voltage difference between the gate-source of an nMOSFET when fully turned on, but also covers the voltage difference between its gate-source when it begins to turn on or partially turns on. For example, at VthLower, i.e. input voltage vs. supply voltage VddSlightly larger, when the third and fourth nmosfets start to conduct or are partially conducting, the correct output signal is already available, and therefore the effect of reducing the output delay is still achieved.
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
Fig. 1 shows a circuit diagram of a high-speed receiving circuit 100 according to the present invention.
As shown in fig. 1, a high-speed receiving circuit 100 according to the present invention includes the following components:
a first n-type metal oxide semiconductor field effect transistor nMOSFET (MN1) having a gate connected to the input terminal (IN) and to the gate of the fourth nMOSFET (NM4), a first one (IN this embodiment, the source) of the drain and the source of the first nMOSFET (MN1) being grounded to GND, and a second one (IN this embodiment, the drain) of the drain and the source of the first nMOSFET (MN1) being connected to the first one (IN this embodiment, the drain) of the drain and the source of the third nMOSFET (MN 3). In different embodiments, the source and drain may be interchanged. In addition, the ground GND may be selected to be a different voltage or potential, for example a voltage or potential other than 0, in different embodiments.
A second nMOSFET (MN2) having gate and inverting input terminal
Figure BDA0002723831660000071
Connected and connected to the gate of the third nMOSFET (NM3), a first one (source in this embodiment) of the drain and source of the second nMOSFET (MN2) is grounded to GND, and a second one (drain in this embodiment) of the drain and source of the second nMOSFET (MN2) is connected to a first one (drain in this embodiment) of the drain and source of the fourth nMOSFET (MN 4).
A third nMOSFET (MN3) having a first one of its drain and source (drain in this embodiment) and an inverted output terminal
Figure BDA0002723831660000072
Is connected to and connected to a first one (drain in this embodiment) of the drain and source of the first p-type metal oxide semiconductor field effect transistor pMOSFET (MP1) and to the gate of the second pMOSFET (MP2), and a second one (source in this embodiment) of the drain and source of the third nMOSFET (MN3) is connected to a supply voltage (V)dd) And (4) connecting.
A fourth nMOSFET (MN4) having a first one of a drain and a source (the drain in this embodiment) connected to the output terminal (OUT) and a first one of a drain and a source (the drain in this embodiment) of the second pMOSFET (MP2) and a gate of the first pMOSFET (MP1), and a second one of a drain and a source (the source in this embodiment) of the fourth nMOSFET (MN4) connected to the power supply voltage (V)dd) And (4) connecting.
A first pMOSFET (MP1) having a second one of its drain and source (source in this embodiment) and a supply voltage (V)dd) And (4) connecting.
A second pMOSFET (MP2) having a second one of its drain and source (source in this embodiment) and a supply voltage (V)dd) And (4) connecting.
The n-type MOSFET and the p-type MOSFET can be selected from different types of MOSFETs, such as enhancement type MOSFETs, depletion type MOSFETs and the like according to specific needs.
The operating principle of the high-speed receiving circuit according to the present invention is explained below.
Low high level of input signal
Applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure BDA0002723831660000081
Applying a first high level VHIn which V isH–Vdd<Vth(e.g. V)H' slightly less than or less than Vdd) In which V isthIs the gate-source turn-on threshold voltage of the third and fourth nMOSFETs (MN3, MN4), so that the second nMOSFET (MN2) and the first pMOSFET (MP1) are turned on, and the first nMOSFET (MN1), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned off, and are turned off at the inverting output terminal
Figure BDA0002723831660000082
Output power supply voltage (V)dd) And outputs a low level, for example, a ground GND level, at an output terminal (OUT). VthFor example, values of 0.1, 0.2, 0.3, 0.4, 0.7, 1, 1.1, 1.2, 1.3, 1.4V may be selected.
Applying a high level V to the Input (IN)HAnd to the inverting input terminal
Figure BDA0002723831660000083
Applying a low level VLSo that the first nMOSFET (MN1) and the second pMOSFET (MP2) are turned on, and the second nMOSFET (MN2), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the first pMOSFET (MP1) are turned off, and a power supply voltage (V) is output at an output terminal (OUT)dd) And at the inverting output
Figure BDA0002723831660000084
Outputs a low level, for example the ground GND level.
Case where high level of input signal is high
Applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure BDA0002723831660000085
Applying a second high level VH', wherein VH’–Vdd≥Vth(e.g. V)H' slightly or more than Vdd) The second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are made conductive, and the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are made non-conductive, and at the inverting output terminal
Figure BDA0002723831660000091
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT). Here, since the third nMOSFET (MN3) is turned on faster than the first pMOSFET (MP1), delay of signal output can be reduced, and at the same time, since the third nMOSFET (MN3) is turned on at the same speed as the second nMOSFET (MN2), i.e., both are turned on substantially simultaneously, distortion in the output signal, such as jitter and duty imbalance, etc., can be substantially eliminated. VthFor example, values of 0.1, 0.2, 0.3, 0.4, 0.7, 1V may be selected.
Applying a second high level V to the input terminal (IN)H' and to the inverting input terminal
Figure BDA0002723831660000092
Applying a low level VLSo that the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned on, and the second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are turned off, and the power supply voltage (V) is output at the output terminal (OUT)dd) And at the inverting output
Figure BDA0002723831660000093
And outputs a low level. Here, since the fourth nMOSFET (MN4) is turned on faster than the second pMOSFET (MP2), delay of signal output can be reduced, and at the same time, since the fourth nMOSFET (MN4) is turned on at the same speed as the first nMOSFET (MN1), i.e., both are turned on substantially simultaneously, distortion in the output signal, such as jitter and duty imbalance, etc., can be substantially eliminated.
As can be seen from the above, by using the third nMOSFET (MN3) and the fourth nMOSFET (MN4), on the one hand, delay is reduced, response speed is improved, on the other hand, distortion in an output signal is eliminated, and a voltage range in which a receiving circuit operates at high speed is expanded, for example, high-speed and stable operation is possible both at low voltage and high input voltage.
Fig. 2 shows a graph of an output voltage waveform of a high-speed receiving circuit according to the present invention.
FIG. 2 is a signal simulation diagram, here with VddFor example, the voltage difference of the input signal is 0.4V to 1.2V when the voltage is 0.9V. As can be seen from fig. 2, the delay of the output signal is around 29.1 ps. It can be seen that the delay of the high-speed receiving circuit of the present invention is greatly reduced compared to the prior art, and the output waveform has no significant distortion.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (12)

1. A high speed receive circuit comprising:
a first n-type metal oxide semiconductor field effect transistor nMOSFET (MN1) having a gate connected to the input terminal (IN) and to the gate of the fourth nMOSFET (NM4), a first one of its drain and source connected to ground, and a second one of its drain and source connected to a first one of the drain and source of the third nMOSFET (MN 3);
a second nMOSFET (MN2) having gate and inverting input terminal
Figure FDA0002723831650000011
Is connected and is connected to the gate of the third nMOSFET (NM3), a first one of its drain and source is grounded, and a second one of its drain and source is connected to a first one of the drain and source of the fourth nMOSFET (MN 4);
a third nMOSFET (MN3) having a first one of its drain and source and an inverted output terminal
Figure FDA0002723831650000012
Is connected to and connected to a first one of the drain and source of a first p-type metal oxide semiconductor field effect transistor pMOSFET (MP1) and to the gate of a second pMOSFET (MP2), and a second one of the drain and source thereof is connected to a supply voltage (V)dd) Connecting;
a fourth nMOSFET (MN4) having a first one of its drain and source connected to the output terminal (OUT) and to a first one of the drain and source of the second pMOSFET (MP2) and to the gate of the first pMOSFET (MP1), and a second one of its drain and source connected to the supply voltage (V)dd) Connecting;
a first pMOSFET (MP1) having a second one of its drain and source connected to a supply voltage (V)dd) Connecting; and
a second pMOSFET (MP2) having a second one of its drain and source connected to a supply voltage (V)dd) And (4) connecting.
2. The high-speed receiving circuit of claim 1, wherein the first to fourth nmosfets (MN1, MN2, MN3, MN4) and first to second pmosfets (MP1, MP2) include one or more of: enhancement mode field effect transistors, and depletion mode field effect transistors.
3. The high-speed receiving circuit according to claim 1, wherein a first one of the drain and the source of said first to second nmosfets (MN1, MN2) is a source, and a second one is a drain; and/or
A first one of the drain and the source of the third to fourth nmosfets (MN3, MN4) is a drain, and a second one is a source; and/or
The first one of the drain and the source of the first to second pMOSFETs (MP1, MP2) is the drain, and the second one is the source.
4. A high speed receiving circuit according to claim 1, wherein a high level value of the input signal inputted at the input terminal (IN) is smaller than, equal to or larger than a high level value of the output signal outputted at the output terminal (OUT).
5. The high speed receiving circuit of claim 4, wherein a high level value of the input signal is at least V greater than a high level value of the output signalthIn which V isthIs the gate-source turn-on threshold voltage of the third and/or fourth nmosfets (MN3, MN 4).
6. The high speed receive circuit of claim 5, wherein 0.1V ≦ Vth ≦ 1.4V.
7. A high-speed receiving circuit with a level conversion function, comprising:
a first n-type metal oxide semiconductor field effect transistor nMOSFET (MN1) having a gate connected to the input terminal (IN) and to a gate of a fourth nMOSFET (NM4), a first one of a drain and a source thereof grounded, and a second one of the drain and the source thereof connected to a first one of a drain and a source of a third nMOSFET (MN3), wherein an input signal input at the input terminal (IN) has a first high level value;
a second nMOSFET (MN2) having gate and inverting input terminal
Figure FDA0002723831650000021
Is connected and is connected to the gate of the third nMOSFET (NM3), a first one of its drain and source is grounded, and a second one of its drain and source is connected to a first one of the drain and source of the fourth nMOSFET (MN 4);
a third nMOSFET (MN3) having a first one of its drain and source and an inverted output terminal
Figure FDA0002723831650000022
Is connected to and connected to a first one of the drain and source of a first p-type metal oxide semiconductor field effect transistor pMOSFET (MP1) and to the gate of a second pMOSFET (MP2), and a second one of its drain and source is connected toSupply voltage (V)dd) Connecting;
a fourth nMOSFET (MN4) having a first one of its drain and source connected to the output terminal (OUT) and to a first one of the drain and source of the second pMOSFET (MP2) and to the gate of the first PMOSFET (MP1), and a second one of its drain and source connected to the supply voltage (V)dd) -connecting, wherein the output signal output at the output terminal (OUT) has a second high value, the second high value not being equal to the first high value;
a first pMOSFET (MP1) having a second one of its drain and source connected to a supply voltage (V)dd) Connecting; and
a second pMOSFET (MP2) having a second one of its drain and source connected to a supply voltage (V)dd) And (4) connecting.
8. The high speed receiving circuit of claim 7, wherein the first high level value is at least V greater than the second high level valuethIn which V isthIs the gate-source turn-on threshold voltage of the third and/or fourth nmosfets (MN3, MN 4).
9. A method for operating a high speed receiving circuit according to one of claims 1 to 6, comprising the steps of:
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure FDA0002723831650000031
Applying a first high level VHIn which V isH–Vdd<VthIn which V isthIs the gate-source turn-on threshold voltage of the third and fourth nMOSFETs (MN3, MN4), so that the second nMOSFET (MN2) and the first pMOSFET (MP1) are turned on, and the first nMOSFET (MN1), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned off, and are turned off at the inverting output terminal
Figure FDA0002723831650000032
Output power supply voltage (V)dd) And outputs low at the output terminal (OUT)A level; and
applying a high level V to the Input (IN)HAnd to the inverting input terminal
Figure FDA0002723831650000033
Applying a low level VLSo that the first nMOSFET (MN1) and the second pMOSFET (MP2) are turned on, and the second nMOSFET (MN2), the third nMOSFET (MN3), the fourth nMOSFET (MN4) and the first pMOSFET (MP1) are turned off, and a power supply voltage (V) is output at an output terminal (OUT)dd) And at the inverting output
Figure FDA0002723831650000034
And outputs a low level.
10. The method of claim 9, further comprising the steps of:
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure FDA0002723831650000035
Applying a second high level VH', wherein VH’–Vdd≥VthSo that the second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are turned on, and the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned off, and at the inverting output terminal
Figure FDA0002723831650000036
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT); and
applying a second high level V to the input terminal (IN)H' and to the inverting input terminal
Figure FDA0002723831650000037
Applying a low level VLSo that the first nMOSFET (MN1), the fourth nMOSFET (MN4) and the second pMOSFET (MP2) are turned on, and the second nMOSFET (MN2), the third nMOSFET (MN3) and the first pMOSFET (MP1) are turned off, and at the output terminal(OUT) output supply voltage (V)dd) And at the inverting output
Figure FDA0002723831650000038
And outputs a low level.
11. A method of level shifting using a high speed receiving circuit according to any of claims 1 to 6, comprising the steps of:
determining the supply voltage (V)dd) And a high level voltage V of the input signalH', make VH’–Vdd≥VthIn which V isthGate-source turn-on threshold voltages for the third and fourth nmosfets (MN3, MN 4);
applying a low level V to the input terminal (IN)LAnd to the inverting input terminal
Figure FDA0002723831650000039
Applying a high level voltage VH', such that at the inverting output
Figure FDA0002723831650000041
Output power supply voltage (V)dd) And outputs a low level at an output terminal (OUT); and
applying a high level V to the Input (IN)H' and to the inverting input terminal
Figure FDA0002723831650000042
Applying a low level VLSo that the supply voltage (V) is output at the output terminal (OUT)dd) And at the inverting output
Figure FDA0002723831650000043
And outputs a low level.
12. A high speed receiver comprising a high speed receiving circuit according to one of claims 1 to 6.
CN202011096185.2A 2020-10-14 2020-10-14 High-speed receiving circuit and operation method thereof Pending CN114362742A (en)

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Application Number Priority Date Filing Date Title
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