CN114361247A - Trench gate metal oxide semiconductor field effect transistor and preparation method thereof - Google Patents
Trench gate metal oxide semiconductor field effect transistor and preparation method thereof Download PDFInfo
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Abstract
The application relates to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof, wherein the preparation method comprises the following steps: a first conductivity type drift region; a second conductive type body region formed in the drift region; the first conduction type source region is formed in the body region and provided with a groove extending into the drift region; a first conductive structure and a second conductive structure which are isolated from each other are filled in the groove, the bottom depth of the first conductive structure is greater than that of the second conductive structure, and the part of the first conductive structure, the depth of which exceeds that of the second conductive structure, is defined as a field plate adjusting structure; the first doping region is of the second conduction type, is formed in the drift region and is connected with the body region, and the bottom depth of the first doping region exceeds the top depth of the field plate adjusting structure; the source region and the body region are connected with the source electrode; the second conductive structure is connected with the gate. By forming the first doping region and the field plate adjusting structure, the depletion of the drift region can be enhanced, and the withstand voltage of the device is improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof.
Background
In a Metal Oxide Semiconductor Field Effect Transistor (MOS), a conduction channel is formed between the source electrode and the drain electrode, the existence of the conduction channel enables the metal oxide semiconductor field effect transistor to have certain conduction resistance, the larger the conduction resistance is, the greater its power consumption, and therefore, the need to minimize on-resistance, currently, mosfets with trench gate structures are commonly used, by forming the trench gate structure, the channel is changed from horizontal to vertical, which greatly increases the cell density and reduces the on-resistance, however, on the basis of the trench gate metal oxide semiconductor field effect transistor, if the on-resistance is further reduced, the doping concentration of the drift region needs to be increased, and increasing the doping concentration will reduce the voltage endurance capability of the device, therefore, limited by the voltage endurance capability, making it difficult to further reduce the on-resistance of the trench-gate mosfet.
Disclosure of Invention
Therefore, it is necessary to provide a new mosfet and a method for manufacturing the same to solve the technical problem that it is difficult to further reduce the on-resistance of the existing trench-gate mosfet.
A trench-gate mosfet, comprising:
a drift region having a first conductivity type formed on the semiconductor substrate;
the body region is provided with a second conduction type and is formed on the upper surface layer of the drift region;
the source region is provided with a first conduction type and is formed on the upper surface layer of the body region;
the groove penetrates through the source region and the body region in sequence and extends into the drift region;
the filling structure comprises a first conductive structure and a second conductive structure which are filled in the groove and are isolated from each other, and oxide layers which are formed between the first conductive structure and the inner wall of the groove and between the second conductive structure and the inner wall of the groove, wherein the depth of the bottom of the first conductive structure exceeds the depth of the bottom of the second conductive structure, and the part of the first conductive structure, the depth of which exceeds the depth of the bottom of the second conductive structure, is defined as a field plate adjusting structure;
the first doping region is formed in the drift region and connected with the lower surface of the body region, the first doping region and the groove are arranged at intervals, and the bottom depth of the first doping region exceeds the top depth of the field plate adjusting structure;
the source electrode lead-out structure is connected with the source region and the body region; and
and the grid electrode leading-out structure is connected with the second conductive structure.
In one embodiment, the sidewall of the first doped region includes a first portion extending downward from the bottom of the body region and parallel to the trench sidewall and a second portion extending downward from the first portion and gradually sloping toward the inside of the first doped region, and the interface of the first portion and the second portion passes through the field plate adjustment structure.
In one embodiment, the mosfet has a plurality of the first doped regions and a plurality of the trenches, each of the trenches is filled with the filling structure, and the first doped regions and the trenches are alternately disposed at intervals.
In one embodiment, the cross section of each groove is in a long strip shape, and a plurality of first doping regions which are arranged along the length direction of the groove at intervals are arranged between every two adjacent grooves.
In one embodiment, the method further comprises the following steps:
an interlayer dielectric layer formed on the source region and the top surface of the trench;
the source electrode lead-out structure penetrates through the interlayer dielectric layer and the source region and extends into the body region to be respectively connected with the source region and the body region;
the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second conductive structure.
In one embodiment, a second doped region is formed in the body region, the second doped region has a second conductivity type, the doping concentration of the second doped region is higher than that of the body region, the second doped region is located below the source region and spaced from the trench, and the source lead-out structure penetrates through the source region and extends into the second doped region.
According to the metal oxide semiconductor field effect transistor, the cell area is provided with the groove, the second conducting structure and the oxide layer are formed in the groove, the second conducting structure is a grid conducting structure, the oxide layer located between the second conducting structure and the inner wall of the groove is a grid oxide layer, the second conducting structure is connected with the grid through the grid leading-out structure, therefore, the groove grid structure is formed, and the longitudinal conduction channel is formed in the body area through the groove grid structure. Meanwhile, the grooves are filled with first conductive structures which are isolated from the second conductive structures besides the second conductive structures, the depth of the first conductive structures is larger than that of the second conductive structures, and the parts of the first conductive structures, the depth of which exceeds the bottom depth of the second conductive structures, are field plate adjusting structures, namely inner field plates for adjusting the electric field of the drift region are formed in the cellular regions. Meanwhile, a first doping region is formed in the cell region, the first doping region is connected with the body region and has a source electrode potential, the conduction type of the first doping region is opposite to that of the drift region, the bottom depth of the first doping region exceeds the top depth of the field plate adjusting structure, so that depletion regions formed by the first doping region and the inner field plate are located at the same height, under the combined action of the first doping region and the inner field plate, depletion of the drift region can be enhanced, and breakdown voltage of the drift region is improved. Therefore, under the condition of equal breakdown voltage, the drift region of the trench gate metal oxide semiconductor field effect transistor can improve the doping concentration, so that the on-resistance is reduced, namely, under the condition of equal breakdown voltage, the trench gate metal oxide semiconductor field effect transistor has lower on-resistance.
A preparation method of a trench gate metal oxide semiconductor field effect transistor comprises the following steps:
providing a semiconductor substrate and forming a drift region with a first conductivity type on the semiconductor substrate;
forming a groove on the drift region, forming an oxide layer on the inner wall of the groove, and filling a first conductive structure and a second conductive structure which are isolated from each other in the groove, wherein the depth of the bottom of the first conductive structure is greater than that of the bottom of the second conductive structure, and the part of the first conductive structure, the depth of which exceeds that of the bottom of the second conductive structure, is defined as a field plate adjusting structure;
doping the upper surface layer of the drift region to form a body region which is in contact with the side wall of the groove and has a second conduction type, wherein the depth of the body region is smaller than that of the groove; doping the upper surface layer of the body region to form a source region which is in contact with the side wall of the groove and has a first conductive type;
forming a first doped region with a second conductivity type in the drift region, wherein the first doped region is connected with the body region, the first doped region is arranged at an interval with the trench, and the bottom depth of the first doped region exceeds the top depth of the field plate adjusting structure; and
and forming a source electrode lead-out structure connected with the source region and the body region, and forming a grid electrode lead-out structure connected with the second conductive structure.
In one embodiment, after the step of doping the upper surface layer of the body region to form the first conductivity type source region in contact with the trench sidewall, the method further includes:
forming an interlayer dielectric layer on the source region and the groove;
sequentially etching the interlayer dielectric layer, the source region and the body region to form a source contact hole penetrating through the dielectric layer and the source region and extending to the body region;
the first doped region connected with the lower surface of the body region is formed in the drift region, and the first doped region comprises: injecting second conductive type impurities into the drift region through the source contact hole, and forming a first doped region connected with the lower surface of the body region in the drift region;
the forming of the source lead-out structure connected to the source region, the body region and the first conductive structure includes: and filling a conductive material into the source contact hole to form the source electrode lead-out structure.
In one embodiment, forming a first doped region having a second conductivity type within the drift region includes:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
doping the first epitaxial layer to form a first doped region with a second conductivity type;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
In one embodiment, forming a first doped region having a second conductivity type within the drift region includes:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
forming a shallow groove on the first epitaxial layer, and epitaxially growing a first doped region with a second conductivity type in the shallow groove;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
According to the preparation method of the trench gate metal oxide semiconductor field effect transistor, the first conductive structure is arranged at the bottom of the trench gate, namely the inner field plate for adjusting the electric field of the drift region is arranged in the drift region, the first doped region is also arranged in the drift region, the conductive type of the first doped region is opposite to that of the drift region, the first doped region is connected with the source electrode through the body region, and under the combined action of the first doped region and the field plate structure at the bottom of the trench gate, the depletion of the drift region is enhanced, so that the voltage resistance of the device is improved. Therefore, under the condition of equal breakdown voltage, the drift region of the trench gate metal oxide semiconductor field effect transistor formed by the preparation method can have higher doping concentration, so that the trench gate metal oxide semiconductor field effect transistor has lower on-resistance.
Drawings
FIG. 1 is a partial cross-sectional side view of a trench gate MOSFET cell region in an embodiment of the present application;
FIG. 2 is a partial cross-sectional side view of a trench gate MOSFET cell region in another embodiment of the present application;
FIG. 3a is a cross-sectional view of a trench-gate MOSFET along line A-A' of FIG. 1 in accordance with an embodiment of the present invention;
FIG. 3b is a cross-sectional view of another embodiment of the trench gate MOSFET along line A-A' of FIG. 1;
FIG. 4a is a schematic diagram of a trench structure according to an embodiment of the present application;
FIG. 4b is a schematic diagram of a structure in a trench according to another embodiment of the present application;
FIG. 5 is a flowchart illustrating steps in a method for fabricating a trench gate MOSFET in accordance with an embodiment of the present invention;
fig. 6a to 6h are cross-sectional views of structures corresponding to relevant steps of a method for manufacturing a trench gate mosfet according to an embodiment of the present invention;
fig. 7a to 7c are cross-sectional views of structures corresponding to the steps related to forming the first doped region in an embodiment of the present application.
Description of the reference symbols
A 100 drift region; 101 a first epitaxial layer; 102 a second epitaxial layer; a 110 body region; 111 a source region; 112 a second doped region; 120 oxidation layer; 130 a first conductive structure; 140 a second conductive structure; 150 an isolation structure; 160 a second doped region; 200 interlayer dielectric layers; 310 source lead-out structure.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, the trench-gate mosfet includes a drift region 100, where the drift region 100 is formed on a semiconductor substrate, and the drift region may be formed by epitaxially growing the semiconductor substrate. The drift region 100 has a body region 110 formed on an upper surface thereof, and the body region 110 has an active region 111 formed on an upper surface thereof.
The source region 111 is opened with a trench penetrating the source region 111 and the body region 110 and extending into the drift region 100, i.e., the bottom end of the trench is located in the drift region 100. The trench is filled with a first conductive structure 130 and a second conductive structure 140 which are isolated from each other, and oxide layers 120 are formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench, wherein the oxide layer 120 between the first conductive structure 130 and the inner wall of the trench is a gate oxide layer, the oxide layer between the second conductive structure 140 and the inner wall of the trench is an isolation oxide layer, and the oxide layer 120 filled in the trench and the first conductive structure 130 and the second conductive structure 140 which are isolated from each other jointly form a filling structure. In the same trench, the depth of the first conductive structure 130 is greater than the depth of the second conductive structure 140, that is, the distance from the first conductive structure 130 to the bottom of the trench is less than the distance from the second conductive structure 140 to the bottom of the trench, and the portion of the first conductive structure 130 having the depth exceeding the depth of the bottom of the second conductive structure 140 is defined as a field plate adjusting structure, that is, the portion of the first conductive structure located below the second conductive structure 140 is a field plate adjusting structure.
The drift region 100 further has a first doped region 160 formed therein, the top of the first doped region 160 is connected to the body region 110, the first doped region 160 is spaced apart from the trench, the bottom depth of the first doped region 160 exceeds the top depth of the field plate adjustment structure, i.e. there is an overlap region between the first doped region 160 and the field plate adjustment structure in the lateral projection.
The trench gate mosfet further includes a source lead-out structure 310 and a gate lead-out structure (not shown), where the source lead-out structure 310 and the gate lead-out structure may be metal pillars, and may be tungsten metal. The source lead-out structure 310 is connected to the source region 111 and the body region 110, and the gate lead-out structure is connected to the second conductive structure 140 in the trench.
The drift region 100 and the source region 111 have a first conductivity type, and the body region 110 and the first doped region 160 have a second conductivity type. The first conductive type is an N type, and the second conductive type is a P type; or the first conduction type is P type, and the second conduction type is N type. It is understood that the front surface of the trench gate mosfet further has a source metal layer and a gate metal layer which are isolated from each other, the source lead-out structures 310 are connected to the source metal layer, the gate lead-out structures are connected to the gate metal layer, and a drain metal layer is further formed on the back surface of the trench gate mosfet.
In the trench gate mosfet, on one hand, the top source region 111 is connected to the source metal layer through the source lead-out structure 310, the bottom drift region 100 is connected to the drain metal layer as the drain region, the body region 110 in the middle of the trench forms the channel region, the trench penetrates through the body region 110 and extends into the drift region 100, the oxide layer 120 and the second conductive structure 140 are arranged in the trench and the second conductive structure 140 is connected to the gate metal layer through the gate lead-out structure, that is, the trench and the gate oxide layer and the second conductive structure 140 therein form a trench gate structure, thereby forming the trench gate mosfet. By means of this trench-gate structure, a longitudinal conducting channel can be formed in the body region 110.
On the other hand, the first conductive structure 130 is further formed in the bottom of the trench, the portion of the first conductive structure located below the second conductive structure 140 is a field plate adjusting structure, the field plate adjusting structure and the isolation oxide layer in contact with the field plate adjusting structure form an inner field plate, so that the electric field distribution in the drift region 100 can be adjusted, the drift region in contact with the inner field plate forms a depletion region, and the depletion of the drift region 100 is enhanced. And a first doped region 160 is further formed in the drift region 100, the first doped region 160 has a source potential and a conductivity type opposite to that of the drift region 100, the first doped region 160 and the drift region 100 form an inverse PN junction, so that the drift region in contact with the first doped region 160 also forms a depletion region, further enhancing the depletion of the drift region 100. Meanwhile, in the present application, the bottom depth of the first doping region 160 exceeds the top depth of the field plate adjustment structure, so that the depletion region formed by the first doping region 160 and the depletion region formed by the inner field plate are laterally distributed side by side, further increasing the withstand voltage of the drift region 100. Compared with a common trench gate metal oxide semiconductor field effect transistor, the trench gate metal oxide semiconductor field effect transistor in the application has higher breakdown voltage, namely, under the condition that the same breakdown voltage is ensured, the drift region 100 of the trench gate metal oxide semiconductor field effect transistor in the application can have higher doping concentration, and therefore the trench gate metal oxide semiconductor field effect transistor in the application also has lower on-resistance. Meanwhile, in the trench, the first conductive structure 130 connected to the source metal layer is closer to the bottom of the trench than the second conductive structure 140 connected to the gate, so that the parasitic capacitance between the gates and the drain can be reduced, and the device has better characteristics.
In one embodiment, as shown in fig. 2, the sidewalls of the first doped region 160 include a first portion 161 extending downward from the bottom of the body region 110 and a first portion 162 extending downward from the first portion, wherein the first portion 161 is parallel to the sidewalls of the trench, the longitudinal cross-section of the first portion 161 is rectangular, and the first portion 161 is spaced apart from the sidewalls of the trench; the second portion 162 is gradually inclined from top to bottom toward the inside of the first doped region 160, the longitudinal section of the second portion 162 is in an inverted trapezoid or an inverted triangle, and the distance between the second portion 162 and the sidewall of the trench gradually increases from top to bottom. At the same time, the interface of the first portion 161 and the second portion 162 (shown in dashed lines in fig. 2) passes through the field plate adjustment structure, i.e., through the first conductive structure 130 within the trench but not through the second conductive structure 140. In this application, the first doped region 160 is spaced apart from the trench, that is, the first doped region 160 is spaced apart from the trench gate, so as to pass the current between the drain and the source. In the mosfet, since the body region 110 only forms a narrower channel region near the trench sidewall for current to pass through, the current density near the trench is also the largest in the drift region 100, and the farther away from the trench, the smaller the current density, and the first doped region 160 can be disposed in a region with a small current density to reduce the current blocking effect, i.e., increasing the distance between the first doped region 160 and the trench is beneficial to reducing the on-resistance of the VDMOS. However, the larger the distance between the first doping region 160 and the field plate adjustment structure is, the larger the spacing between adjacent depletion layers is, and thus the weaker the withstand voltage capability is. In this embodiment, the shape of the first doped region 160 is further improved, so that the distance between the upper sidewall of the first doped region 160 and the field plate adjusting structure is smaller, a densely distributed depletion layer is formed, and the lower sidewall gradually inclines inward to increase the distance between the first doped region and the trench, that is, to reduce the area of the first doped region 160, thereby reducing the on-resistance of the device while ensuring the voltage endurance capability. Furthermore, the depletion layer formed by the first doped region 160 and the depletion layer formed by the inner field plate extend all around and then are connected with each other, so that the voltage withstanding effect is better.
In one embodiment, as shown in fig. 1, the mosfet has a plurality of first doped regions 160 and a plurality of trenches, each of the trenches is filled with the filling structure, and the first doped regions 160 and the trenches are alternately disposed. In this embodiment, a plurality of trenches are provided to form a plurality of trench gate structures, which can increase current density, and a first doped region is provided between each trench, so that the distribution density of the depletion region is increased under the combined action of the first doped region and the field plate in the trench, thereby further improving the withstand voltage.
Further, as shown in fig. 3a, a cross-sectional view taken along a section line AA' in fig. 1 in one embodiment is shown, wherein the cross-section of the trench is a long bar shape, and a plurality of first doping regions 160 are disposed between adjacent trenches and spaced side by side along the length direction of the trench. In this embodiment, the first doping region 160 disposed between adjacent trenches is segmented, so that the occupied space of the first doping region 160 can be reduced, thereby reducing the on-resistance of the device. In one embodiment, the depletion regions formed by the adjacent first doping regions 160 extend to the periphery and are connected to each other, so as to reduce the on-resistance and increase the withstand voltage of the device.
In another embodiment, as shown in FIG. 3b, a cross-sectional view taken along the line AA' of FIG. 1 shows another embodiment, wherein the cross-section of the trench is a long strip, a first doped region 160 is between adjacent trenches, and the first doped region 160 is a long strip. In this embodiment, a strip-shaped first doping region 160 is disposed between adjacent trench gate structures, so that the depletion capability of the first doping region 160 to the drift region 100 can be enhanced, and the device withstand voltage can be enhanced.
In an embodiment, as shown in fig. 1, an interlayer dielectric layer 200 is further formed on the source region 111 and the trench, the interlayer dielectric layer 200 may be specifically silicon oxide, and the source lead-out structure 310 penetrates through the interlayer dielectric layer 200 and the source region 111 and extends into the body region 110 to connect with the source region 111 and the body region 110. The gate lead-out structure is formed right above the trench, penetrates through the interlayer dielectric layer 200 and is connected with the second conductive structure 140 in the trench. Furthermore, the grid electrode leading-out structure and the source electrode leading-out structure are arranged in a staggered mode so as to be connected with the grid electrode metal layer and the source electrode metal layer respectively. The first conductive structure 130 may be an uncharged floating structure, forming a floating inner field plate, or may be electrically connected to the source electrode, forming a charged inner field plate.
In an embodiment, when the source leading-out structure 310 is manufactured, a source contact hole needs to be formed, and in an actual process, the first doped region 160 is formed by injecting doped ions into the drift region through the source contact hole, so that the first doped region 160 is specifically formed in an orthographic projection region of the source leading-out structure 310, or covers an orthographic projection region of the source leading-out structure 310 and is uniformly spread out from the orthographic projection region to the periphery.
In an embodiment, as shown in fig. 1, a second doped region 112 is further formed in the body region 110, the second doped region 112 has the second conductivity type, and the doping concentration of the second doped region 112 is higher than that of the body region 110, the second doped region 112 is specifically located below the source region 111 and spaced apart from the trench, the source lead-out structure 310 penetrates through the source region 111 and extends into the second doped region 112, the source lead-out structure 310 is connected to the source region 111, and the bottom of the source lead-out structure is surrounded by the second doped region 112, so as to reduce the contact resistance between the source lead-out structure 310 and the body region 110.
The distribution of the first conductive structure 130 and the second conductive structure 140 in the trench 120 has various designs. In one embodiment, as shown in fig. 1, in the trench, the first conductive structure 130 is distributed at the bottom of the trench, the second conductive structure 140 is distributed at the top of the trench, and the first conductive structure 130 and the second conductive structure 140 are isolated by the isolation structure 150, wherein the oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench. Specifically, the isolation structure 150 is silicon oxide. In this embodiment, the first conductive structure 130 at the bottom of the trench can adjust the electric field of the drift region, enhance depletion of the drift region, and also weaken parasitic capacitance between gates and drains, thereby improving device performance. Further, as shown in fig. 1, inside the trench, the top surface of the first conductive structure 130 and the bottom surface of the second conductive structure 140 are approximately flat surfaces. In another embodiment, as shown in fig. 4a, the middle of the top surface of the first conductive structure 130 protrudes outward and the middle of the bottom surface of the second conductive structure 140 is recessed inward in the trench to correspond to the protrusion of the first conductive structure 130.
In one embodiment, as shown in fig. 4b, in the trench, the first conductive structure 130 extends from the top of the trench to the bottom of the trench, an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench, the second conductive structure 140 is formed in the oxide layer 120 on both sides of the first conductive structure 130, the first conductive structure 130 and the second conductive structure 140 are separated by the oxide layer 120, and the depth of the first conductive structure 130 extending to the bottom of the trench is greater than the depth of the second conductive structure 140 extending to the bottom of the trench. In the present embodiment, the second conductive structure 140 is disposed in the oxide layer 120, so that the thickness of the oxide layer 120 can be increased, thereby enhancing the device withstand voltage.
The application also relates to a preparation method of the trench gate metal oxide semiconductor field effect transistor, as shown in fig. 5, the preparation method comprises the following steps:
step S510: a semiconductor substrate is provided and a drift region having a first conductivity type is formed on the semiconductor substrate.
Step S520: the method comprises the steps that a groove is formed in a drift region, an oxide layer is formed on the inner wall of the groove, a first conductive structure and a second conductive structure which are isolated from each other are filled in the groove, the depth of the bottom of the first conductive structure is larger than that of the bottom of the second conductive structure, and the part, with the depth exceeding that of the bottom of the second conductive structure, of the first conductive structure is defined as a field plate adjusting structure.
As shown in fig. 6a, a drift region 100 having a first conductivity type is formed by doping a semiconductor substrate, and particularly, an epitaxial layer on the semiconductor substrate is doped to form the drift region 100 on the epitaxial layer.
Through the photolithography and etching processes, a trench is opened in the drift region 100, and the trench is filled with a filling structure. Since the structures of the first conductive structure 130 and the second conductive structure 140 in the trench have various forms, accordingly, the steps of forming the first conductive structure 130 and the second conductive structure 140 in the trench also have various embodiments. In one embodiment, step S520 may include the following steps:
step S521: and forming a groove on the drift region, and forming an oxide layer on the inner wall of the groove.
As shown in fig. 6a, an oxide layer 120 is formed on the inner wall of the trench, and specifically, the oxide layer 120 may be formed by thermal oxidation.
Step S522: and filling the first conductive structure into the groove.
Step S523: and etching the first conductive structure and the oxide layer positioned at the top of the groove, and reserving the first conductive structure and the oxide layer at the bottom of the groove.
As shown in fig. 6b, the first conductive structure 130 is filled in the trench, and the first conductive structure may be formed by a deposition process. The first conductive structure and the oxide layer at the top of the trench are etched, leaving the first conductive structure 130 at the bottom of the trench and the oxide layer 120 between the first conductive structure 130 and the sidewalls of the trench.
Step S524: and forming an isolation structure in the groove, wherein the isolation structure covers the first conductive structure at the bottom of the groove and does not fill the groove.
As shown in fig. 6c, an isolation structure 150, which may be specifically silicon oxide, is deposited in the trench by a deposition process, wherein the isolation structure 150 covers the first conductive structure 130 and does not fill the trench.
Step S525: and forming an oxide layer on the side wall of the groove above the isolation structure and filling the groove with a second conductive structure.
As shown in fig. 6d, an oxide layer is formed on the sidewall of the trench above the isolation structure 150 and the second conductive structure 140 is filled in the trench, the second conductive structure 140 is isolated from the inner wall of the trench by the oxide layer 120, and the second conductive structure 140 is isolated from the first conductive structure 130 by the isolation structure 150. In the filling structure formed in the steps S521 to S525, the first conductive structure 130 at the bottom of the trench is the field plate adjusting structure.
Step S530: doping the upper surface layer of the drift region to form a body region which is in contact with the side wall of the groove and has a second conduction type, wherein the depth of the body region is smaller than that of the groove; and doping the upper surface layer of the body region to form a source region with the first conductivity type, wherein the source region is in contact with the side wall of the groove.
As shown in fig. 6e, the upper surface of the drift region 100 is doped to form body regions 110 of the second conductivity type in contact with the trench sidewalls, the depth of the body regions 110 being smaller than the depth of the trench, i.e. the bottom of the trench is still located within the drift region 100. The upper surface layer of the body region 110 is doped to form a source region 111 having the first conductive type contacting the sidewall of the trench.
Step S540: and forming a first doped region with a second conduction type in the drift region, wherein the first doped region is connected with the body region, the first doped region is arranged at an interval with the groove, and the bottom depth of the first doped region exceeds the top depth of the field plate adjusting structure.
As shown in fig. 6e and 6f, in an embodiment, between step S530 and step S540, forming an interlayer dielectric layer 200 on the source region 111 and the trench, and sequentially etching the interlayer dielectric layer 200, the source region 111, and the body region 110 on both sides of the trench to form a source contact hole, where the source contact hole is spaced from the trench. In step S540, specifically, doping ions having the second conductivity type are implanted into the drift region through the source contact hole, and a first doping region 160 contacting the body region 110 is formed in the drift region, at this time, a projected area of the first doping region 160 is the same as a projected area of the source contact hole. In one embodiment, after the first doped region 160 is formed in the drift region 100 by implanting the dopant ions having the second conductivity type through the source contact hole, the second doped region 112 is formed on the surface layer of the body region by further continuing to implant the dopant ions having the second conductivity type through the source contact hole.
Step S550: and forming a source electrode lead-out structure connected with the source region and the body region, and forming a grid electrode lead-out structure connected with the second conductive structure.
As shown in fig. 6h, a source lead-out structure 310 connected to the source region 111 and the body region 110 is formed, and a gate lead-out structure (not shown) connected to the second conductive structure 140 is formed. In one embodiment, when the active contact hole is formed before step S550, in step S550, the source lead-out structure 310 may be formed by filling a conductive material into the active contact hole. In an embodiment, when the second doped region 112 is formed in the body region 110 through the source contact hole, the source contact hole is filled with a conductive material to form the source extraction structure 310, and the bottom of the source extraction structure 310 is surrounded by the second doped region 112, so that the contact resistance between the source extraction structure 310 and the body region can be reduced.
In the above embodiment, the first doping region 160 is formed in the drift region 100 at the source contact hole by an implantation process, in other embodiments, the drift region 100 is grown by an epitaxial process, and the first doping region 160 is formed during the epitaxial growth process, which may specifically be implemented by two ways:
the first mode is as follows:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
doping the first epitaxial layer to form a first doped region with a second conductivity type;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
As shown in fig. 7a to 7c, a first epitaxial layer 101 is epitaxially grown on a semiconductor substrate, then a specific region of the first epitaxial layer 101 is doped with a second conductivity type to form a first doped region 160 with the second conductivity type, and a second epitaxial layer 102 is further epitaxially grown on the first epitaxial layer 101 and the first doped region 160, so that the first epitaxial layer 101 and the second epitaxial layer 102 form a desired drift region 110, and at this time, the first doped region 160 is formed inside the drift region 110.
The second mode is as follows:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
forming a shallow groove on the first epitaxial layer, and epitaxially growing a first doped region with a second conductivity type in the shallow groove;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
The second embodiment is different from the first embodiment in that the first doped region 160 is formed in the first epitaxial layer 101, in the first embodiment, the first doped region 160 is formed by directly doping a specific region of the first epitaxial layer 101, and in the second embodiment, a shallow trench is formed in the specific region, and then the first doped region 160 having the second conductivity type is epitaxially grown in the shallow trench. It should be noted that the first doping region can be formed in any of the above manners, and can be flexibly selected according to specific conditions.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A trench gate MOSFET comprising:
a drift region having a first conductivity type formed on the semiconductor substrate;
the body region is provided with a second conduction type and is formed on the upper surface layer of the drift region;
the source region is provided with a first conduction type and is formed on the upper surface layer of the body region;
the groove penetrates through the source region and the body region in sequence and extends into the drift region;
the filling structure comprises a first conductive structure and a second conductive structure which are filled in the groove and are isolated from each other, and oxide layers which are formed between the first conductive structure and the inner wall of the groove and between the second conductive structure and the inner wall of the groove, wherein the depth of the bottom of the first conductive structure exceeds the depth of the bottom of the second conductive structure, and the part of the first conductive structure, the depth of which exceeds the depth of the bottom of the second conductive structure, is defined as a field plate adjusting structure;
the first doping region is formed in the drift region and connected with the lower surface of the body region, the first doping region and the groove are arranged at intervals, and the bottom depth of the first doping region exceeds the top depth of the field plate adjusting structure;
the source electrode lead-out structure is connected with the source region and the body region; and
and the grid electrode leading-out structure is connected with the second conductive structure.
2. The mosfet of claim 1, wherein the sidewalls of the first doped region comprise a first portion extending downward from the bottom of the body region parallel to the trench sidewalls and a second portion extending downward from the first portion and tapering inward into the first doped region, wherein an interface of the first portion and the second portion crosses the field plate adjustment structure.
3. The mosfet of claim 1, wherein the mosfet has a plurality of the first doped regions and a plurality of the trenches, each trench is filled with the filling structure, and the first doped regions and the trenches are alternately spaced apart along a width direction of the trench.
4. The mosfet of claim 3 wherein the cross-section of the trench is elongated and a plurality of the first doped regions are spaced apart along the length of the trench between adjacent trenches.
5. The mosfet of claim 1, further comprising:
an interlayer dielectric layer formed on the source region and the top surface of the trench;
the source electrode lead-out structure penetrates through the interlayer dielectric layer and the source region and extends into the body region to be respectively connected with the source region and the body region;
the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second conductive structure.
6. The mosfet of claim 1 wherein a second doped region is formed in the body region, the second doped region having a second conductivity type and having a higher doping concentration than the body region, the second doped region being under the source region and spaced apart from the trench, the source extension structure penetrating the source region and extending into the second doped region.
7. A method for preparing a trench gate metal oxide semiconductor field effect transistor is characterized by comprising the following steps:
providing a semiconductor substrate and forming a drift region with a first conductivity type on the semiconductor substrate;
forming a groove on the drift region, forming an oxide layer on the inner wall of the groove, and filling a first conductive structure and a second conductive structure which are isolated from each other in the groove, wherein the depth of the bottom of the first conductive structure is greater than that of the bottom of the second conductive structure, and the part of the first conductive structure, the depth of which exceeds that of the bottom of the second conductive structure, is defined as a field plate adjusting structure;
doping the upper surface layer of the drift region to form a body region which is in contact with the side wall of the groove and has a second conduction type, wherein the depth of the body region is smaller than that of the groove; doping the upper surface layer of the body region to form a source region which is in contact with the side wall of the groove and has a first conductive type;
forming a first doped region with a second conductivity type in the drift region, wherein the first doped region is connected with the lower surface of the body region, the first doped region is arranged at an interval with the trench, and the bottom depth of the first doped region exceeds the top depth of the field plate adjusting structure; and
and forming a source electrode lead-out structure connected with the source region and the body region, and forming a grid electrode lead-out structure connected with the second conductive structure.
8. The method of claim 7, further comprising, after said step of doping an upper surface of said body region to form source regions of first conductivity type in contact with said trench sidewalls:
forming an interlayer dielectric layer on the source region and the groove;
sequentially etching the interlayer dielectric layer, the source region and the body region to form a source contact hole penetrating through the dielectric layer and the source region and extending to the body region;
the first doped region connected with the lower surface of the body region is formed in the drift region, and the first doped region comprises: implanting doping ions with a second conductivity type into the drift region through the source contact hole, and forming a first doping region connected with the lower surface of the body region in the drift region;
the forming of the source lead-out structure connected to the source region, the body region and the first conductive structure includes: and filling a conductive material into the source contact hole to form the source electrode lead-out structure.
9. The method of claim 7, wherein forming a first doped region having a second conductivity type within the drift region comprises:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
doping the first epitaxial layer to form a first doped region with a second conductivity type;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
10. The method of claim 7, wherein forming a first doped region having a second conductivity type within the drift region comprises:
epitaxially growing a first epitaxial layer on the semiconductor substrate;
forming a shallow groove on the first epitaxial layer, and epitaxially growing a first doped region with a second conductivity type in the shallow groove;
and continuously epitaxially growing a second epitaxial layer on the first epitaxial layer and the first doped region, wherein the drift region comprises the first epitaxial layer and the second epitaxial layer.
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| CN202010418876.3A CN114361247A (en) | 2020-05-18 | 2020-05-18 | Trench gate metal oxide semiconductor field effect transistor and preparation method thereof |
| PCT/CN2020/140672 WO2021232813A1 (en) | 2020-05-18 | 2020-12-29 | Trench gate metal oxide semiconductor field effect transistor, and manufacturing method thereof |
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| US8067800B2 (en) * | 2009-12-28 | 2011-11-29 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with resurf step oxide and the method to make the same |
| US8648413B2 (en) * | 2009-12-28 | 2014-02-11 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched source-body contacts |
| CN103137698B (en) * | 2011-11-23 | 2016-04-27 | 力士科技股份有限公司 | A kind of mos field effect transistor and manufacture method |
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