CN114268400B - PTP network time service system based on E1 optical fiber - Google Patents
PTP network time service system based on E1 optical fiber Download PDFInfo
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- CN114268400B CN114268400B CN202111364884.5A CN202111364884A CN114268400B CN 114268400 B CN114268400 B CN 114268400B CN 202111364884 A CN202111364884 A CN 202111364884A CN 114268400 B CN114268400 B CN 114268400B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a PTP network time service system based on an E1 optical fiber, which adopts a mode of combining E1 with PTP network time service to externally time service so as to improve the time service precision of E1. The network time service system comprises: ARM processor, FPGA module and E1 modulation demodulation chip; the ARM processor is used for analyzing the PTP synchronous message and realizing a time service synchronous algorithm; the FPGA module is used for stamping a time stamp on the PTP synchronous message and converting network interface data into serial interface data meeting E1 communication; and the E1 modem chip is used for modem between serial interface data and HB3 codes, so as to realize the function of data optical fiber transmission.
Description
Technical Field
The invention relates to a time service method, in particular to a PTP network time service system based on an E1 optical fiber, and belongs to the technical field of communication and precise time service.
Technical Field
With the high-speed development of the fields of intelligent digital power grids, 4G and 5G high-speed communication networks, national defense, military industry, industrial control and the like, the requirements on high-precision time references are higher and higher, and the high-precision time references are obtained by a high-precision clock synchronization technology. The high-precision time service synchronization can be carried out between the large-scale systems with long distance by satellite means such as GPS and Beidou, however, the small-scale systems inside the large-scale systems cannot carry out the clock synchronization by applying the satellite technology on a large scale due to objective reasons such as cost, maintenance, environmental factors and the like, so that other clock synchronization modes such as E1, IRIG-B codes, NTP, PTP and the like can only be selected in the small-scale systems. NTP is most widely used with the advantages of earliest time of occurrence, lowest cost, lowest implementation difficulty, etc. However, the accuracy of NTP timing can only reach ms level, and the stability of clock synchronization is poor due to the influence of jitter of network protocol stack, which is difficult to meet the demands in many application scenarios. And secondly, IRIG-B codes, the clock synchronization precision of which can reach us level, can meet the clock synchronization requirement of most small-sized systems. IRIG-B codes have their obvious drawbacks such as requiring special wiring making post maintenance and upgrades difficult. In recent years, a PTP clock synchronization technology, namely an IEEE1588 clock synchronization technology, has been developed, so that the clock synchronization time service precision is greatly improved, and the stability is greatly improved.
In early military products, E1 adopts a mode of combining with IRIG-B code time service and uses a Bettv line for transmission time service, and when two devices are far away, the on-line signal quality is poor, the line delay is increased, and the synchronization precision is affected. With the increasing requirement on the synchronization precision, the E1 combined with IRIG-B code time service technology cannot meet the requirement, and the E1 link time service is required to be upgraded and modified.
Disclosure of Invention
In view of this, the present invention provides a PTP network time service system based on E1 optical fiber, which adopts a mode of combining E1 with PTP network time service to externally time service, so as to improve the time service precision of E1.
The E1 optical fiber based PTP network time service system comprises: ARM processor, FPGA module and E1 modulation demodulation chip;
the ARM processor is used for analyzing the PTP synchronous message and realizing a time service synchronous algorithm;
the FPGA module is used for stamping a time stamp on the PTP synchronous message and converting network interface data into serial interface data meeting E1 communication;
the E1 modem chip is used for modem between serial interface data and HB3 codes, and realizes the function of data optical fiber transmission. The method comprises the following steps: the E1 modem chip modulates serial interface data transmitted by the FPGA module into HB3 codes, and then is connected with an optical transceiver to realize an optical fiber transmission function; in addition, HB3 codes received from the optical transceiver are demodulated into serial interface data and sent to the FPGA module.
As a preferred mode of the invention, when the network time service system is used as a master clock, the FPGA module only carries out time stamping on the received Sync message and the delay_Req message, and other messages are transmitted in a transparent way; the method comprises the following steps:
when the FPGA module detects a Sync message from a message sent by an ARM processor, recording t1 timestamp information of the Sync message, and then sending the Sync message comprising the t1 timestamp information to a slave clock end; simultaneously informing the ARM processor to read t1 time stamp information of the Sync message, and after acquiring t1 time, putting the information into a Follow_Up message and sending the information to a slave clock end through the FPGA module by the ARM processor; when the FPGA module receives a message sent from a slave clock end and detects a delay_req message, recording time stamp information of the arrival time t4 of the message, filling the delay_req message with the t4 time stamp information, and sending the time stamp information to an ARM processor, wherein the ARM processor extracts the t4 time stamp information from the received delay_req message, and then sends the time stamp information to the slave clock end through the FPGA module in the delay_resp message;
when the network time service system is used as a slave clock, the FPGA module only marks a time stamp on the received Sync and the sent delay_Req message, and other messages are transmitted in a transparent way; the method comprises the following steps:
when the FPGA module detects a Sync message from a received message, t2 timestamp information of the arrival time of the Sync message is recorded, then the t2 timestamp information is filled in the Sync message and is sent to the ARM processor, and the ARM processor extracts the t2 timestamp information from the received Sync message for time service synchronous calculation; when the FPGA module detects the delay_req message from the message sent by the ARM processor, t3 time stamp information of the delay_req message is recorded, and then the ARM processor is informed to read the t3 time stamp information of the delay_req message for calculation.
As a preferred mode of the present invention, the FPGA module further includes an error protection mechanism: the FPGA module always sends error-preventing bytes to the E1 modem chip when no network message is transmitted, so that the E1 modem chip is always in a non-idle state; the error-proof byte sets the bytes of the format.
As a preferred mode of the invention, the FPGA module always sends 0x7E to E1 modem chips when no network message is transmitted.
As a preferred mode of the present invention, the FPGA module further includes an encryption mechanism: the FPGA module replaces error-proof bytes in the received network message with bytes in a set format, and the bytes are encrypted, so that the message is encrypted; then converting the serial interface data into serial interface data meeting E1 communication and sending the serial interface data to an E1 modem chip;
after receiving serial interface data sent by an E1 modem chip, the FPGA module forms byte messages with the serial interface data; when the message has non-error-proof bytes, the message is received, and the encryption bytes in the received message are respectively replaced with the error-proof bytes correspondingly, so that the decryption of the message is realized.
As a preferable mode of the invention, when the FPGA module receives the PTP synchronous message and the common Ethernet message at the same time, the FPGA module preferentially transmits the PTP synchronous message.
As a preferable mode of the invention, when the FPGA module receives the message, the message type judgment is firstly carried out, and then the PTP synchronous message and the common Ethernet message are stored separately.
Advantageous effects
(1) By adopting the PTP network time service system based on the E1 optical fiber, the synchronization precision can be improved while the synchronization precision is not influenced when the line is lengthened.
(2) An FPGA module is arranged between the ARM processor and the E1 modem chip, and the FPGA module is used for stamping a time stamp on the PTP synchronous message at the position closest to the port, so that time service precision is ensured.
Drawings
FIG. 1 is a schematic diagram of the system as a master clock and a slave clock respectively;
fig. 2 is a functional block diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The embodiment provides a PTP network time service system based on an E1 optical fiber, which combines E1 with PTP network time service to perform external time service so as to improve the time service precision of E1.
As shown in fig. 1, the E1 optical fiber PTP network timing system adopts a frame structure of an ARM processor+fpga module+e1 chip to implement a network timing function, that is, the network timing system includes: ARM processor, FPGA module and E1 modulation demodulation chip; the ARM processor is responsible for the analysis of PTP messages and the realization of a time service synchronization algorithm, and the FPGA module realizes the function of time stamping the PTP network time service messages and the function of converting a network MII interface into a serial interface which meets E1 communication; e1 modem chip modulates the message transmitted by FPGA into HB3 code, then connects the optical transceiver, realizes the optical fiber transmission function. The network time service system can be used as a master clock or a slave clock.
Specific:
the ARM processor uses the existing mature PTP network timing technology to realize the analysis and timing synchronization algorithm of the PTP message; the ARM processor periodically sends network messages to the FPGA module. When the system is in a main clock mode, the ARM processor periodically sends Sync and Follow_up messages to the FPGA module; when the system is a slave mode clock, after the ARM processor receives the Sync and Follow_Up messages sent by the master clock end, the ARM processor sends a delay_req message to the FPGA module.
The FPGA module mainly realizes the processing of PTP message time service time stamp and interface protocol conversion function, and has 15 submodules, namely:
a sending message type judging module: the method is used for judging the message types (including PTP synchronous messages and common Ethernet messages) sent by the ARM processor, then the PTP synchronous messages are sent to a PTP message sending storage module, and the common Ethernet messages are sent to a common message sending storage module so as to realize separate storage of the PTP synchronous messages and the common Ethernet messages.
And a general report message storage module is sent: the system is used for storing common Ethernet messages and sending the common Ethernet messages to the sending control module.
The PTP message transmitting storage module: and the device is used for storing the PTP synchronous message and sending the PTP synchronous message to the time stamp unit.
A transmission time stamp unit: the device is used for stamping a time stamp on the received PTP synchronous message; as shown in fig. 1, when the network time service system is used as a master clock, PTP synchronous messages needing to be time stamped are Sync messages; when the network time service system is a slave clock, the PTP synchronous message needing to be time stamped is a delay_req message; and then sending the PTP synchronous message with the time stamp to a control module.
And a transmission control module: the E1 error-proofing encryption module is used for transmitting the PTP message and the common Ethernet message; meanwhile, the transmission priority of the PTP message and the common Ethernet message is controlled: when PTP message and common Ethernet message are received at the same time, PTP message is transmitted preferentially.
E1 error-proofing encryption module: the method is used for replacing 0x7E and 0x7D in network messages (including PTP synchronous messages and common Ethernet messages) with 0x7D5E and 0x7D5D respectively (other bytes can be replaced), and then sending the network messages to an E1 modem chip according to serial data conforming to E1 transmission. Meanwhile, the module always transmits 0x7E to the E1 modem chip when no network message is transmitted, so that the E1 modem chip is always in a non-idle state, signal jump is avoided to a certain extent when the network message is transmitted, and a certain error prevention mechanism is provided.
And E1 error-proofing decryption module: for receiving serial E1 data and composing it into byte messages. When the received message is not 0x7E, the received message is started, 0x7D5E and 0x7D5D in the received message are replaced by 0x7E and 0x7D respectively, and then the decrypted message is converted into a GMII interface and sent to a received message type judging module.
The receiving message type judging module: and the module is used for judging whether the current received message is a common Ethernet message or a PTP synchronous message, then transmitting the PTP synchronous message to a module for transmitting and receiving the PTP message, and transmitting the common Ethernet message to a module for receiving the common message.
And receiving a general report module: and the device is used for storing the received common network message.
A module for receiving PTP message: used for storing the received PTP synchronous message.
Receive timestamp unit: the network time service system is used for marking time stamps on received PTP synchronous messages, and when the network time service system is a master clock, the messages needing to be marked with the time stamps are delay_req messages; when the network time service system is a slave clock, the message needing to be stamped with a time stamp is a Sync message.
And a receiving control module: the device is used for transmitting the received PTP message and the common Ethernet message to the ARM processor; meanwhile, the transmission priority of the PTP message and the common Ethernet message is controlled: when PTP message and common Ethernet message are received at the same time, PTP message is transmitted preferentially.
Parameter interaction module: the method is used for realizing the function of parameter transmission between the ARM processor and the FPGA through the MDC/MDIO interface, and the interactive parameters comprise: a local time adjustment value, a pps rising edge timestamp value, an interrupt status register and a PTP master-slave mode which are interacted with the local time adjustment module; the Sync message t1 time stamp and the delay_req message t3 time stamp are interacted with the sending time stamp unit.
A local time adjustment module: the local time adjustment module of the FPGA works in a 125M clock domain, and after power-on, the local time starts from 0 and is counted up at 8ns intervals. After detecting the pps_out rising edge sent by the ARM processor, locking the local time, storing the PPS rising edge time stamp value into the PPS rising edge time stamp value register, triggering the ptp_ riq signal to inform the ARM processor to read the PPS rising edge time stamp value by using the SMI management interface, comparing the PPS rising edge time stamp value obtained by the ARM processor with the local time to calculate the relative time, informing the FPGA through the local time adjustment value register, and immediately updating the local time after receiving the local time adjustment value.
E1 chip configuration module: the method is used for configuring the working mode of the E1 modem chip to enable the E1 modem chip to work in a unipolar IO and debounce mode, and the functions of HDB3 encoding and decoding and clock recovery are achieved under the 2.048MHz clock.
The E1 modem chip works under a 2.048MHz clock and is mainly used for realizing the functions of HDB3 encoding and decoding and clock recovery.
The message time stamping operation is shown in fig. 1. When the system is used as a main clock, a time stamp unit of the FPGA only processes a Sync message sent by an ARM processor and a received delay_Req message, and other messages are transmitted in a transparent way. The method comprises the following steps: when a sending time stamp unit detects a Sync message from a message sent by an ARM processor, recording t1 time stamp information of the Sync message, and then sending the Sync message comprising the t1 time stamp information to a slave clock end; and triggering the PTP_IRQ signal to inform the ARM processor to read t1 time stamp information of the Sync message by using the SMI management port, and after acquiring t1 time, the ARM processor puts the information into a Follow_Up message and sends the information to the slave clock end through the FPGA module. The method comprises the steps that a receiving time stamp unit receives a message sent from a clock end, when the receiving time stamp unit detects a delay_req message from the received message, time stamp information of a message at a time t4 is recorded, then the t4 time stamp information is filled in the delay_req message and sent to an ARM processor, the ARM processor extracts the t4 time stamp information from the received delay_req message, and then the t4 time stamp information is placed in the delay_resp message and sent to the slave clock end through an FPGA module.
When the system is used as a slave clock, the time stamp unit only processes the received Sync and the sent delay_Req messages, and other messages are transmitted in a transparent way. When the receiving time stamp unit detects a Sync message from the received message, t2 time stamp information of the arrival time of the Sync message is recorded, then the t2 time stamp information is filled in the Sync message and is sent to the ARM processor, and the ARM processor extracts the t2 time stamp information from the received Sync message for time service synchronous calculation. When detecting the delay_req message sent by the ARM processor, the sending time stamp unit records t3 time stamp information of the delay_req message, then triggers the PTP_IRQ signal, and informs the ARM processor to read the t3 time stamp information of the delay_req message by using the SMI management port for calculation.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. PTP network time service system based on E1 optic fibre, its characterized in that includes: ARM processor, FPGA module and E1 modulation demodulation chip;
the ARM processor is used for analyzing the PTP synchronous message and realizing a time service synchronous algorithm;
the FPGA module is used for stamping a time stamp on the PTP synchronous message and converting network interface data into serial interface data meeting E1 communication;
the E1 modem chip is used for modem between serial interface data and HB3 codes, and realizes the function of data optical fiber transmission; when the network time service system is used as a master clock, the FPGA module only carries out time stamping on the received Sync message and delay_Req message, and other messages are transmitted in a transparent way; the method comprises the following steps:
when the FPGA module detects a Sync message from a message sent by an ARM processor, recording t1 timestamp information of the Sync message, and then sending the Sync message comprising the t1 timestamp information to a slave clock end; simultaneously informing the ARM processor to read t1 time stamp information of the Sync message, and after acquiring t1 time, putting the information into a Follow_Up message and sending the information to a slave clock end through the FPGA module by the ARM processor; when the FPGA module receives a message sent from a slave clock end and detects a delay_req message, recording time stamp information of the arrival time t4 of the message, filling the delay_req message with the t4 time stamp information, and sending the time stamp information to an ARM processor, wherein the ARM processor extracts the t4 time stamp information from the received delay_req message, and then sends the time stamp information to the slave clock end through the FPGA module in the delay_resp message;
when the network time service system is used as a slave clock, the FPGA module only marks a time stamp on the received Sync and the sent delay_Req message, and other messages are transmitted in a transparent way; the method comprises the following steps:
when the FPGA module detects a Sync message from a received message, t2 timestamp information of the arrival time of the Sync message is recorded, then the t2 timestamp information is filled in the Sync message and is sent to the ARM processor, and the ARM processor extracts the t2 timestamp information from the received Sync message for time service synchronous calculation; when the FPGA module detects the delay_req message from the message sent by the ARM processor, t3 time stamp information of the delay_req message is recorded, and then the ARM processor is informed to read the t3 time stamp information of the delay_req message for calculation.
2. The PTP network time service system based on E1 optical fiber of claim 1, wherein: the FPGA module is also provided with an error prevention mechanism: the FPGA module always sends error-preventing bytes to the E1 modem chip when no network message is transmitted, so that the E1 modem chip is always in a non-idle state; the error-proof byte is a byte with a set format.
3. The PTP network time service system based on E1 optical fiber of claim 2, wherein: and the FPGA module always transmits 0x7E to E1 modem chips when no network message is transmitted.
4. A PTP network time service system based on E1 optical fiber according to claim 2 or 3, wherein: the FPGA module is also provided with an encryption mechanism: the FPGA module replaces the error-proof byte in the received network message with a byte in a set format and sets the byte as an encrypted byte, so that the message is encrypted; then converting the serial interface data into serial interface data meeting E1 communication and sending the serial interface data to an E1 modem chip;
after receiving serial interface data sent by an E1 modem chip, the FPGA module forms byte messages with the serial interface data; when the message has non-error-proof bytes, the message is received, and the encryption bytes in the received message are respectively replaced with the error-proof bytes correspondingly, so that the decryption of the message is realized.
5. The PTP network time service system based on E1 optical fiber of claim 1, wherein: and when the FPGA module receives the PTP synchronous message and the common Ethernet message at the same time, the PTP synchronous message is preferentially transmitted.
6. The PTP network time service system based on E1 optical fiber of claim 1, wherein: when the FPGA module receives the message, the message type judgment is firstly carried out, and then the PTP synchronous message and the common Ethernet message are stored separately.
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