CN114256362A - Photoelectric detector and preparation method thereof - Google Patents
Photoelectric detector and preparation method thereof Download PDFInfo
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- CN114256362A CN114256362A CN202111537393.6A CN202111537393A CN114256362A CN 114256362 A CN114256362 A CN 114256362A CN 202111537393 A CN202111537393 A CN 202111537393A CN 114256362 A CN114256362 A CN 114256362A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
- H01L31/113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
- H01L31/1136—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor the device being a metal-insulator-semiconductor field-effect transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Abstract
The application provides a photoelectric detector and a preparation method thereof. The composite substrate comprises a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged on the upper surface of the grid electrode; the charge trapping layer is arranged on the upper surface of the gate insulating layer; the tunneling insulating layer is arranged on the upper surface of the charge trapping layer; the semiconductor channel is arranged on the upper surface of the tunneling insulating layer; the source electrode is arranged on the upper surface of the tunneling insulating layer; the drain electrode is arranged on the upper surface of the tunneling insulating layer; the source electrode and the drain electrode are respectively positioned at two sides of the semiconductor channel; the charge trapping layer includes a plurality of nanoparticles. According to the photoelectric detector, the photo-generated holes are filled by electrons in the charge capturing layer, so that the recombination probability of the photo-generated electron holes is greatly reduced, the sensitivity of the photoelectric detector is improved, and the detection performance of the photoelectric detector is ensured.
Description
Technical Field
The application relates to the technical field of optical sensing, in particular to a photoelectric detector and a preparation method thereof.
Background
With the increasing development of optical sensing applications, photodetectors are widely used. The photoelectric detector has wide application in various fields of military and national economy. The infrared radiation sensor is mainly used for ray measurement and detection, industrial automatic control, photometric measurement and the like in visible light or near infrared wave bands; the infrared band is mainly used for missile guidance, infrared thermal imaging, infrared remote sensing and the like.
When the photoelectric detector is actually used, incident light excites the photoelectric detector to generate photo-generated electrons; the transition of the photo-generated electrons from the valence band to the conduction band of the semiconductor increases the semiconductor carrier concentration, thereby generating a photocurrent. Wherein the photocurrent is positively correlated with the incident light intensity. However, the optical signal loss in the optical path is large with the increase of the monitoring distance and the increase of the optical path interfaces, resulting in a low intensity of the incident light received by the photodetector.
In the prior art, a high-power light source is used or an optical amplifier is used in a light path, so that the light intensity of incident light in a photoelectric detector is improved, and the detection performance of the photoelectric detector is ensured. However, this approach increases the energy consumption and the cost of the detection system, and makes the structure of the detection system more complicated.
Disclosure of Invention
An object of the embodiments of the present application is to provide a photodetector and a method for manufacturing the same, which can ensure the detection performance of the photodetector by improving the detection sensitivity of the photodetector under the weak light condition without using a high-power light source or using an optical amplifier in the light path.
In one aspect, the present application provides a photodetector comprising: the semiconductor device comprises a composite substrate, a charge trapping layer, a tunneling insulating layer, a semiconductor channel, a source electrode and a drain electrode. The composite substrate comprises a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged on the upper surface of the grid electrode; the charge trapping layer is arranged on the upper surface of the gate insulating layer; the tunneling insulating layer is arranged on the upper surface of the charge trapping layer; the semiconductor channel is arranged on the upper surface of the tunneling insulating layer; the source electrode is arranged on the upper surface of the tunneling insulating layer; the drain electrode is arranged on the upper surface of the tunneling insulating layer; the source electrode and the drain electrode are respectively positioned at two sides of the semiconductor channel; the charge trapping layer includes a plurality of nanoparticles.
In one embodiment, the diameter of the nanoparticles is 1-30 nm.
In one embodiment, the nanoparticles are metal particles, oxide particles, or semiconductor particles.
In one embodiment, the material of the nanoparticles, the source electrode and the drain electrode is the same.
In one embodiment, the nanoparticles, the source electrode and the drain electrode are made of gold.
In one embodiment, the tunneling insulation layer has a thickness of 5-20 nm, and the gate insulation layer has a thickness of 30-300 nm.
In one embodiment, the tunneling insulating layer is made of aluminum oxide, silicon dioxide or silicon nitride; the gate insulating layer is made of silicon dioxide, polystyrene or aluminum oxide; the grid is made of silicon, indium tin oxide or copper; the semiconductor channel is made of silicon, gallium arsenide, n-type indium gallium arsenide or graphene.
On the other hand, the application also provides a preparation method of the photoelectric detector, which comprises the following steps:
forming a composite substrate by the grid and the grid insulating layer;
forming a charge trap layer on an upper surface of the gate insulating layer; wherein the charge trapping layer comprises a plurality of nanoparticles, the nanoparticles being metal particles, oxide particles or semiconductor particles;
forming a tunneling insulating layer on an upper surface of the charge trapping layer;
forming a source electrode, a drain electrode and a semiconductor channel on the upper surface of the tunneling insulating layer; the source and the drain are respectively positioned at two sides of the semiconductor channel.
In one embodiment, forming a charge trapping layer on an upper surface of a gate insulating layer includes:
forming an intermediate layer on an upper surface of the gate insulating layer;
annealing the intermediate layer to form a plurality of nanoparticles, wherein the plurality of nanoparticles form a charge trapping layer;
wherein the nanoparticles are metal particles.
In one embodiment, forming a source, a drain and a semiconductor channel on the upper surface of the tunneling insulating layer, the source and the drain being respectively located at two sides of the semiconductor channel, includes:
forming a semiconductor layer on the upper surface of the tunneling insulating layer;
forming a photoresist layer on the upper surface of the semiconductor layer;
photoetching the photoresist layer to form a mask layer;
etching the semiconductor layer through the mask layer to form a first groove and a second groove;
forming a source electrode in the first groove and a drain electrode in the second groove; the semiconductor layer between the source electrode and the drain electrode is a semiconductor channel;
and removing the mask layer.
The photodetector in the present application includes a composite substrate, a charge trapping layer, a tunneling insulating layer, a semiconductor channel, a source electrode, and a drain electrode. The composite substrate comprises a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged on the upper surface of the grid electrode; the charge trapping layer is arranged on the upper surface of the gate insulating layer; the tunneling insulating layer is arranged on the upper surface of the charge trapping layer; the semiconductor channel is arranged on the upper surface of the tunneling insulating layer; the source electrode is arranged on the upper surface of the tunneling insulating layer; the drain electrode is arranged on the upper surface of the tunneling insulating layer; the source electrode and the drain electrode are respectively positioned at two sides of the semiconductor channel; the charge trapping layer includes a plurality of nanoparticles.
Therefore, electrons in the charge trapping layer can be effectively utilized to fill photo-generated holes, the recombination probability of the photo-generated electron holes is greatly reduced, effective photocurrent can be generated in the photoelectric detector, and the sensitivity of the photoelectric detector is improved. Meanwhile, a high-power light source or an optical amplifier is not needed to be used in the light path, and the detection performance of the photoelectric detector can be ensured by improving the detection sensitivity of the photoelectric detector under the condition of weak light.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below.
Fig. 1 is a schematic structural diagram of a photodetector according to an embodiment of the present application;
fig. 2 is a schematic diagram of an operation of a photodetector according to an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for manufacturing a photodetector according to an embodiment of the present disclosure;
fig. 4 is a schematic detailed flowchart of step S240 according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating a method for manufacturing a photodetector according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a method for manufacturing a photodetector according to an embodiment of the present disclosure;
fig. 7 is a schematic view of a method for manufacturing a photodetector according to an embodiment of the present disclosure.
Reference numerals:
10-a composite substrate; 11-a gate insulating layer; 12-a gate; 20-a charge trapping layer; 21-nanoparticles; 30-a tunneling insulating layer; a 40-drain electrode; 41-a first trench; a 50-source electrode; 51-a second trench; 60-a semiconductor channel; 61-conduction band; a 62-valence band; 63-a semiconductor layer; 70-a photoresist layer; 71-a mask layer; 100-photodetector.
Detailed Description
The terms "first," "second," "third," and the like are used for descriptive purposes only and not for purposes of indicating or implying relative importance, and do not denote any order or order.
Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally arranged when products of the application are used, and are used only for convenience in describing the application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the application.
In the description of the present application, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements.
The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a photodetector according to an embodiment of the present application. Fig. 2 is a schematic diagram of a photodetector according to an embodiment of the present disclosure. Referring to fig. 1, a photodetector 100 includes a composite substrate 10, a charge trapping layer 20, a tunneling insulating layer 30, a drain 40, a source 50, and a semiconductor channel 60. The composite substrate 10 includes a gate insulating layer 11 and a gate 12.
The gate insulating layer 11 is arranged on the upper surface of the gate 12; the charge trapping layer 20 is disposed on the upper surface of the gate insulating layer 11; the tunneling insulating layer 30 is disposed on the upper surface of the charge trapping layer 20; the semiconductor channel 60 is arranged on the upper surface of the tunneling insulating layer 30; the source electrode 50 is arranged on the upper surface of the tunneling insulating layer 30; the drain electrode 40 is arranged on the upper surface of the tunneling insulating layer 30; the source electrode 50 and the drain electrode 40 are respectively located at two sides of the semiconductor channel 60, and the charge trapping layer 20 includes a plurality of nanoparticles 21.
The gate 12 is made of high conductivity silicon, indium oxide, copper, gold, silver, or the like. The gate electrode 12 may be any metal material having a conductive property.
The thickness of the gate insulating layer 11 is 30-300 nm; the gate insulating layer 11 may be made of silicon dioxide, polystyrene, silicon nitride, or the like.
The diameter of the nano-particles 21 is 1-30 nanometers; the nanoparticles 21 may be metal particles, oxide particles or semiconductor particles. The nanoparticles 21 may also be quantum dots composed of semiconductor particles.
The thickness of the tunneling insulating layer 30 is 5-20 nanometers; the tunneling insulating layer 30 may be an insulating material such as aluminum oxide, silicon dioxide, silicon nitride, or other organic molecules.
The semiconductor channel 60 may be a semiconductor material such as silicon, gallium arsenide, n-type indium gallium arsenide, or graphene. The semiconductor channel 60 may be made of a topological insulator, a transition metal chalcogenide, or the like. The structure of the semiconductor channel 60 may be a nanowire or a nanoribbon, etc.
The length of the semiconductor channel 60 is 20 μm or less. The thickness of the semiconductor channel 60 is 50 nm or less. The source electrode 50 and the drain electrode 40 are each greater than 5 nanometers thick.
By the above measures, the sizes of the semiconductor channel 60, the source electrode 50 and the drain electrode 40 are limited, so that the conductivity of the photodetector 100 can be improved, and the detection performance of the photodetector 100 can be improved.
In one embodiment, the nanoparticles, the source and the drain are made of the same material. For example, the material of the nanoparticles, the source electrode and the drain electrode may be all metal.
In one embodiment, the nanoparticles, the source electrode and the drain electrode are made of gold.
In one embodiment, the material of the nanoparticles, the source electrode and the drain electrode can be freely selected according to the requirement.
The thicknesses mentioned in the above embodiments are all the dimensions in the vertical direction shown in fig. 1; the lengths mentioned in the above embodiments are all the horizontal dimensions shown in fig. 1.
The photodetector 100 may sense a change in the intensity of light. Thus, the photodetector 100 may be used in conjunction with a sensing element, such as a fiber optic sensor, for measuring a physical parameter. For example, the physical parameters may be temperature, pressure, and the like.
In operation, when the photodetector 100 is in operation, the source 50 and the drain 40 are connected to an external power source, which applies a fixed bias voltage between the source 50 and the drain 40. A positive gate voltage needs to be applied to the gate electrode 12 before a weak optical signal is incident. Illustratively, the bias voltage may be 1V, and the positive gate voltage may be 5V. Under the action of the positive gate voltage, electrons in the semiconductor channel 60 are injected into the charge trapping layer 20 by a Fowler-Nordheim tunneling mechanism. At this time, the current in the photodetector 100 is very small, about 1 pA.
When a weak optical signal is irradiated on the semiconductor channel 60, the positive gate voltage applied to the gate electrode 12 is first removed. Photo-generated electrons are generated in the back semiconductor channel 60 after removal and are transferred from the valence band 62 to the conduction band 61 by illumination, leaving the same number of photo-generated holes in the valence band 62 after the transfer. At this point, electrons in the charge trapping layer 20 may re-return through the tunneling insulating layer 30 into the semiconductor channel 60, recombining with the photo-generated holes in the semiconductor channel 60, as shown in fig. 2. At this time, the electrons that have transited to the conduction band 61 in the semiconductor channel 60 cannot return to the valence band 62 to recombine with the photo-generated holes, so that a stable photocurrent can be generated in the photodetector 100. Illustratively, when the illumination intensity is 50nw/cm-2When the light irradiation time was 0.1s, the photocurrent was about 10 nA.
When the weak light signal is removed, the positive gate voltage is applied to the gate 12 again, so that the electrons in the semiconductor channel 60 enter the charge trapping layer 20 again to prepare for the next weak light detection, and repeated use of the photodetector 100 is realized by this measure.
In one embodiment, the amount of bias between the source 50 and the drain 40 and the amount of positive gate voltage applied to the gate 12 may be adjusted according to the actual situation.
According to the technical scheme provided by the embodiment of the application, the electrons in the charge trapping layer 20 are used for filling the photo-generated holes, so that the recombination phenomenon of the photo-generated electron holes in the actual photoelectric conversion process can be effectively solved, and the situation that the transition speed of the electrons is lower than the recombination speed under the low-light condition is avoided, so that the effective photo-generated current can be generated in the photoelectric detector 100. The detection performance of the photoelectric detector 100 can be ensured by improving the detection sensitivity of the photoelectric detector 100 under the weak light condition without using a high-power light source or using an optical amplifier in a light path. The method does not increase the energy consumption and the use cost of the detection system, and does not make the structure of the detection system more complicated.
Meanwhile, in the embodiment, the detection performance of the photoelectric detector can be ensured without adding high-sensitivity devices such as a photomultiplier tube or an avalanche diode.
In the technical solution provided by the above embodiment of the present application, electrons in the semiconductor channel 60 can tunnel from the semiconductor channel 60 to the charge trapping layer 20 under the action of the positive gate voltage; electrons that tunnel to the charge trapping layer 20 after the positive gate voltage is removed cannot return to the semiconductor channel 60 and need to be stably stored in the charge trapping layer 20. In order to meet the above requirements, the thickness of the tunneling insulating layer 30 is limited in the present application, that is, the thickness of the tunneling insulating layer 30 is limited to 5 to 20 nanometers. Illustratively, the tunnel insulating layer 30 may have a thickness of 15 nanometers.
By the above measures, by providing the tunnel insulating layer 30 with an appropriate thickness, electrons can be stably present in the charge trap layer 20 or the semiconductor channel 60. When no grid voltage is applied or the light source is not incident, the electron transfer phenomenon can not be generated.
Fig. 3 is a schematic flow chart of a method for manufacturing a photodetector according to an embodiment of the present disclosure. Please refer to fig. 4, which is a flowchart illustrating a detailed process of step S240 according to an embodiment of the present application. Fig. 5 is a schematic view of a method for manufacturing a photodetector according to an embodiment of the present disclosure. Fig. 6 is a schematic view of a method for manufacturing a photodetector according to an embodiment of the present disclosure. Fig. 7 is a schematic view of a method for manufacturing a photodetector according to an embodiment of the present disclosure.
Referring to fig. 3, the method of fabricating the photodetector may include steps S210 to S240 as follows.
Step S210: and forming the grid electrode and the grid electrode insulating layer into a composite substrate.
Specifically, the gate insulating layer 11 may be deposited on the gate electrode 12, thereby forming the composite substrate 10.
Step S220: and forming a charge trapping layer on the upper surface of the gate insulating layer, wherein the charge trapping layer comprises a plurality of nanoparticles, and the nanoparticles are metal particles, oxide particles or semiconductor particles.
As shown in fig. 1, the charge trapping layer 20 is composed of a plurality of nanoparticles 21.
In an embodiment, when the nanoparticles 21 are metal particles, an intermediate layer may be deposited on the upper surface of the gate insulating layer 11, and a high temperature annealing process may be performed on the intermediate layer, so that a plurality of nanoparticles 21 are formed on the intermediate layer after the high temperature annealing, and the plurality of nanoparticles 21 form the charge trapping layer 20.
Illustratively, when the nanoparticles 21 are gold and the diameter of the nanoparticles 21 is 5 nm, a layer of gold 5 nm thick may be deposited on the upper surface of the gate insulating layer 11. After the deposition is completed, a gold layer is formed on the upper surface of the gate insulating layer 11. At this time, the composite substrate 10 with the gold layer may be placed in a vacuum material return furnace for high temperature annealing, and after the high temperature annealing, a plurality of nanoparticles 21 may be formed on the gold layer. The plurality of nanoparticles 21 constitute the charge trapping layer 20.
It can be seen that the thickness of the charge trapping layer 20 is the diameter of the nanoparticles 21.
For example, the annealing temperature of the high-temperature annealing may be 500 to 700 ℃.
In an embodiment, when the nanoparticles 21 are semiconductor particles or oxide particles, the semiconductor particles or oxide particles may be directly deposited on the upper surface of the gate insulating layer 11, and the charge trapping layer 20 may be directly formed on the upper surface of the gate insulating layer 11 after the deposition is finished.
It is seen that when the nanoparticles 21 are semiconductor particles or oxide particles, the charge trap layer 20 can be formed on the upper surface of the gate insulating layer 11 without performing an annealing process.
Step S230: a tunneling insulating layer is formed on an upper surface of the charge trapping layer.
After the charge trapping layer 20 is formed on the upper surface of the gate insulating layer 11, the tunneling insulating layer 30 may be deposited on the upper surface of the charge trapping layer 20.
For example, the tunnel insulating layer 30 may be made of an oxide material, and in this case, an insulating oxide film may be deposited on the upper surface of the charge trapping layer 20. A tunnel insulating layer 30 is formed on the upper surface of the charge trapping layer 20 after the deposition is completed.
Step S240: forming a source electrode, a drain electrode and a semiconductor channel on the upper surface of the tunneling insulating layer; the source and the drain are respectively positioned at two sides of the semiconductor channel.
Referring to fig. 4, step S240 may further include steps S241 to S246 as follows.
Step S241: and forming a semiconductor layer on the upper surface of the tunneling insulating layer.
Referring to fig. 5, after forming the tunnel insulating layer 30 on the upper surface of the charge trap layer 20, a semiconductor material may be deposited on the upper surface of the tunnel insulating layer 30, so that a semiconductor layer 63 is formed on the upper surface of the tunnel insulating layer 30.
Illustratively, when the semiconductor material is n-type indium gallium arsenide, the n-type indium gallium arsenide may be deposited on the upper surface of the tunneling insulating layer 30. After the deposition is completed, a semiconductor layer 63 is formed on the upper surface of the tunnel insulating layer 30.
Step S242: a photoresist layer is formed on an upper surface of the semiconductor layer.
Referring to fig. 5, after forming the semiconductor layer 63 on the upper surface of the tunneling insulating layer 30, a photoresist may be applied on the upper surface of the semiconductor layer 63 such that a photoresist layer 70 is formed on the upper surface of the semiconductor layer 63.
Step S243: and forming a mask layer by photoetching the photoresist layer.
Referring to fig. 6, after forming a photoresist layer 70 on the upper surface of the semiconductor layer 63, a mask layer 71 may be patterned by a uv photolithography process to define the source and drain electrodes 50 and 40 on the photoresist layer 70.
In one embodiment, the uv lithography process may be replaced with maskless lithography techniques such as e-beam lithography, laser direct writing, etc.
Step S244: and etching the semiconductor layer through the mask layer to form a first groove and a second groove.
Referring to fig. 7, after forming the mask layer 71, an etching process may be performed on the semiconductor layer 63 through the mask layer 71, that is, according to the pattern marks of the source electrode 50 and the drain electrode 40 in the mask layer 71, the etching process may be performed on the semiconductor layer, so that the first trench 41 and the second trench 51 are formed on the upper surface of the tunneling insulation layer 30, respectively. The positions of the first trench 41 and the second trench 51 are shown in fig. 7. The semiconductor layer 63 between the first trench 41 and the second trench 51 is a semiconductor channel 60.
Step S245: and forming a source electrode in the first groove and forming a drain electrode in the second groove, wherein the semiconductor layer between the source electrode and the drain electrode is a semiconductor channel.
After forming the first trench 41 and the second trench 51 on the upper surface of the tunnel insulating layer 30, the drain 40 may be deposited in the first trench 41, and the source 50 may be deposited in the second trench 51. Wherein the semiconductor layer 63 between the source electrode 50 and the drain electrode 40 is a semiconductor channel 60.
Illustratively, when the source electrode 50 and the drain electrode 40 are metal and the thickness of the source electrode 50 and the thickness of the drain electrode 40 are both 50 nanometers, 50 nanometers of metal may be deposited in the first trench 41 and 50 nanometers of metal may be deposited in the second trench 51. The source electrode 50 and the drain electrode 40 are generated in the above manner.
Step S246: and removing the mask layer.
Referring to fig. 7, after the source electrode 50 and the drain electrode 40 are obtained, the mask layer 71 on the upper surface of the semiconductor channel 60 needs to be removed, i.e., the semiconductor channel 60 needs to be subjected to a photoresist removing process.
After the binder removal, the fabrication of the photodetector 100 is completed.
In the present application, the deposition operations mentioned in the above embodiments may be performed by a semiconductor deposition process and a metal deposition process. Specifically, magnetron sputtering, thermal evaporation deposition, atomic layer deposition, liquid phase dispersion, and the like can be used.
It should be noted that the features of the embodiments in the present application may be combined with each other without conflict.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A photodetector, comprising:
a composite substrate; the composite substrate comprises a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged on the upper surface of the grid electrode;
the charge trapping layer is arranged on the upper surface of the gate insulating layer;
the tunneling insulating layer is arranged on the upper surface of the charge trapping layer;
the semiconductor channel is arranged on the upper surface of the tunneling insulating layer;
the source electrode is arranged on the upper surface of the tunneling insulating layer;
the drain electrode is arranged on the upper surface of the tunneling insulating layer;
the source electrode and the drain electrode are respectively positioned on two sides of the semiconductor channel, and the charge trapping layer comprises a plurality of nano particles.
2. The photodetector of claim 1, wherein the nanoparticles have a diameter of 1 to 30 nm.
3. The photodetector of claim 1, wherein the nanoparticles are metal particles, oxide particles, or semiconductor particles.
4. The photodetector of claim 1, wherein the nanoparticles, the source electrode and the drain electrode are made of the same material.
5. The photodetector of claim 4, wherein the nanoparticles, the source electrode and the drain electrode are all made of gold.
6. The photodetector as claimed in any one of claims 1 to 5, wherein the tunneling insulating layer has a thickness of 5 to 20 nm, and the gate insulating layer has a thickness of 30 to 300 nm.
7. The photodetector of any one of claims 1 to 5, wherein the tunneling insulating layer is made of alumina, silicon dioxide or silicon nitride;
the gate insulating layer is made of silicon dioxide, polystyrene or aluminum oxide;
the grid electrode is made of silicon, indium tin oxide, copper, gold or silver;
the semiconductor channel is made of silicon, gallium arsenide, n-type indium gallium arsenide or graphene.
8. A method of fabricating a photodetector, the method comprising:
forming a composite substrate by the grid and the grid insulating layer;
forming a charge trap layer on an upper surface of the gate insulating layer; wherein the charge trapping layer comprises a plurality of nanoparticles, the nanoparticles being metal particles, oxide particles or semiconductor particles;
forming a tunneling insulating layer on an upper surface of the charge trapping layer;
forming a source electrode, a drain electrode and a semiconductor channel on the upper surface of the tunneling insulating layer; the source electrode and the drain electrode are respectively positioned on two sides of the semiconductor channel.
9. The method of claim 8, wherein forming a charge trapping layer on an upper surface of the gate insulating layer comprises:
forming an intermediate layer on an upper surface of the gate insulating layer;
annealing the intermediate layer to form a plurality of nanoparticles, the plurality of nanoparticles constituting the charge trapping layer;
wherein the nanoparticles are metal particles.
10. The method of claim 8, wherein forming a source, a drain and a semiconductor channel on an upper surface of the tunneling insulating layer, the source and the drain being respectively located on two sides of the semiconductor channel comprises:
forming a semiconductor layer on the upper surface of the tunneling insulating layer;
forming a photoresist layer on the upper surface of the semiconductor layer;
photoetching the photoresist layer to form a mask layer;
etching the semiconductor layer through the mask layer to form a first groove and a second groove;
forming a source electrode in the first trench and a drain electrode in the second trench; the semiconductor layer between the source electrode and the drain electrode is the semiconductor channel;
and removing the mask layer.
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